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ad9625_fmc, ad9625x2_fmc: initial checkin

main
Rejeesh Kutty 2014-06-09 16:40:48 -04:00
parent 3e5990366e
commit 2d27f88588
16 changed files with 2248 additions and 0 deletions
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316
projects/ad9625_fmc/common/ad9625_fmc_bd.tcl Normal file
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# ad9625
if {$sys_zynq == 1} {
set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
} else {
set spi_csn_o [create_bd_port -dir O -from 1 -to 0 spi_csn_o]
set spi_csn_i [create_bd_port -dir I -from 1 -to 0 spi_csn_i]
}
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
set rx_sync [create_bd_port -dir O rx_sync]
set rx_sysref [create_bd_port -dir O rx_sysref]
set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p]
set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n]
if {$sys_zynq == 0} {
set gpio_ad9625_i [create_bd_port -dir I -from 1 -to 0 gpio_ad9625_i]
set gpio_ad9625_o [create_bd_port -dir O -from 1 -to 0 gpio_ad9625_o]
set gpio_ad9625_t [create_bd_port -dir O -from 1 -to 0 gpio_ad9625_t]
}
# adc peripherals
set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9625_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
set axi_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_gt
set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {256}] $axi_ad9625_dma
if {$sys_zynq == 1} {
set axi_ad9625_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9625_gt_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9625_gt_interconnect
set axi_ad9625_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9625_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9625_dma_interconnect
}
# spi
if {$sys_zynq == 0} {
set axi_ad9625_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_ad9625_gpio]
set_property -dict [list CONFIG.C_IS_DUAL {0}] $axi_ad9625_gpio
set_property -dict [list CONFIG.C_GPIO_WIDTH {2}] $axi_ad9625_gpio
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_ad9625_gpio
set axi_ad9625_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_ad9625_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9625_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $axi_ad9625_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9625_spi
}
# additions to default configuration
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property LEFT 16 [get_bd_ports GPIO_I]
set_property LEFT 16 [get_bd_ports GPIO_O]
set_property LEFT 16 [get_bd_ports GPIO_T]
} else {
set_property -dict [list CONFIG.NUM_MI {13}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_SI {10}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
delete_bd_objs [get_bd_nets sys_concat_intc_din_2]
delete_bd_objs [get_bd_ports unc_int2]
}
# connections (spi and gpio)
if {$sys_zynq == 1 } {
connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O]
connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
} else {
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9625_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9625_spi/ss_o]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9625_spi/sck_i]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9625_spi/sck_o]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9625_spi/io0_i]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9625_spi/io0_o]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9625_spi/io1_i]
connect_bd_net -net gpio_ad9625_i [get_bd_ports gpio_ad9625_i] [get_bd_pins axi_ad9625_gpio/gpio_io_i]
connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o]
connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t]
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
}
# connections (gt)
connect_bd_net -net axi_ad9625_gt_ref_clk_c [get_bd_pins axi_ad9625_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
connect_bd_net -net axi_ad9625_gt_rx_data_p [get_bd_pins axi_ad9625_gt/rx_data_p] [get_bd_ports rx_data_p]
connect_bd_net -net axi_ad9625_gt_rx_data_n [get_bd_pins axi_ad9625_gt/rx_data_n] [get_bd_ports rx_data_n]
connect_bd_net -net axi_ad9625_gt_rx_sync [get_bd_pins axi_ad9625_gt/rx_sync] [get_bd_ports rx_sync]
connect_bd_net -net axi_ad9625_gt_rx_sysref [get_bd_pins axi_ad9625_gt/rx_sysref] [get_bd_ports rx_sysref]
# connections (adc)
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins axi_ad9625_gt/rx_clk_g]
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins axi_ad9625_gt/rx_clk]
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins axi_ad9625_core/rx_clk]
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins axi_ad9625_jesd/rx_core_clk]
connect_bd_net -net axi_ad9625_gt_rx_rst [get_bd_pins axi_ad9625_gt/rx_rst]
connect_bd_net -net axi_ad9625_gt_rx_rst [get_bd_pins axi_ad9625_jesd/rx_reset]
connect_bd_net -net axi_ad9625_gt_rx_sysref [get_bd_pins axi_ad9625_jesd/rx_sysref]
connect_bd_net -net axi_ad9625_gt_rx_gt_charisk [get_bd_pins axi_ad9625_gt/rx_gt_charisk] [get_bd_pins axi_ad9625_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_ad9625_gt_rx_gt_disperr [get_bd_pins axi_ad9625_gt/rx_gt_disperr] [get_bd_pins axi_ad9625_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_ad9625_gt_rx_gt_notintable [get_bd_pins axi_ad9625_gt/rx_gt_notintable] [get_bd_pins axi_ad9625_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_ad9625_gt_rx_gt_data [get_bd_pins axi_ad9625_gt/rx_gt_data] [get_bd_pins axi_ad9625_jesd/gt_rxdata_in]
connect_bd_net -net axi_ad9625_gt_rx_rst_done [get_bd_pins axi_ad9625_gt/rx_rst_done] [get_bd_pins axi_ad9625_jesd/rx_reset_done]
connect_bd_net -net axi_ad9625_gt_rx_ip_comma_align [get_bd_pins axi_ad9625_gt/rx_ip_comma_align] [get_bd_pins axi_ad9625_jesd/rxencommaalign_out]
connect_bd_net -net axi_ad9625_gt_rx_ip_sync [get_bd_pins axi_ad9625_gt/rx_ip_sync] [get_bd_pins axi_ad9625_jesd/rx_sync]
connect_bd_net -net axi_ad9625_gt_rx_ip_sof [get_bd_pins axi_ad9625_gt/rx_ip_sof] [get_bd_pins axi_ad9625_jesd/rx_start_of_frame]
connect_bd_net -net axi_ad9625_gt_rx_ip_data [get_bd_pins axi_ad9625_gt/rx_ip_data] [get_bd_pins axi_ad9625_jesd/rx_tdata]
connect_bd_net -net axi_ad9625_gt_rx_data [get_bd_pins axi_ad9625_gt/rx_data] [get_bd_pins axi_ad9625_core/rx_data]
connect_bd_net -net axi_ad9625_adc_clk [get_bd_pins axi_ad9625_core/adc_clk] [get_bd_pins axi_ad9625_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9625_adc_dwr [get_bd_pins axi_ad9625_core/adc_dwr] [get_bd_pins axi_ad9625_dma/fifo_wr_en]
connect_bd_net -net axi_ad9625_adc_dsync [get_bd_pins axi_ad9625_core/adc_dsync] [get_bd_pins axi_ad9625_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins axi_ad9625_core/adc_ddata] [get_bd_pins axi_ad9625_dma/fifo_wr_din]
connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9625_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9625_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9625_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9625_gt/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_dma/s_axi_aresetn]
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9625_spi/axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9625_gpio/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gpio/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/ext_spi_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_spi/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gpio/s_axi_aresetn]
}
# interconnect (gt es)
if {$sys_zynq == 1} {
connect_bd_intf_net -intf_net axi_ad9625_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad9625_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9625_gt/m_axi]
connect_bd_intf_net -intf_net axi_ad9625_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad9625_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
} else {
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9625_gt/m_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
}
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt/m_axi_aresetn]
# interconnect (dma)
if {$sys_zynq == 1} {
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
connect_bd_intf_net -intf_net axi_ad9625_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9625_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_intf_net -intf_net axi_ad9625_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9625_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9625_dma/m_dest_axi]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma/m_dest_axi_aresetn]
} else {
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9625_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9625_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9625_dma/m_dest_axi_aresetn]
}
# ila
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {256}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_jesd_rx_mon
connect_bd_net -net axi_ad9625_gt_rx_mon_data [get_bd_pins axi_ad9625_gt/rx_mon_data]
connect_bd_net -net axi_ad9625_gt_rx_mon_trigger [get_bd_pins axi_ad9625_gt/rx_mon_trigger]
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_ad9625_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
connect_bd_net -net axi_ad9625_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
connect_bd_net -net axi_ad9625_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_core/s_axi/axi_lite] SEG_data_ad9625_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_gt/s_axi/axi_lite] SEG_data_ad9625_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_jesd/s_axi/Reg] SEG_data_ad9625_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_dma/s_axi/axi_lite] SEG_data_ad9625_dma
if {$sys_zynq == 0} {
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_spi/axi_lite/Reg] SEG_data_ad9625_spi
create_bd_addr_seg -range 0x00010000 -offset 0x40030000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ad9625_gpio/s_axi/Reg] SEG_data_gpio_3
}
if {$sys_zynq == 1} {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9625_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
} else {
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
}

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9625_fmc_spi (
spi_adc_csn,
spi_clk_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_adc_sdio,
spi_clk_sdio);
// 4 wire
input spi_adc_csn;
input spi_clk_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_adc_sdio;
inout spi_clk_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
wire spi_adc_miso_s;
wire spi_clk_miso_s;
// check on rising edge and change on falling edge
assign spi_csn_s = spi_adc_csn & spi_clk_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
assign spi_miso = ((spi_adc_miso_s & ~spi_adc_csn) | (spi_clk_miso_s & ~spi_clk_csn));
// io butter
IOBUF i_iobuf_adc_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_adc_miso_s),
.IO (spi_adc_sdio));
IOBUF i_iobuf_clk_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_clk_miso_s),
.IO (spi_clk_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************

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source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source ../common/ad9625_fmc_bd.tcl

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# ad9625
set_property -dict {PACKAGE_PIN A10 } [get_ports rx_ref_clk_p] ; ## D04 FMC1_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN A9 } [get_ports rx_ref_clk_n] ; ## D05 FMC1_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN D8 } [get_ports rx_data_p[0]] ; ## C06 FMC1_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN D7 } [get_ports rx_data_n[0]] ; ## C07 FMC1_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN C6 } [get_ports rx_data_p[1]] ; ## A02 FMC1_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN C5 } [get_ports rx_data_n[1]] ; ## A03 FMC1_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN B8 } [get_ports rx_data_p[2]] ; ## A06 FMC1_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN B7 } [get_ports rx_data_n[2]] ; ## A07 FMC1_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN A6 } [get_ports rx_data_p[3]] ; ## A10 FMC1_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN A5 } [get_ports rx_data_n[3]] ; ## A11 FMC1_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN E6 } [get_ports rx_data_p[4]] ; ## B12 FMC1_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN E5 } [get_ports rx_data_n[4]] ; ## B13 FMC1_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN H8 } [get_ports rx_data_p[5]] ; ## A14 FMC1_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN H7 } [get_ports rx_data_n[5]] ; ## A15 FMC1_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN F8 } [get_ports rx_data_p[6]] ; ## B16 FMC1_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN F7 } [get_ports rx_data_n[6]] ; ## B17 FMC1_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN G6 } [get_ports rx_data_p[7]] ; ## A18 FMC1_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN G5 } [get_ports rx_data_n[7]] ; ## A19 FMC1_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## H10 FMC1_HPC_LA04_P
set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## H11 FMC1_HPC_LA04_N
set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D11 FMC1_HPC_LA05_P
set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D12 FMC1_HPC_LA05_N
set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports spi_adc_csn] ; ## H08 FMC1_HPC_LA02_N
set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVCMOS18} [get_ports spi_adc_clk] ; ## D08 FMC1_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVCMOS18} [get_ports spi_adc_sdio] ; ## D09 FMC1_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports spi_clk_csn] ; ## H07 FMC1_HPC_LA02_P
set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVCMOS18} [get_ports spi_clk_clk] ; ## G06 FMC1_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVCMOS18} [get_ports spi_clk_sdio] ; ## G07 FMC1_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports adc_irq] ; ## G09 FMC1_HPC_LA03_P
set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd] ; ## G10 FMC1_HPC_LA03_N
# clocks
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_nets i_system_wrapper/system_i/axi_ad9625_gt_rx_clk]
set_clock_groups -asynchronous -group {rx_div_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create ad9625_fmc_vc707
adi_project_files ad9625_fmc_vc707 [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"../common/ad9625_fmc_spi.v" \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
adi_project_run ad9625_fmc_vc707

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
sgmii_rxp,
sgmii_rxn,
sgmii_txp,
sgmii_txn,
phy_rstn,
mgt_clk_p,
mgt_clk_n,
mdio_mdc,
mdio_mdio,
fan_pwm,
gpio_lcd,
gpio_led,
gpio_sw,
iic_rstn,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_data_p,
rx_data_n,
adc_irq,
adc_fd,
spi_adc_csn,
spi_adc_clk,
spi_adc_sdio,
spi_clk_csn,
spi_clk_clk,
spi_clk_sdio);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
input sgmii_rxp;
input sgmii_rxn;
output sgmii_txp;
output sgmii_txn;
output phy_rstn;
input mgt_clk_p;
input mgt_clk_n;
output mdio_mdc;
inout mdio_mdio;
output fan_pwm;
output [ 6:0] gpio_lcd;
output [ 7:0] gpio_led;
input [12:0] gpio_sw;
output iic_rstn;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [35:0] hdmi_data;
output spdif;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 7:0] rx_data_p;
input [ 7:0] rx_data_n;
inout adc_irq;
inout adc_fd;
output spi_adc_csn;
output spi_adc_clk;
inout spi_adc_sdio;
output spi_clk_csn;
output spi_clk_clk;
inout spi_clk_sdio;
// internal signals
wire [1:0] gpio_i;
wire [1:0] gpio_o;
wire [1:0] gpio_t;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire spi_clk;
wire spi_miso;
wire spi_mosi;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf (
.dt (gpio_t),
.di (gpio_o),
.do (gpio_i),
.dio ({ adc_irq, // 1
adc_fd})); // 0
assign spi_adc_clk = spi_clk;
assign spi_clk_clk = spi_clk;
ad9625_fmc_spi i_ad9625_fmc_spi (
.spi_adc_csn (spi_adc_csn),
.spi_clk_csn (spi_clk_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_adc_sdio (spi_adc_sdio),
.spi_clk_sdio (spi_clk_sdio));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.fan_pwm (fan_pwm),
.gpio_lcd_tri_o (gpio_lcd),
.gpio_led_tri_o (gpio_led),
.gpio_sw_tri_i (gpio_sw),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.iic_rstn (iic_rstn),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.gpio_ad9625_i (gpio_i),
.gpio_ad9625_o (gpio_o),
.gpio_ad9625_t (gpio_t),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (1'b1),
.spi_csn_o ({spi_clk_csn, spi_adc_csn}),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
source ../common/ad9625_fmc_bd.tcl
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
p_plddr3_fifo [current_bd_instance .] plddr3_fifo 256
set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3]
set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk]
connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3]
connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk]
delete_bd_objs [get_bd_nets axi_ad9625_adc_clk]
delete_bd_objs [get_bd_nets axi_ad9625_adc_dwr]
delete_bd_objs [get_bd_nets axi_ad9625_adc_ddata]
delete_bd_objs [get_bd_nets axi_ad9625_adc_dovf]
delete_bd_objs [get_bd_nets axi_ad9625_adc_dsync]
connect_bd_net -net [get_bd_nets axi_ad9625_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_ad9625_gt/rx_rst]
connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_ps7/FCLK_RESET2_N]
connect_bd_net -net axi_ad9625_adc_clk [get_bd_pins axi_ad9625_core/adc_clk] [get_bd_pins plddr3_fifo/adc_clk]
connect_bd_net -net axi_ad9625_adc_dwr [get_bd_pins axi_ad9625_core/adc_dwr] [get_bd_pins plddr3_fifo/adc_wr]
connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins axi_ad9625_core/adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata]
connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf]
connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins plddr3_fifo/axi_xfer_req]
connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9625_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9625_dma/fifo_wr_en]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/fifo_wr_din]
connect_bd_net -net axi_ad9625_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9625_adc_dsync [get_bd_pins axi_ad9625_core/adc_dsync] [get_bd_pins axi_ad9625_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon
connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins ila_dma_mon/clk]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins ila_dma_mon/probe0]
connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins ila_dma_mon/probe1]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins ila_dma_mon/probe2]
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr

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# ad9625
set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[4]] ; ## B12 FMC_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[4]] ; ## B13 FMC_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[5]] ; ## A14 FMC_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[5]] ; ## A15 FMC_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[6]] ; ## B16 FMC_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[6]] ; ## B17 FMC_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[7]] ; ## A18 FMC_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[7]] ; ## A19 FMC_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports spi_adc_csn] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports spi_adc_clk] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports spi_adc_sdio] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_clk_csn] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports spi_clk_clk] ; ## G06 FMC_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS25} [get_ports spi_clk_sdio] ; ## G07 FMC_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_irq] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fd] ; ## G10 FMC_HPC_LA03_N
# clocks
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_nets i_system_wrapper/system_i/axi_ad9625_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create ad9625_fmc_zc706
adi_project_files ad9625_fmc_zc706 [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"../common/ad9625_fmc_spi.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run ad9625_fmc_zc706

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR3_addr,
DDR3_ba,
DDR3_cas_n,
DDR3_ck_n,
DDR3_ck_p,
DDR3_cke,
DDR3_cs_n,
DDR3_dm,
DDR3_dq,
DDR3_dqs_n,
DDR3_dqs_p,
DDR3_odt,
DDR3_ras_n,
DDR3_reset_n,
DDR3_we_n,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
sys_clk_p,
sys_clk_n,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_data_p,
rx_data_n,
adc_irq,
adc_fd,
spi_adc_csn,
spi_adc_clk,
spi_adc_sdio,
spi_clk_csn,
spi_clk_clk,
spi_clk_sdio);
output [13:0] DDR3_addr;
output [ 2:0] DDR3_ba;
output DDR3_cas_n;
output [ 0:0] DDR3_ck_n;
output [ 0:0] DDR3_ck_p;
output [ 0:0] DDR3_cke;
output [ 0:0] DDR3_cs_n;
output [ 7:0] DDR3_dm;
inout [63:0] DDR3_dq;
inout [ 7:0] DDR3_dqs_n;
inout [ 7:0] DDR3_dqs_p;
output [ 0:0] DDR3_odt;
output DDR3_ras_n;
output DDR3_reset_n;
output DDR3_we_n;
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [14:0] gpio_bd;
input sys_clk_p;
input sys_clk_n;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 7:0] rx_data_p;
input [ 7:0] rx_data_n;
inout adc_irq;
inout adc_fd;
output spi_adc_csn;
output spi_adc_clk;
inout spi_adc_sdio;
output spi_clk_csn;
output spi_clk_clk;
inout spi_clk_sdio;
// internal signals
wire [16:0] gpio_i;
wire [16:0] gpio_o;
wire [16:0] gpio_t;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire spi_clk;
wire spi_miso;
wire spi_mosi;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dt (gpio_t),
.di (gpio_o),
.do (gpio_i),
.dio ({ adc_irq, // 16
adc_fd, // 15
gpio_bd})); // 0
assign spi_adc_clk = spi_clk;
assign spi_clk_clk = spi_clk;
ad9625_fmc_spi i_ad9625_fmc_spi (
.spi_adc_csn (spi_adc_csn),
.spi_clk_csn (spi_clk_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_adc_sdio (spi_adc_sdio),
.spi_clk_sdio (spi_clk_sdio));
system_wrapper i_system_wrapper (
.DDR3_addr (DDR3_addr),
.DDR3_ba (DDR3_ba),
.DDR3_cas_n (DDR3_cas_n),
.DDR3_ck_n (DDR3_ck_n),
.DDR3_ck_p (DDR3_ck_p),
.DDR3_cke (DDR3_cke),
.DDR3_cs_n (DDR3_cs_n),
.DDR3_dm (DDR3_dm),
.DDR3_dq (DDR3_dq),
.DDR3_dqs_n (DDR3_dqs_n),
.DDR3_dqs_p (DDR3_dqs_p),
.DDR3_odt (DDR3_odt),
.DDR3_ras_n (DDR3_ras_n),
.DDR3_reset_n (DDR3_reset_n),
.DDR3_we_n (DDR3_we_n),
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (1'b1),
.spi_csn_0_o (spi_adc_csn),
.spi_csn_1_o (spi_clk_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

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# ad9625
set spi_csn_o [create_bd_port -dir O -from 1 -to 0 spi_csn_o]
set spi_csn_i [create_bd_port -dir I -from 1 -to 0 spi_csn_i]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
set rx_ref_clk_0 [create_bd_port -dir I rx_ref_clk_0]
set rx_data_0_p [create_bd_port -dir I -from 7 -to 0 rx_data_0_p]
set rx_data_0_n [create_bd_port -dir I -from 7 -to 0 rx_data_0_n]
set rx_sync_0 [create_bd_port -dir O rx_sync_0]
set rx_ref_clk_1 [create_bd_port -dir I rx_ref_clk_1]
set rx_data_1_p [create_bd_port -dir I -from 7 -to 0 rx_data_1_p]
set rx_data_1_n [create_bd_port -dir I -from 7 -to 0 rx_data_1_n]
set rx_sync_1 [create_bd_port -dir O rx_sync_1]
set rx_sysref [create_bd_port -dir O rx_sysref]
set gpio_ad9625_i [create_bd_port -dir I -from 18 -to 0 gpio_ad9625_i]
set gpio_ad9625_o [create_bd_port -dir O -from 18 -to 0 gpio_ad9625_o]
set gpio_ad9625_t [create_bd_port -dir O -from 18 -to 0 gpio_ad9625_t]
set gt_rx_clk [create_bd_port -dir O gt_rx_clk]
set gt_rx_data_0 [create_bd_port -dir O -from 255 -to 0 gt_rx_data_0]
set gt_rx_data_1 [create_bd_port -dir O -from 255 -to 0 gt_rx_data_1]
set core_rx_data_0 [create_bd_port -dir I -from 255 -to 0 core_rx_data_0]
set core_rx_data_1 [create_bd_port -dir I -from 255 -to 0 core_rx_data_1]
set core_dwr_0 [create_bd_port -dir O core_dwr_0]
set core_ddata_0 [create_bd_port -dir O -from 255 -to 0 core_ddata_0]
set core_dovf_0 [create_bd_port -dir I core_dovf_0]
set core_dwr_1 [create_bd_port -dir O core_dwr_1]
set core_ddata_1 [create_bd_port -dir O -from 255 -to 0 core_ddata_1]
set core_dovf_1 [create_bd_port -dir I core_dovf_1]
set adc_dwr [create_bd_port -dir I adc_dwr]
set adc_dsync [create_bd_port -dir I adc_dsync]
set adc_ddata [create_bd_port -dir I -from 511 -to 0 adc_ddata]
set adc_dovf [create_bd_port -dir O adc_dovf]
# adc peripherals
set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core]
set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9625_0_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd
set axi_ad9625_0_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_0_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_ad9625_0_gt
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_0_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_0_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_0_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_0_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_0_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_0_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_0_gt
set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9625_1_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd
set axi_ad9625_1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_1_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_ad9625_1_gt
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_1_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_1_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_1_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_1_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_1_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_1_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_1_gt
set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {512}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {512}] $axi_ad9625_dma
set axi_ad9625_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_ad9625_gpio]
set_property -dict [list CONFIG.C_IS_DUAL {0}] $axi_ad9625_gpio
set_property -dict [list CONFIG.C_GPIO_WIDTH {19}] $axi_ad9625_gpio
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_ad9625_gpio
set axi_ad9625_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_ad9625_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9625_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $axi_ad9625_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9625_spi
# additions to default configuration
set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
delete_bd_objs [get_bd_nets sys_concat_intc_din_2]
delete_bd_objs [get_bd_ports unc_int2]
# connections (spi and gpio)
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9625_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9625_spi/ss_o]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9625_spi/sck_i]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9625_spi/sck_o]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9625_spi/io0_i]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9625_spi/io0_o]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9625_spi/io1_i]
connect_bd_net -net gpio_ad9625_i [get_bd_ports gpio_ad9625_i] [get_bd_pins axi_ad9625_gpio/gpio_io_i]
connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o]
connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t]
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
# connections (gt)
connect_bd_net -net axi_ad9625_0_gt_ref_clk_c [get_bd_pins axi_ad9625_0_gt/ref_clk_c] [get_bd_ports rx_ref_clk_0]
connect_bd_net -net axi_ad9625_0_gt_rx_data_p [get_bd_pins axi_ad9625_0_gt/rx_data_p] [get_bd_ports rx_data_0_p]
connect_bd_net -net axi_ad9625_0_gt_rx_data_n [get_bd_pins axi_ad9625_0_gt/rx_data_n] [get_bd_ports rx_data_0_n]
connect_bd_net -net axi_ad9625_0_gt_rx_sync [get_bd_pins axi_ad9625_0_gt/rx_sync] [get_bd_ports rx_sync_0]
connect_bd_net -net axi_ad9625_0_gt_rx_sysref [get_bd_pins axi_ad9625_0_gt/rx_sysref] [get_bd_ports rx_sysref]
connect_bd_net -net axi_ad9625_1_gt_ref_clk_c [get_bd_pins axi_ad9625_1_gt/ref_clk_c] [get_bd_ports rx_ref_clk_1]
connect_bd_net -net axi_ad9625_1_gt_rx_data_p [get_bd_pins axi_ad9625_1_gt/rx_data_p] [get_bd_ports rx_data_1_p]
connect_bd_net -net axi_ad9625_1_gt_rx_data_n [get_bd_pins axi_ad9625_1_gt/rx_data_n] [get_bd_ports rx_data_1_n]
connect_bd_net -net axi_ad9625_1_gt_rx_sync [get_bd_pins axi_ad9625_1_gt/rx_sync] [get_bd_ports rx_sync_1]
# connections (adc)
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_gt/rx_clk_g]
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_0_gt/rx_rst]
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_gt/rx_clk]
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_core/rx_clk]
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_0_jesd/rx_core_clk]
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_0_jesd/rx_reset]
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_1_gt/rx_clk]
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_1_core/rx_clk]
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_1_jesd/rx_core_clk]
connect_bd_net -net axi_ad9625_0_gt_rx_rst [get_bd_pins axi_ad9625_1_jesd/rx_reset]
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins axi_ad9625_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_ports gt_rx_clk]
connect_bd_net -net axi_ad9625_0_gt_rx_sysref [get_bd_pins axi_ad9625_0_jesd/rx_sysref]
connect_bd_net -net axi_ad9625_0_gt_rx_sysref [get_bd_pins axi_ad9625_1_jesd/rx_sysref]
connect_bd_net -net axi_ad9625_0_gt_rx_gt_charisk [get_bd_pins axi_ad9625_0_gt/rx_gt_charisk] [get_bd_pins axi_ad9625_0_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_ad9625_0_gt_rx_gt_disperr [get_bd_pins axi_ad9625_0_gt/rx_gt_disperr] [get_bd_pins axi_ad9625_0_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_ad9625_0_gt_rx_gt_notintable [get_bd_pins axi_ad9625_0_gt/rx_gt_notintable] [get_bd_pins axi_ad9625_0_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_ad9625_0_gt_rx_gt_data [get_bd_pins axi_ad9625_0_gt/rx_gt_data] [get_bd_pins axi_ad9625_0_jesd/gt_rxdata_in]
connect_bd_net -net axi_ad9625_0_gt_rx_rst_done [get_bd_pins axi_ad9625_0_gt/rx_rst_done] [get_bd_pins axi_ad9625_0_jesd/rx_reset_done]
connect_bd_net -net axi_ad9625_0_gt_rx_ip_comma_align [get_bd_pins axi_ad9625_0_gt/rx_ip_comma_align] [get_bd_pins axi_ad9625_0_jesd/rxencommaalign_out]
connect_bd_net -net axi_ad9625_0_gt_rx_ip_sync [get_bd_pins axi_ad9625_0_gt/rx_ip_sync] [get_bd_pins axi_ad9625_0_jesd/rx_sync]
connect_bd_net -net axi_ad9625_0_gt_rx_ip_sof [get_bd_pins axi_ad9625_0_gt/rx_ip_sof] [get_bd_pins axi_ad9625_0_jesd/rx_start_of_frame]
connect_bd_net -net axi_ad9625_0_gt_rx_ip_data [get_bd_pins axi_ad9625_0_gt/rx_ip_data] [get_bd_pins axi_ad9625_0_jesd/rx_tdata]
connect_bd_net -net axi_ad9625_1_gt_rx_gt_charisk [get_bd_pins axi_ad9625_1_gt/rx_gt_charisk] [get_bd_pins axi_ad9625_1_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_ad9625_1_gt_rx_gt_disperr [get_bd_pins axi_ad9625_1_gt/rx_gt_disperr] [get_bd_pins axi_ad9625_1_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_ad9625_1_gt_rx_gt_notintable [get_bd_pins axi_ad9625_1_gt/rx_gt_notintable] [get_bd_pins axi_ad9625_1_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_ad9625_1_gt_rx_gt_data [get_bd_pins axi_ad9625_1_gt/rx_gt_data] [get_bd_pins axi_ad9625_1_jesd/gt_rxdata_in]
connect_bd_net -net axi_ad9625_1_gt_rx_rst_done [get_bd_pins axi_ad9625_1_gt/rx_rst_done] [get_bd_pins axi_ad9625_1_jesd/rx_reset_done]
connect_bd_net -net axi_ad9625_1_gt_rx_ip_comma_align [get_bd_pins axi_ad9625_1_gt/rx_ip_comma_align] [get_bd_pins axi_ad9625_1_jesd/rxencommaalign_out]
connect_bd_net -net axi_ad9625_1_gt_rx_ip_sync [get_bd_pins axi_ad9625_1_gt/rx_ip_sync] [get_bd_pins axi_ad9625_1_jesd/rx_sync]
connect_bd_net -net axi_ad9625_1_gt_rx_ip_sof [get_bd_pins axi_ad9625_1_gt/rx_ip_sof] [get_bd_pins axi_ad9625_1_jesd/rx_start_of_frame]
connect_bd_net -net axi_ad9625_1_gt_rx_ip_data [get_bd_pins axi_ad9625_1_gt/rx_ip_data] [get_bd_pins axi_ad9625_1_jesd/rx_tdata]
connect_bd_net -net axi_ad9625_0_gt_rx_data [get_bd_pins axi_ad9625_0_gt/rx_data] [get_bd_ports gt_rx_data_0]
connect_bd_net -net axi_ad9625_1_gt_rx_data [get_bd_pins axi_ad9625_1_gt/rx_data] [get_bd_ports gt_rx_data_1]
connect_bd_net -net axi_ad9625_0_core_rx_data [get_bd_pins axi_ad9625_0_core/rx_data] [get_bd_ports core_rx_data_0]
connect_bd_net -net axi_ad9625_1_core_rx_data [get_bd_pins axi_ad9625_1_core/rx_data] [get_bd_ports core_rx_data_1]
connect_bd_net -net axi_ad9625_0_core_adc_dwr [get_bd_pins axi_ad9625_0_core/adc_dwr] [get_bd_ports core_dwr_0]
connect_bd_net -net axi_ad9625_0_core_adc_ddata [get_bd_pins axi_ad9625_0_core/adc_ddata] [get_bd_ports core_ddata_0]
connect_bd_net -net axi_ad9625_0_core_adc_dovf [get_bd_pins axi_ad9625_0_core/adc_dovf] [get_bd_ports core_dovf_0]
connect_bd_net -net axi_ad9625_1_core_adc_dwr [get_bd_pins axi_ad9625_1_core/adc_dwr] [get_bd_ports core_dwr_1]
connect_bd_net -net axi_ad9625_1_core_adc_ddata [get_bd_pins axi_ad9625_1_core/adc_ddata] [get_bd_ports core_ddata_1]
connect_bd_net -net axi_ad9625_1_core_adc_dovf [get_bd_pins axi_ad9625_1_core/adc_dovf] [get_bd_ports core_dovf_1]
connect_bd_net -net axi_ad9625_dma_adc_dwr [get_bd_pins axi_ad9625_dma/fifo_wr_en] [get_bd_ports adc_dwr]
connect_bd_net -net axi_ad9625_dma_adc_dsync [get_bd_pins axi_ad9625_dma/fifo_wr_sync] [get_bd_ports adc_dsync]
connect_bd_net -net axi_ad9625_dma_adc_ddata [get_bd_pins axi_ad9625_dma/fifo_wr_din] [get_bd_ports adc_ddata]
connect_bd_net -net axi_ad9625_dma_adc_dovf [get_bd_pins axi_ad9625_dma/fifo_wr_overflow] [get_bd_ports adc_dovf]
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9625_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9625_0_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9625_0_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9625_0_gt/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9625_spi/axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9625_gpio/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_ad9625_1_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_ad9625_1_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_ad9625_1_gt/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/ext_spi_clk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gpio/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_spi/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gpio/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_jesd/s_axi_aresetn]
# interconnect (gt es)
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9625_0_gt/m_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9625_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9625_1_gt/m_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_0_gt/drp_clk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9625_dma/m_dest_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_1_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_0_gt/m_axi_aresetn]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9625_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_1_gt/m_axi_aresetn]
# ila
set ila_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_rx_mon]
# set_property -dict [list CONFIG.C_NUM_OF_PROBES {7}] $ila_rx_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {256}] $ila_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {256}] $ila_rx_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {512}] $ila_rx_mon
# set_property -dict [list CONFIG.C_PROBE3_WIDTH {10}] $ila_rx_mon
# set_property -dict [list CONFIG.C_PROBE4_WIDTH {662}] $ila_rx_mon
# set_property -dict [list CONFIG.C_PROBE5_WIDTH {10}] $ila_rx_mon
# set_property -dict [list CONFIG.C_PROBE6_WIDTH {662}] $ila_rx_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_rx_mon
set_property -dict [list CONFIG.C_PROBE4_WIDTH {4}] $ila_rx_mon
set_property -dict [list CONFIG.C_PROBE5_WIDTH {256}] $ila_rx_mon
set_property -dict [list CONFIG.C_PROBE6_WIDTH {1}] $ila_rx_mon
set_property -dict [list CONFIG.C_PROBE7_WIDTH {4}] $ila_rx_mon
set_property -dict [list CONFIG.C_PROBE8_WIDTH {256}] $ila_rx_mon
connect_bd_net -net axi_ad9625_0_gt_rx_clk [get_bd_pins ila_rx_mon/CLK]
connect_bd_net -net axi_ad9625_0_core_rx_data [get_bd_pins ila_rx_mon/probe0]
connect_bd_net -net axi_ad9625_1_core_rx_data [get_bd_pins ila_rx_mon/probe1]
connect_bd_net -net axi_ad9625_dma_adc_ddata [get_bd_pins ila_rx_mon/probe2]
connect_bd_net -net axi_ad9625_0_gt_rx_ip_comma_align [get_bd_pins ila_rx_mon/probe3]
connect_bd_net -net axi_ad9625_0_gt_rx_ip_sof [get_bd_pins ila_rx_mon/probe4]
connect_bd_net -net axi_ad9625_0_gt_rx_ip_data [get_bd_pins ila_rx_mon/probe5]
connect_bd_net -net axi_ad9625_1_gt_rx_ip_comma_align [get_bd_pins ila_rx_mon/probe6]
connect_bd_net -net axi_ad9625_1_gt_rx_ip_sof [get_bd_pins ila_rx_mon/probe7]
connect_bd_net -net axi_ad9625_1_gt_rx_ip_data [get_bd_pins ila_rx_mon/probe8]
# connect_bd_net -net axi_ad9625_0_gt_rx_mon_trigger [get_bd_pins axi_ad9625_0_gt/rx_mon_trigger] [get_bd_pins ila_rx_mon/probe3]
# connect_bd_net -net axi_ad9625_0_gt_rx_mon_data [get_bd_pins axi_ad9625_0_gt/rx_mon_data] [get_bd_pins ila_rx_mon/probe4]
# connect_bd_net -net axi_ad9625_1_gt_rx_mon_trigger [get_bd_pins axi_ad9625_1_gt/rx_mon_trigger] [get_bd_pins ila_rx_mon/probe5]
# connect_bd_net -net axi_ad9625_1_gt_rx_mon_data [get_bd_pins axi_ad9625_1_gt/rx_mon_data] [get_bd_pins ila_rx_mon/probe6]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x44a10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_0_core/s_axi/axi_lite] SEG_data_ad9625_0_core
create_bd_addr_seg -range 0x00010000 -offset 0x44a60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_0_gt/s_axi/axi_lite] SEG_data_ad9625_0_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44a91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_0_jesd/s_axi/Reg] SEG_data_ad9625_0_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x44b10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_1_core/s_axi/axi_lite] SEG_data_ad9625_1_core
create_bd_addr_seg -range 0x00010000 -offset 0x44b60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_1_gt/s_axi/axi_lite] SEG_data_ad9625_1_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44b91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_1_jesd/s_axi/Reg] SEG_data_ad9625_1_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_dma/s_axi/axi_lite] SEG_data_ad9625_dma
create_bd_addr_seg -range 0x00010000 -offset 0x44a70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_spi/axi_lite/Reg] SEG_data_ad9625_spi
create_bd_addr_seg -range 0x00010000 -offset 0x40030000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_gpio/s_axi/Reg] SEG_data_ad9625_gpio
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_0_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_1_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9625x2_fmc_spi (
spi_csn_0,
spi_csn_1,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio,
spi_dirn);
// 4 wire
input spi_csn_0;
input spi_csn_1;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
output spi_dirn;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = spi_csn_0 & spi_csn_1;
assign spi_dirn = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************

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source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source ../common/ad9625x2_fmc_bd.tcl

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# ad9625
set_property -dict {PACKAGE_PIN A10 } [get_ports rx_ref_clk_0_p] ; ## D04 FMC1_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN A9 } [get_ports rx_ref_clk_0_n] ; ## D05 FMC1_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN G6 } [get_ports rx_data_0_p[0]] ; ## A18 FMC1_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN G5 } [get_ports rx_data_0_n[0]] ; ## A19 FMC1_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN F8 } [get_ports rx_data_0_p[1]] ; ## B16 FMC1_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN F7 } [get_ports rx_data_0_n[1]] ; ## B17 FMC1_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN H8 } [get_ports rx_data_0_p[2]] ; ## A14 FMC1_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN H7 } [get_ports rx_data_0_n[2]] ; ## A15 FMC1_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN E6 } [get_ports rx_data_0_p[3]] ; ## B12 FMC1_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN E5 } [get_ports rx_data_0_n[3]] ; ## B13 FMC1_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN A6 } [get_ports rx_data_0_p[4]] ; ## A10 FMC1_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN A5 } [get_ports rx_data_0_n[4]] ; ## A11 FMC1_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN B8 } [get_ports rx_data_0_p[5]] ; ## A06 FMC1_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN B7 } [get_ports rx_data_0_n[5]] ; ## A07 FMC1_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN D8 } [get_ports rx_data_0_p[6]] ; ## C06 FMC1_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN D7 } [get_ports rx_data_0_n[6]] ; ## C07 FMC1_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN C6 } [get_ports rx_data_0_p[7]] ; ## A02 FMC1_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN C5 } [get_ports rx_data_0_n[7]] ; ## A03 FMC1_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN K8 } [get_ports rx_ref_clk_1_p] ; ## D04 FMC2_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN K7 } [get_ports rx_ref_clk_1_n] ; ## D05 FMC2_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN V4 } [get_ports rx_data_1_p[0]] ; ## A18 FMC2_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN V3 } [get_ports rx_data_1_n[0]] ; ## A19 FMC2_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN U6 } [get_ports rx_data_1_p[1]] ; ## B16 FMC2_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN U5 } [get_ports rx_data_1_n[1]] ; ## B17 FMC2_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN W6 } [get_ports rx_data_1_p[2]] ; ## A14 FMC2_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN W5 } [get_ports rx_data_1_n[2]] ; ## A15 FMC2_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN R6 } [get_ports rx_data_1_p[3]] ; ## B12 FMC2_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN R5 } [get_ports rx_data_1_n[3]] ; ## B13 FMC2_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN J6 } [get_ports rx_data_1_p[4]] ; ## A10 FMC2_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN J5 } [get_ports rx_data_1_n[4]] ; ## A11 FMC2_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN L6 } [get_ports rx_data_1_p[5]] ; ## A06 FMC2_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN L5 } [get_ports rx_data_1_n[5]] ; ## A07 FMC2_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN P8 } [get_ports rx_data_1_p[6]] ; ## C06 FMC2_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN P7 } [get_ports rx_data_1_n[6]] ; ## C07 FMC2_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN N6 } [get_ports rx_data_1_p[7]] ; ## A02 FMC2_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN N5 } [get_ports rx_data_1_n[7]] ; ## A03 FMC2_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVDS} [get_ports rx_sysref_p] ; ## G06 FMC1_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVDS} [get_ports rx_sysref_n] ; ## G07 FMC1_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS} [get_ports rx_sync_0_p] ; ## D08 FMC1_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS} [get_ports rx_sync_0_n] ; ## D09 FMC1_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVDS} [get_ports rx_sync_1_p] ; ## H07 FMC1_HPC_LA02_P
set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVDS} [get_ports rx_sync_1_n] ; ## H08 FMC1_HPC_LA02_N
set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_csn_0] ; ## D11 FMC1_HPC_LA05_P
set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports spi_csn_1] ; ## D12 FMC1_HPC_LA05_N
set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## C14 FMC1_HPC_LA10_P
set_property -dict {PACKAGE_PIN M39 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## C15 FMC1_HPC_LA10_N
set_property -dict {PACKAGE_PIN M36 IOSTANDARD LVCMOS18} [get_ports spi_dirn] ; ## H19 FMC1_HPC_LA15_P
set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports pwdn_0] ; ## H13 FMC1_HPC_LA07_P
set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports rst_0] ; ## C10 FMC1_HPC_LA06_P
set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports drst_0] ; ## G12 FMC1_HPC_LA08_P
set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVCMOS18} [get_ports arst_0] ; ## D14 FMC1_HPC_LA09_P
set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVCMOS18} [get_ports fd_0] ; ## H10 FMC1_HPC_LA04_P
set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports irq_0] ; ## G09 FMC1_HPC_LA03_P
set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports pwdn_1] ; ## H14 FMC1_HPC_LA07_N
set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVCMOS18} [get_ports rst_1] ; ## C11 FMC1_HPC_LA06_N
set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports drst_1] ; ## G13 FMC1_HPC_LA08_N
set_property -dict {PACKAGE_PIN P42 IOSTANDARD LVCMOS18} [get_ports arst_1] ; ## D15 FMC1_HPC_LA09_N
set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVCMOS18} [get_ports fd_1] ; ## H11 FMC1_HPC_LA04_N
set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports irq_1] ; ## G10 FMC1_HPC_LA03_N
set_property -dict {PACKAGE_PIN L37 IOSTANDARD LVCMOS18} [get_ports pwr_good] ; ## H20 FMC1_HPC_LA15_N
set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_p] ; ## H16 FMC1_HPC_LA11_P
set_property -dict {PACKAGE_PIN F41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_n] ; ## H17 FMC1_HPC_LA11_N
set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVDS} [get_ports vdither_p] ; ## G18 FMC1_HPC_LA16_P
set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVDS} [get_ports vdither_n] ; ## G19 FMC1_HPC_LA16_N
set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVCMOS18} [get_ports dac_clk] ; ## D17 FMC1_HPC_LA13_P
set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVCMOS18} [get_ports dac_data] ; ## D18 FMC1_HPC_LA13_N
set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVCMOS18} [get_ports dac_sync_0] ; ## C18 FMC1_HPC_LA14_P
set_property -dict {PACKAGE_PIN N40 IOSTANDARD LVCMOS18} [get_ports dac_sync_1] ; ## C19 FMC1_HPC_LA14_N
# clocks
create_clock -name rx_ref_clk_0 -period 1.60 [get_ports rx_ref_clk_0_p]
create_clock -name rx_ref_clk_1 -period 1.60 [get_ports rx_ref_clk_1_p]
create_clock -name rx_div_clk_0 -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_0_gt/rx_clk_g]
set_clock_groups -asynchronous -group {rx_div_clk_0}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_0_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_0_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_0_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_0_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_0_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_0_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_1_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_1_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_1_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_1_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_1_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_1_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

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projects/ad9625x2_fmc/vc707/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create ad9625x2_fmc_vc707
adi_project_files ad9625x2_fmc_vc707 [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"../common/ad9625x2_fmc_spi.v" \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
adi_project_run ad9625x2_fmc_vc707

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projects/ad9625x2_fmc/vc707/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
sgmii_rxp,
sgmii_rxn,
sgmii_txp,
sgmii_txn,
phy_rstn,
mgt_clk_p,
mgt_clk_n,
mdio_mdc,
mdio_mdio,
fan_pwm,
gpio_lcd,
gpio_led,
gpio_sw,
iic_rstn,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif,
rx_ref_clk_0_p,
rx_ref_clk_0_n,
rx_data_0_p,
rx_data_0_n,
rx_ref_clk_1_p,
rx_ref_clk_1_n,
rx_data_1_p,
rx_data_1_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_0_p,
rx_sync_0_n,
rx_sync_1_p,
rx_sync_1_n,
spi_csn_0,
spi_csn_1,
spi_clk,
spi_sdio,
spi_dirn,
trig_p,
trig_n,
vdither_p,
vdither_n,
pwr_good,
dac_clk,
dac_data,
dac_sync_0,
dac_sync_1,
fd_1,
irq_1,
fd_0,
irq_0,
pwdn_1,
rst_1,
drst_1,
arst_1,
pwdn_0,
rst_0,
drst_0,
arst_0);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [ 13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [ 63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
input sgmii_rxp;
input sgmii_rxn;
output sgmii_txp;
output sgmii_txn;
output phy_rstn;
input mgt_clk_p;
input mgt_clk_n;
output mdio_mdc;
inout mdio_mdio;
output fan_pwm;
output [ 6:0] gpio_lcd;
output [ 7:0] gpio_led;
input [ 12:0] gpio_sw;
output iic_rstn;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [ 35:0] hdmi_data;
output spdif;
input rx_ref_clk_0_p;
input rx_ref_clk_0_n;
input [ 7:0] rx_data_0_p;
input [ 7:0] rx_data_0_n;
input rx_ref_clk_1_p;
input rx_ref_clk_1_n;
input [ 7:0] rx_data_1_p;
input [ 7:0] rx_data_1_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_0_p;
output rx_sync_0_n;
output rx_sync_1_p;
output rx_sync_1_n;
output spi_csn_0;
output spi_csn_1;
output spi_clk;
inout spi_sdio;
output spi_dirn;
input trig_p;
input trig_n;
output vdither_p;
output vdither_n;
inout pwr_good;
inout dac_clk;
inout dac_data;
inout dac_sync_0;
inout dac_sync_1;
inout fd_1;
inout irq_1;
inout fd_0;
inout irq_0;
inout pwdn_1;
inout rst_1;
inout drst_1;
inout arst_1;
inout pwdn_0;
inout rst_0;
inout drst_0;
inout arst_0;
// internal registers
reg [511:0] adc_ddata = 'd0;
reg [255:0] core_rx_data_0 = 'd0;
reg [255:0] core_rx_data_1 = 'd0;
// internal signals
wire [ 18:0] gpio_i;
wire [ 18:0] gpio_o;
wire [ 18:0] gpio_t;
wire rx_ref_clk_0;
wire rx_ref_clk_1;
wire rx_sysref;
wire rx_sync_0;
wire rx_sync_1;
wire spi_clk;
wire spi_miso;
wire spi_mosi;
wire gt_rx_clk;
wire [255:0] gt_rx_data_0;
wire [255:0] gt_rx_data_1;
wire adc_dwr;
wire adc_dovf;
wire [255:0] adc_ddata_0;
wire [255:0] adc_ddata_1;
// interleaving
always @(posedge gt_rx_clk) begin
core_rx_data_0 <= gt_rx_data_0;
core_rx_data_1 <= gt_rx_data_1;
adc_ddata[((16*31)+15):(16*31)] = adc_ddata_1[((16*15)+15):(16*15)];
adc_ddata[((16*30)+15):(16*30)] = adc_ddata_0[((16*15)+15):(16*15)];
adc_ddata[((16*29)+15):(16*29)] = adc_ddata_1[((16*14)+15):(16*14)];
adc_ddata[((16*28)+15):(16*28)] = adc_ddata_0[((16*14)+15):(16*14)];
adc_ddata[((16*27)+15):(16*27)] = adc_ddata_1[((16*13)+15):(16*13)];
adc_ddata[((16*26)+15):(16*26)] = adc_ddata_0[((16*13)+15):(16*13)];
adc_ddata[((16*25)+15):(16*25)] = adc_ddata_1[((16*12)+15):(16*12)];
adc_ddata[((16*24)+15):(16*24)] = adc_ddata_0[((16*12)+15):(16*12)];
adc_ddata[((16*23)+15):(16*23)] = adc_ddata_1[((16*11)+15):(16*11)];
adc_ddata[((16*22)+15):(16*22)] = adc_ddata_0[((16*11)+15):(16*11)];
adc_ddata[((16*21)+15):(16*21)] = adc_ddata_1[((16*10)+15):(16*10)];
adc_ddata[((16*20)+15):(16*20)] = adc_ddata_0[((16*10)+15):(16*10)];
adc_ddata[((16*19)+15):(16*19)] = adc_ddata_1[((16* 9)+15):(16* 9)];
adc_ddata[((16*18)+15):(16*18)] = adc_ddata_0[((16* 9)+15):(16* 9)];
adc_ddata[((16*17)+15):(16*17)] = adc_ddata_1[((16* 8)+15):(16* 8)];
adc_ddata[((16*16)+15):(16*16)] = adc_ddata_0[((16* 8)+15):(16* 8)];
adc_ddata[((16*15)+15):(16*15)] = adc_ddata_1[((16* 7)+15):(16* 7)];
adc_ddata[((16*14)+15):(16*14)] = adc_ddata_0[((16* 7)+15):(16* 7)];
adc_ddata[((16*13)+15):(16*13)] = adc_ddata_1[((16* 6)+15):(16* 6)];
adc_ddata[((16*12)+15):(16*12)] = adc_ddata_0[((16* 6)+15):(16* 6)];
adc_ddata[((16*11)+15):(16*11)] = adc_ddata_1[((16* 5)+15):(16* 5)];
adc_ddata[((16*10)+15):(16*10)] = adc_ddata_0[((16* 5)+15):(16* 5)];
adc_ddata[((16* 9)+15):(16* 9)] = adc_ddata_1[((16* 4)+15):(16* 4)];
adc_ddata[((16* 8)+15):(16* 8)] = adc_ddata_0[((16* 4)+15):(16* 4)];
adc_ddata[((16* 7)+15):(16* 7)] = adc_ddata_1[((16* 3)+15):(16* 3)];
adc_ddata[((16* 6)+15):(16* 6)] = adc_ddata_0[((16* 3)+15):(16* 3)];
adc_ddata[((16* 5)+15):(16* 5)] = adc_ddata_1[((16* 2)+15):(16* 2)];
adc_ddata[((16* 4)+15):(16* 4)] = adc_ddata_0[((16* 2)+15):(16* 2)];
adc_ddata[((16* 3)+15):(16* 3)] = adc_ddata_1[((16* 1)+15):(16* 1)];
adc_ddata[((16* 2)+15):(16* 2)] = adc_ddata_0[((16* 1)+15):(16* 1)];
adc_ddata[((16* 1)+15):(16* 1)] = adc_ddata_1[((16* 0)+15):(16* 0)];
adc_ddata[((16* 0)+15):(16* 0)] = adc_ddata_0[((16* 0)+15):(16* 0)];
end
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk_0 (
.CEB (1'd0),
.I (rx_ref_clk_0_p),
.IB (rx_ref_clk_0_n),
.O (rx_ref_clk_0),
.ODIV2 ());
IBUFDS_GTE2 i_ibufds_rx_ref_clk_1 (
.CEB (1'd0),
.I (rx_ref_clk_1_p),
.IB (rx_ref_clk_1_n),
.O (rx_ref_clk_1),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync_0 (
.I (rx_sync_0),
.O (rx_sync_0_p),
.OB (rx_sync_0_n));
OBUFDS i_obufds_rx_sync_1 (
.I (rx_sync_1),
.O (rx_sync_1_p),
.OB (rx_sync_1_n));
IBUFDS i_ibufds_trig (
.I (trig_p),
.IB (trig_n),
.O (gpio_i[18]));
OBUFDS i_obufds_vdither (
.I (gpio_o[17]),
.O (vdither_p),
.OB (vdither_n));
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dt (gpio_t[16:0]),
.di (gpio_o[16:0]),
.do (gpio_i[16:0]),
.dio ({ pwr_good, // 16
dac_clk, // 15
dac_data, // 14
dac_sync_0, // 13
dac_sync_1, // 12
fd_1, // 11
irq_1, // 10
fd_0, // 9
irq_0, // 8
pwdn_1, // 7
rst_1, // 6
drst_1, // 5
arst_1, // 4
pwdn_0, // 3
rst_0, // 2
drst_0, // 1
arst_0})); // 0
ad9625x2_fmc_spi i_ad9625x2_fmc_spi (
.spi_csn_0 (spi_csn_0),
.spi_csn_1 (spi_csn_1),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio),
.spi_dirn (spi_dirn));
system_wrapper i_system_wrapper (
.adc_ddata (adc_ddata),
.adc_dovf (adc_dovf),
.adc_dsync (1'b1),
.adc_dwr (adc_dwr),
.core_ddata_0 (adc_ddata_0),
.core_ddata_1 (adc_ddata_1),
.core_dovf_0 (adc_dovf),
.core_dovf_1 (adc_dovf),
.core_dwr_0 (adc_dwr),
.core_dwr_1 (),
.core_rx_data_0 (core_rx_data_0),
.core_rx_data_1 (core_rx_data_1),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.fan_pwm (fan_pwm),
.gpio_ad9625_i (gpio_i),
.gpio_ad9625_o (gpio_o),
.gpio_ad9625_t (gpio_t),
.gpio_lcd_tri_o (gpio_lcd),
.gpio_led_tri_o (gpio_led),
.gpio_sw_tri_i (gpio_sw),
.gt_rx_clk (gt_rx_clk),
.gt_rx_data_0 (gt_rx_data_0),
.gt_rx_data_1 (gt_rx_data_1),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.iic_rstn (iic_rstn),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.rx_data_0_n (rx_data_0_n),
.rx_data_0_p (rx_data_0_p),
.rx_data_1_n (rx_data_1_n),
.rx_data_1_p (rx_data_1_p),
.rx_ref_clk_0 (rx_ref_clk_0),
.rx_ref_clk_1 (rx_ref_clk_1),
.rx_sync_0 (rx_sync_0),
.rx_sync_1 (rx_sync_1),
.rx_sysref (rx_sysref),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.spdif (spdif),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (2'b11),
.spi_csn_o ({spi_csn_1, spi_csn_0}),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.unc_int0 (1'b0),
.unc_int1 (1'b0),
.unc_int3 (1'b0),
.unc_int4 (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************