zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

xilinx/axi_adxcvr: Add 204C support, increase version to 17.3.a

main
Laszlo Nagy 2021-04-19 14:54:36 +01:00 committed by Laszlo Nagy
parent 77a5edaa83
commit 2d13b5b8cd
3 changed files with 25 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/xilinx/axi_adxcvr/axi_adxcvr.v
View File

@ -43,6 +43,7 @@ module axi_adxcvr #(
parameter integer ID = 0,
parameter integer NUM_OF_LANES = 8,
parameter integer XCVR_TYPE = 0,
parameter integer LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
@ -2117,6 +2118,7 @@ module axi_adxcvr #(
axi_adxcvr_up #(
.ID (ID),
.LINK_MODE (LINK_MODE),
.NUM_OF_LANES (NUM_OF_LANES),
.XCVR_TYPE (XCVR_TYPE),
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),

18
library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
View File

@ -19,6 +19,24 @@ adi_ip_infer_mm_interfaces axi_adxcvr
adi_init_bd_tcl
adi_ip_bd axi_adxcvr "bd/bd.tcl"
set cc [ipx::current_core]
# Arrange GUI page layout
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# Link layer mode
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $page0
set_property -dict [list \
"display_name" "Link Layer mode" \
"tooltip" "Link Layer mode" \
"widget" "comboBox" \
] $p
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {64B66B 2 8B10B 1} \
] [ipx::get_user_parameters $p -of_objects $cc]
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
set_property master_address_space_ref m_axi \

7
library/xilinx/axi_adxcvr/axi_adxcvr_up.v
View File

@ -42,6 +42,7 @@ module axi_adxcvr_up #(
parameter integer ID = 0,
parameter integer NUM_OF_LANES = 8,
parameter integer XCVR_TYPE = 0,
parameter integer LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
parameter [ 7:0] FPGA_TECHNOLOGY = 0,
parameter [ 7:0] FPGA_FAMILY = 0,
parameter [ 7:0] SPEED_GRADE = 0,
@ -130,7 +131,7 @@ module axi_adxcvr_up #(
// parameters
localparam [31:0] VERSION = 32'h00110261;
localparam [31:0] VERSION = 32'h00110361;
// internal registers
@ -507,7 +508,9 @@ module axi_adxcvr_up #(
// generic
assign up_rparam_s[15: 9] = 7'd0;
assign up_rparam_s[15:14] = 2'd0;
assign up_rparam_s[13:12] = LINK_MODE[1:0];
assign up_rparam_s[11: 9] = 3'd0;
assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1;
assign up_rparam_s[ 7: 0] = NUM_OF_LANES;