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Move Altera IP core dependency tracking to library Makefiles 

Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.

For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.

Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.

Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.

This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-03-27 11:21:09 +02:00 committed by István Csomortáni
parent 48ef19ec60
commit 2b914d33c1
116 changed files with 1509 additions and 1754 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitignore vendored
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@ -73,5 +73,5 @@ reconfig_mif
*.xml
*.hw
gui
.timestamp_altera

28
library/Makefile
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@ -10,6 +10,18 @@ all: lib
clean:
$(MAKE) -C altera/adi_jesd204 clean
$(MAKE) -C altera/avl_adxcfg clean
$(MAKE) -C altera/avl_adxcvr clean
$(MAKE) -C altera/avl_adxcvr_octet_swap clean
$(MAKE) -C altera/avl_adxphy clean
$(MAKE) -C altera/avl_dacfifo clean
$(MAKE) -C altera/axi_adxcvr clean
$(MAKE) -C altera/common/alt_ifconv clean
$(MAKE) -C altera/common/alt_mem_asym clean
$(MAKE) -C altera/common/alt_mul clean
$(MAKE) -C altera/common/alt_serdes clean
$(MAKE) -C altera/jesd204_phy clean
$(MAKE) -C axi_ad5766 clean
$(MAKE) -C axi_ad6676 clean
$(MAKE) -C axi_ad7616 clean
@ -59,6 +71,8 @@ clean:
$(MAKE) -C jesd204/jesd204_common clean
$(MAKE) -C jesd204/jesd204_rx clean
$(MAKE) -C jesd204/jesd204_rx_static_config clean
$(MAKE) -C jesd204/jesd204_soft_pcs_rx clean
$(MAKE) -C jesd204/jesd204_soft_pcs_tx clean
$(MAKE) -C jesd204/jesd204_tx clean
$(MAKE) -C jesd204/jesd204_tx_static_config clean
$(MAKE) -C spi_engine/axi_spi_engine clean
@ -102,6 +116,18 @@ clean-all:clean
lib:
$(MAKE) -C altera/adi_jesd204
$(MAKE) -C altera/avl_adxcfg
$(MAKE) -C altera/avl_adxcvr
$(MAKE) -C altera/avl_adxcvr_octet_swap
$(MAKE) -C altera/avl_adxphy
$(MAKE) -C altera/avl_dacfifo
$(MAKE) -C altera/axi_adxcvr
$(MAKE) -C altera/common/alt_ifconv
$(MAKE) -C altera/common/alt_mem_asym
$(MAKE) -C altera/common/alt_mul
$(MAKE) -C altera/common/alt_serdes
$(MAKE) -C altera/jesd204_phy
$(MAKE) -C axi_ad5766
$(MAKE) -C axi_ad6676
$(MAKE) -C axi_ad7616
@ -151,6 +177,8 @@ lib:
$(MAKE) -C jesd204/jesd204_common
$(MAKE) -C jesd204/jesd204_rx
$(MAKE) -C jesd204/jesd204_rx_static_config
$(MAKE) -C jesd204/jesd204_soft_pcs_rx
$(MAKE) -C jesd204/jesd204_soft_pcs_tx
$(MAKE) -C jesd204/jesd204_tx
$(MAKE) -C jesd204/jesd204_tx_static_config
$(MAKE) -C spi_engine/axi_spi_engine

15
library/altera/adi_jesd204/Makefile Normal file
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@ -0,0 +1,15 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := adi_jesd204
ALTERA_DEPS += adi_jesd204_hw.tcl
ALTERA_LIB_DEPS += altera/axi_adxcvr
ALTERA_LIB_DEPS += altera/jesd204_phy
ALTERA_LIB_DEPS += jesd204/jesd204_soft_pcs_rx
ALTERA_LIB_DEPS += jesd204/jesd204_soft_pcs_tx
include ../../scripts/library.mk

11
library/altera/avl_adxcfg/Makefile Normal file
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@ -0,0 +1,11 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := avl_adxcfg
ALTERA_DEPS += avl_adxcfg.v
ALTERA_DEPS += avl_adxcfg_hw.tcl
include ../../scripts/library.mk

13
library/altera/avl_adxcvr/Makefile Normal file
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@ -0,0 +1,13 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := avl_adxcvr
ALTERA_DEPS += avl_adxcvr_hw.tcl
ALTERA_LIB_DEPS += altera/avl_adxcvr_octet_swap
ALTERA_LIB_DEPS += altera/avl_adxphy
include ../../scripts/library.mk

11
library/altera/avl_adxcvr_octet_swap/Makefile Normal file
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@ -0,0 +1,11 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := avl_adxcvr_octet_swap
ALTERA_DEPS += avl_adxcvr_octet_swap.v
ALTERA_DEPS += avl_adxcvr_octet_swap_hw.tcl
include ../../scripts/library.mk

11
library/altera/avl_adxphy/Makefile Normal file
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@ -0,0 +1,11 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := avl_adxphy
ALTERA_DEPS += avl_adxphy.v
ALTERA_DEPS += avl_adxphy_hw.tcl
include ../../scripts/library.mk

21
library/altera/avl_dacfifo/Makefile Normal file
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@ -0,0 +1,21 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := avl_dacfifo
ALTERA_DEPS += ../../common/ad_b2g.v
ALTERA_DEPS += ../../common/ad_g2b.v
ALTERA_DEPS += ../../common/ad_mem.v
ALTERA_DEPS += ../../common/util_delay.v
ALTERA_DEPS += avl_dacfifo.v
ALTERA_DEPS += avl_dacfifo_byteenable_coder.v
ALTERA_DEPS += avl_dacfifo_byteenable_decoder.v
ALTERA_DEPS += avl_dacfifo_constr.sdc
ALTERA_DEPS += avl_dacfifo_hw.tcl
ALTERA_DEPS += avl_dacfifo_rd.v
ALTERA_DEPS += avl_dacfifo_wr.v
ALTERA_DEPS += util_dacfifo_bypass.v
include ../../scripts/library.mk

13
library/altera/axi_adxcvr/Makefile Normal file
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@ -0,0 +1,13 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_adxcvr
ALTERA_DEPS += ../../common/up_axi.v
ALTERA_DEPS += axi_adxcvr.v
ALTERA_DEPS += axi_adxcvr_hw.tcl
ALTERA_DEPS += axi_adxcvr_up.v
include ../../scripts/library.mk

11
library/altera/common/alt_ifconv/Makefile Normal file
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@ -0,0 +1,11 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := alt_ifconv
ALTERA_DEPS += alt_ifconv.v
ALTERA_DEPS += alt_ifconv_hw.tcl
include ../../../scripts/library.mk

4
library/altera/common/alt_ifconv/alt_ifconv_hw.tcl
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@ -5,7 +5,9 @@ source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
ad_ip_create alt_ifconv {Altera Interface Translator} alt_ifconv_elab
ad_ip_files alt_ifconv $ad_hdl_dir/library/altera/common/alt_ifconv/alt_ifconv.v
ad_ip_files alt_ifconv { \
$ad_hdl_dir/library/altera/common/alt_ifconv/alt_ifconv.v \
}
# parameters

10
library/altera/common/alt_mem_asym/Makefile Normal file
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@ -0,0 +1,10 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := alt_mem_asym
ALTERA_DEPS += alt_mem_asym_hw.tcl
include ../../../scripts/library.mk

10
library/altera/common/alt_mul/Makefile Normal file
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@ -0,0 +1,10 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := alt_mul
ALTERA_DEPS += alt_mul_hw.tcl
include ../../../scripts/library.mk

10
library/altera/common/alt_serdes/Makefile Normal file
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@ -0,0 +1,10 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := alt_serdes
ALTERA_DEPS += alt_serdes_hw.tcl
include ../../../scripts/library.mk

15
library/altera/jesd204_phy/Makefile Normal file
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@ -0,0 +1,15 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := jesd204_phy
ALTERA_DEPS += jesd204_phy_glue.v
ALTERA_DEPS += jesd204_phy_glue_hw.tcl
ALTERA_DEPS += jesd204_phy_hw.tcl
ALTERA_LIB_DEPS += jesd204/jesd204_soft_pcs_rx
ALTERA_LIB_DEPS += jesd204/jesd204_soft_pcs_tx
include ../../scripts/library.mk

31
library/axi_ad5766/Makefile
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@ -5,22 +5,23 @@
LIBRARY_NAME := axi_ad5766
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/util_pulse_gen.v
M_DEPS += axi_ad5766.v
M_DEPS += axi_ad5766_ip.tcl
M_DEPS += up_ad5766_sequencer.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += ../common/util_pulse_gen.v
GENERIC_DEPS += axi_ad5766.v
GENERIC_DEPS += up_ad5766_sequencer.v
M_DEPS += ../spi_engine/interfaces/spi_engine_ctrl.xml
M_DEPS += ../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
M_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl.xml
M_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_DEPS += axi_ad5766_ip.tcl
LIB_DEPS += util_cdc
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_cdc
include ../scripts/library.mk

39
library/axi_ad6676/Makefile
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@ -5,24 +5,25 @@
LIBRARY_NAME := axi_ad6676
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad6676.v
M_DEPS += axi_ad6676_channel.v
M_DEPS += axi_ad6676_constr.xdc
M_DEPS += axi_ad6676_if.v
M_DEPS += axi_ad6676_ip.tcl
M_DEPS += axi_ad6676_pnmon.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad6676.v
GENERIC_DEPS += axi_ad6676_channel.v
GENERIC_DEPS += axi_ad6676_if.v
GENERIC_DEPS += axi_ad6676_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad6676_constr.xdc
XILINX_DEPS += axi_ad6676_ip.tcl
include ../scripts/library.mk

23
library/axi_ad7616/Makefile
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@ -5,17 +5,18 @@
LIBRARY_NAME := axi_ad7616
M_DEPS += ../common/ad_edge_detect.v
M_DEPS += ../common/up_axi.v
M_DEPS += axi_ad7616.v
M_DEPS += axi_ad7616_control.v
M_DEPS += axi_ad7616_ip.tcl
M_DEPS += axi_ad7616_maxis2wrfifo.v
M_DEPS += axi_ad7616_pif.v
GENERIC_DEPS += ../common/ad_edge_detect.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_ad7616.v
GENERIC_DEPS += axi_ad7616_control.v
GENERIC_DEPS += axi_ad7616_maxis2wrfifo.v
GENERIC_DEPS += axi_ad7616_pif.v
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
XILINX_DEPS += axi_ad7616_ip.tcl
XILINX_LIB_DEPS += spi_engine/axi_spi_engine
XILINX_LIB_DEPS += spi_engine/spi_engine_execution
XILINX_LIB_DEPS += spi_engine/spi_engine_interconnect
XILINX_LIB_DEPS += spi_engine/spi_engine_offload
include ../scripts/library.mk

57
library/axi_ad9122/Makefile
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@ -5,29 +5,38 @@
LIBRARY_NAME := axi_ad9122
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_mmcm_drp.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/ad_serdes_clk.v
M_DEPS += ../xilinx/common/ad_serdes_out.v
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9122.v
M_DEPS += axi_ad9122_channel.v
M_DEPS += axi_ad9122_constr.xdc
M_DEPS += axi_ad9122_core.v
M_DEPS += axi_ad9122_if.v
M_DEPS += axi_ad9122_ip.tcl
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9122.v
GENERIC_DEPS += axi_ad9122_channel.v
GENERIC_DEPS += axi_ad9122_core.v
GENERIC_DEPS += axi_ad9122_if.v
XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v
XILINX_DEPS += ../xilinx/common/ad_serdes_out.v
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9122_constr.xdc
XILINX_DEPS += axi_ad9122_ip.tcl
ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9122_constr.sdc
ALTERA_DEPS += axi_ad9122_hw.tcl
include ../scripts/library.mk

48
library/axi_ad9144/Makefile
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@ -5,25 +5,33 @@
LIBRARY_NAME := axi_ad9144
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9144.v
M_DEPS += axi_ad9144_channel.v
M_DEPS += axi_ad9144_core.v
M_DEPS += axi_ad9144_if.v
M_DEPS += axi_ad9144_ip.tcl
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9144.v
GENERIC_DEPS += axi_ad9144_channel.v
GENERIC_DEPS += axi_ad9144_core.v
GENERIC_DEPS += axi_ad9144_if.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9144_ip.tcl
ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9144_hw.tcl
include ../scripts/library.mk

48
library/axi_ad9152/Makefile
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@ -5,25 +5,33 @@
LIBRARY_NAME := axi_ad9152
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9152.v
M_DEPS += axi_ad9152_channel.v
M_DEPS += axi_ad9152_core.v
M_DEPS += axi_ad9152_if.v
M_DEPS += axi_ad9152_ip.tcl
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9152.v
GENERIC_DEPS += axi_ad9152_channel.v
GENERIC_DEPS += axi_ad9152_core.v
GENERIC_DEPS += axi_ad9152_if.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9152_ip.tcl
ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9152_hw.tcl
include ../scripts/library.mk

41
library/axi_ad9162/Makefile
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@ -5,25 +5,26 @@
LIBRARY_NAME := axi_ad9162
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9162.v
M_DEPS += axi_ad9162_channel.v
M_DEPS += axi_ad9162_core.v
M_DEPS += axi_ad9162_if.v
M_DEPS += axi_ad9162_ip.tcl
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9162.v
GENERIC_DEPS += axi_ad9162_channel.v
GENERIC_DEPS += axi_ad9162_core.v
GENERIC_DEPS += axi_ad9162_if.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9162_ip.tcl
include ../scripts/library.mk

47
library/axi_ad9250/Makefile
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@ -5,25 +5,32 @@
LIBRARY_NAME := axi_ad9250
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9250.v
M_DEPS += axi_ad9250_channel.v
M_DEPS += axi_ad9250_constr.xdc
M_DEPS += axi_ad9250_if.v
M_DEPS += axi_ad9250_ip.tcl
M_DEPS += axi_ad9250_pnmon.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9250.v
GENERIC_DEPS += axi_ad9250_channel.v
GENERIC_DEPS += axi_ad9250_if.v
GENERIC_DEPS += axi_ad9250_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9250_constr.xdc
XILINX_DEPS += axi_ad9250_ip.tcl
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9250_hw.tcl
include ../scripts/library.mk

47
library/axi_ad9265/Makefile
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@ -5,28 +5,29 @@
LIBRARY_NAME := axi_ad9265
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_data_clk.v
M_DEPS += ../xilinx/common/ad_data_in.v
M_DEPS += ../xilinx/common/ad_dcfilter.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9265.v
M_DEPS += axi_ad9265_channel.v
M_DEPS += axi_ad9265_constr.xdc
M_DEPS += axi_ad9265_if.v
M_DEPS += axi_ad9265_ip.tcl
M_DEPS += axi_ad9265_pnmon.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9265.v
GENERIC_DEPS += axi_ad9265_channel.v
GENERIC_DEPS += axi_ad9265_if.v
GENERIC_DEPS += axi_ad9265_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_data_clk.v
XILINX_DEPS += ../xilinx/common/ad_data_in.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9265_constr.xdc
XILINX_DEPS += axi_ad9265_ip.tcl
include ../scripts/library.mk

98
library/axi_ad9361/Makefile
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@ -5,47 +5,61 @@
LIBRARY_NAME := axi_ad9361
M_DEPS += ../common/ad_addsub.v
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_pps_receiver.v
M_DEPS += ../common/ad_pps_receiver_constr.ttcl
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_tdd_control.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_tdd_cntrl.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_data_clk.v
M_DEPS += ../xilinx/common/ad_data_in.v
M_DEPS += ../xilinx/common/ad_data_out.v
M_DEPS += ../xilinx/common/ad_dcfilter.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9361.v
M_DEPS += axi_ad9361_constr.xdc
M_DEPS += axi_ad9361_ip.tcl
M_DEPS += axi_ad9361_rx.v
M_DEPS += axi_ad9361_rx_channel.v
M_DEPS += axi_ad9361_rx_pnmon.v
M_DEPS += axi_ad9361_tdd.v
M_DEPS += axi_ad9361_tdd_if.v
M_DEPS += axi_ad9361_tx.v
M_DEPS += axi_ad9361_tx_channel.v
M_DEPS += xilinx/axi_ad9361_cmos_if.v
M_DEPS += xilinx/axi_ad9361_lvds_if.v
GENERIC_DEPS += ../common/ad_addsub.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_iqcor.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_pps_receiver.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_tdd_control.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_tdd_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9361.v
GENERIC_DEPS += axi_ad9361_rx.v
GENERIC_DEPS += axi_ad9361_rx_channel.v
GENERIC_DEPS += axi_ad9361_rx_pnmon.v
GENERIC_DEPS += axi_ad9361_tdd.v
GENERIC_DEPS += axi_ad9361_tdd_if.v
GENERIC_DEPS += axi_ad9361_tx.v
GENERIC_DEPS += axi_ad9361_tx_channel.v
XILINX_DEPS += ../common/ad_pps_receiver_constr.ttcl
XILINX_DEPS += ../xilinx/common/ad_data_clk.v
XILINX_DEPS += ../xilinx/common/ad_data_in.v
XILINX_DEPS += ../xilinx/common/ad_data_out.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9361_constr.xdc
XILINX_DEPS += axi_ad9361_ip.tcl
XILINX_DEPS += xilinx/axi_ad9361_cmos_if.v
XILINX_DEPS += xilinx/axi_ad9361_lvds_if.v
ALTERA_DEPS += ../altera/common/ad_dcfilter.v
ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += altera/axi_ad9361_cmos_if.v
ALTERA_DEPS += altera/axi_ad9361_lvds_if.v
ALTERA_DEPS += altera/axi_ad9361_lvds_if_10.v
ALTERA_DEPS += altera/axi_ad9361_lvds_if_c5.v
ALTERA_DEPS += axi_ad9361_constr.sdc
ALTERA_DEPS += axi_ad9361_hw.tcl
include ../scripts/library.mk

67
library/axi_ad9371/Makefile
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@ -5,34 +5,43 @@
LIBRARY_NAME := axi_ad9371
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_dcfilter.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9371.v
M_DEPS += axi_ad9371_if.v
M_DEPS += axi_ad9371_ip.tcl
M_DEPS += axi_ad9371_rx.v
M_DEPS += axi_ad9371_rx_channel.v
M_DEPS += axi_ad9371_rx_os.v
M_DEPS += axi_ad9371_tx.v
M_DEPS += axi_ad9371_tx_channel.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_iqcor.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9371.v
GENERIC_DEPS += axi_ad9371_if.v
GENERIC_DEPS += axi_ad9371_rx.v
GENERIC_DEPS += axi_ad9371_rx_channel.v
GENERIC_DEPS += axi_ad9371_rx_os.v
GENERIC_DEPS += axi_ad9371_tx.v
GENERIC_DEPS += axi_ad9371_tx_channel.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9371_ip.tcl
ALTERA_DEPS += ../altera/common/ad_dcfilter.v
ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9371_hw.tcl
include ../scripts/library.mk

67
library/axi_ad9379/Makefile
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@ -5,34 +5,43 @@
LIBRARY_NAME := axi_ad9379
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_dcfilter.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9379.v
M_DEPS += axi_ad9379_if.v
M_DEPS += axi_ad9379_ip.tcl
M_DEPS += axi_ad9379_rx.v
M_DEPS += axi_ad9379_rx_channel.v
M_DEPS += axi_ad9379_rx_os.v
M_DEPS += axi_ad9379_tx.v
M_DEPS += axi_ad9379_tx_channel.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_iqcor.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9379.v
GENERIC_DEPS += axi_ad9379_if.v
GENERIC_DEPS += axi_ad9379_rx.v
GENERIC_DEPS += axi_ad9379_rx_channel.v
GENERIC_DEPS += axi_ad9379_rx_os.v
GENERIC_DEPS += axi_ad9379_tx.v
GENERIC_DEPS += axi_ad9379_tx_channel.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9379_ip.tcl
ALTERA_DEPS += ../altera/common/ad_dcfilter.v
ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9379_hw.tcl
include ../scripts/library.mk

47
library/axi_ad9434/Makefile
View File

@ -5,28 +5,29 @@
LIBRARY_NAME := axi_ad9434
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_mmcm_drp.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/ad_serdes_clk.v
M_DEPS += ../xilinx/common/ad_serdes_in.v
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9434.v
M_DEPS += axi_ad9434_constr.xdc
M_DEPS += axi_ad9434_core.v
M_DEPS += axi_ad9434_if.v
M_DEPS += axi_ad9434_ip.tcl
M_DEPS += axi_ad9434_pnmon.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9434.v
GENERIC_DEPS += axi_ad9434_core.v
GENERIC_DEPS += axi_ad9434_if.v
GENERIC_DEPS += axi_ad9434_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v
XILINX_DEPS += ../xilinx/common/ad_serdes_in.v
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9434_constr.xdc
XILINX_DEPS += axi_ad9434_ip.tcl
include ../scripts/library.mk

45
library/axi_ad9467/Makefile
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@ -5,27 +5,28 @@
LIBRARY_NAME := axi_ad9467
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_data_clk.v
M_DEPS += ../xilinx/common/ad_data_in.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9467.v
M_DEPS += axi_ad9467_channel.v
M_DEPS += axi_ad9467_constr.xdc
M_DEPS += axi_ad9467_if.v
M_DEPS += axi_ad9467_ip.tcl
M_DEPS += axi_ad9467_pnmon.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9467.v
GENERIC_DEPS += axi_ad9467_channel.v
GENERIC_DEPS += axi_ad9467_if.v
GENERIC_DEPS += axi_ad9467_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_data_clk.v
XILINX_DEPS += ../xilinx/common/ad_data_in.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9467_constr.xdc
XILINX_DEPS += axi_ad9467_ip.tcl
include ../scripts/library.mk

43
library/axi_ad9625/Makefile
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@ -5,26 +5,27 @@
LIBRARY_NAME := axi_ad9625
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_mem.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9625.v
M_DEPS += axi_ad9625_channel.v
M_DEPS += axi_ad9625_constr.xdc
M_DEPS += axi_ad9625_if.v
M_DEPS += axi_ad9625_ip.tcl
M_DEPS += axi_ad9625_pnmon.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9625.v
GENERIC_DEPS += axi_ad9625_channel.v
GENERIC_DEPS += axi_ad9625_if.v
GENERIC_DEPS += axi_ad9625_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9625_constr.xdc
XILINX_DEPS += axi_ad9625_ip.tcl
include ../scripts/library.mk

49
library/axi_ad9671/Makefile
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@ -5,26 +5,33 @@
LIBRARY_NAME := axi_ad9671
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_mem.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9671.v
M_DEPS += axi_ad9671_channel.v
M_DEPS += axi_ad9671_constr.xdc
M_DEPS += axi_ad9671_if.v
M_DEPS += axi_ad9671_ip.tcl
M_DEPS += axi_ad9671_pnmon.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9671.v
GENERIC_DEPS += axi_ad9671_channel.v
GENERIC_DEPS += axi_ad9671_if.v
GENERIC_DEPS += axi_ad9671_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9671_constr.xdc
XILINX_DEPS += axi_ad9671_ip.tcl
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9671_hw.tcl
include ../scripts/library.mk

45
library/axi_ad9680/Makefile
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@ -5,24 +5,31 @@
LIBRARY_NAME := axi_ad9680
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9680.v
M_DEPS += axi_ad9680_channel.v
M_DEPS += axi_ad9680_if.v
M_DEPS += axi_ad9680_ip.tcl
M_DEPS += axi_ad9680_pnmon.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9680.v
GENERIC_DEPS += axi_ad9680_channel.v
GENERIC_DEPS += axi_ad9680_if.v
GENERIC_DEPS += axi_ad9680_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9680_ip.tcl
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9680_hw.tcl
include ../scripts/library.mk

54
library/axi_ad9684/Makefile
View File

@ -5,28 +5,36 @@
LIBRARY_NAME := axi_ad9684
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_mmcm_drp.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/ad_serdes_clk.v
M_DEPS += ../xilinx/common/ad_serdes_in.v
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9684.v
M_DEPS += axi_ad9684_channel.v
M_DEPS += axi_ad9684_constr.xdc
M_DEPS += axi_ad9684_if.v
M_DEPS += axi_ad9684_ip.tcl
M_DEPS += axi_ad9684_pnmon.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9684.v
GENERIC_DEPS += axi_ad9684_channel.v
GENERIC_DEPS += axi_ad9684_if.v
GENERIC_DEPS += axi_ad9684_pnmon.v
XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v
XILINX_DEPS += ../xilinx/common/ad_serdes_in.v
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9684_constr.xdc
XILINX_DEPS += axi_ad9684_ip.tcl
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9684_constr.sdc
ALTERA_DEPS += axi_ad9684_hw.tcl
include ../scripts/library.mk

45
library/axi_ad9739a/Makefile
View File

@ -5,27 +5,28 @@
LIBRARY_NAME := axi_ad9739a
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/ad_serdes_out.v
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9739a.v
M_DEPS += axi_ad9739a_channel.v
M_DEPS += axi_ad9739a_constr.xdc
M_DEPS += axi_ad9739a_core.v
M_DEPS += axi_ad9739a_if.v
M_DEPS += axi_ad9739a_ip.tcl
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9739a.v
GENERIC_DEPS += axi_ad9739a_channel.v
GENERIC_DEPS += axi_ad9739a_core.v
GENERIC_DEPS += axi_ad9739a_if.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/ad_serdes_out.v
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9739a_constr.xdc
XILINX_DEPS += axi_ad9739a_ip.tcl
include ../scripts/library.mk

65
library/axi_ad9963/Makefile
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@ -5,37 +5,38 @@
LIBRARY_NAME := axi_ad9963
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_data_in.v
M_DEPS += ../xilinx/common/ad_dcfilter.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9963.v
M_DEPS += axi_ad9963_constr.xdc
M_DEPS += axi_ad9963_if.v
M_DEPS += axi_ad9963_ip.tcl
M_DEPS += axi_ad9963_rx.v
M_DEPS += axi_ad9963_rx_channel.v
M_DEPS += axi_ad9963_rx_pnmon.v
M_DEPS += axi_ad9963_tx.v
M_DEPS += axi_ad9963_tx_channel.v
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_iqcor.v
GENERIC_DEPS += ../common/ad_pnmon.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9963.v
GENERIC_DEPS += axi_ad9963_if.v
GENERIC_DEPS += axi_ad9963_rx.v
GENERIC_DEPS += axi_ad9963_rx_channel.v
GENERIC_DEPS += axi_ad9963_rx_pnmon.v
GENERIC_DEPS += axi_ad9963_tx.v
GENERIC_DEPS += axi_ad9963_tx_channel.v
XILINX_DEPS += ../xilinx/common/ad_data_in.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9963_constr.xdc
XILINX_DEPS += axi_ad9963_ip.tcl
include ../scripts/library.mk

23
library/axi_adc_decimate/Makefile
View File

@ -5,17 +5,18 @@
LIBRARY_NAME := axi_adc_decimate
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += axi_adc_decimate.v
M_DEPS += axi_adc_decimate_filter.v
M_DEPS += axi_adc_decimate_ip.tcl
M_DEPS += axi_adc_decimate_reg.v
M_DEPS += cic_decim.v
M_DEPS += fir_decim.v
GENERIC_DEPS += ../common/ad_iqcor.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += axi_adc_decimate.v
GENERIC_DEPS += axi_adc_decimate_filter.v
GENERIC_DEPS += axi_adc_decimate_reg.v
GENERIC_DEPS += cic_decim.v
GENERIC_DEPS += fir_decim.v
LIB_DEPS += util_cic
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += axi_adc_decimate_ip.tcl
XILINX_LIB_DEPS += util_cic
include ../scripts/library.mk

15
library/axi_adc_trigger/Makefile
View File

@ -5,12 +5,13 @@
LIBRARY_NAME := axi_adc_trigger
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += axi_adc_trigger.v
M_DEPS += axi_adc_trigger_constr.xdc
M_DEPS += axi_adc_trigger_ip.tcl
M_DEPS += axi_adc_trigger_reg.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += axi_adc_trigger.v
GENERIC_DEPS += axi_adc_trigger_reg.v
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += axi_adc_trigger_constr.xdc
XILINX_DEPS += axi_adc_trigger_ip.tcl
include ../scripts/library.mk

17
library/axi_clkgen/Makefile
View File

@ -5,13 +5,14 @@
LIBRARY_NAME := axi_clkgen
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clkgen.v
M_DEPS += ../xilinx/common/ad_mmcm_drp.v
M_DEPS += axi_clkgen.v
M_DEPS += axi_clkgen_constr.xdc
M_DEPS += axi_clkgen_ip.tcl
M_DEPS += bd/bd.tcl
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clkgen.v
GENERIC_DEPS += axi_clkgen.v
XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v
XILINX_DEPS += axi_clkgen_constr.xdc
XILINX_DEPS += axi_clkgen_ip.tcl
XILINX_DEPS += bd/bd.tcl
include ../scripts/library.mk

23
library/axi_dac_interpolate/Makefile
View File

@ -5,16 +5,17 @@
LIBRARY_NAME := axi_dac_interpolate
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += axi_dac_interpolate.v
M_DEPS += axi_dac_interpolate_filter.v
M_DEPS += axi_dac_interpolate_ip.tcl
M_DEPS += axi_dac_interpolate_reg.v
M_DEPS += cic_interp.v
M_DEPS += fir_interp.v
GENERIC_DEPS += ../common/ad_iqcor.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += axi_dac_interpolate.v
GENERIC_DEPS += axi_dac_interpolate_filter.v
GENERIC_DEPS += axi_dac_interpolate_reg.v
GENERIC_DEPS += cic_interp.v
GENERIC_DEPS += fir_interp.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += axi_dac_interpolate_ip.tcl
include ../scripts/library.mk

69
library/axi_dmac/Makefile
View File

@ -5,36 +5,47 @@
LIBRARY_NAME := axi_dmac
M_DEPS += ../common/up_axi.v
M_DEPS += 2d_transfer.v
M_DEPS += address_generator.v
M_DEPS += axi_dmac.v
M_DEPS += axi_dmac_constr.ttcl
M_DEPS += axi_dmac_ip.tcl
M_DEPS += axi_register_slice.v
M_DEPS += bd/bd.tcl
M_DEPS += data_mover.v
M_DEPS += dest_axi_mm.v
M_DEPS += dest_axi_stream.v
M_DEPS += dest_fifo_inf.v
M_DEPS += inc_id.h
M_DEPS += request_arb.v
M_DEPS += request_generator.v
M_DEPS += resp.h
M_DEPS += response_generator.v
M_DEPS += response_handler.v
M_DEPS += splitter.v
M_DEPS += src_axi_mm.v
M_DEPS += src_axi_stream.v
M_DEPS += src_fifo_inf.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += 2d_transfer.v
GENERIC_DEPS += address_generator.v
GENERIC_DEPS += axi_dmac.v
GENERIC_DEPS += axi_register_slice.v
GENERIC_DEPS += data_mover.v
GENERIC_DEPS += dest_axi_mm.v
GENERIC_DEPS += dest_axi_stream.v
GENERIC_DEPS += dest_fifo_inf.v
GENERIC_DEPS += inc_id.h
GENERIC_DEPS += request_arb.v
GENERIC_DEPS += request_generator.v
GENERIC_DEPS += resp.h
GENERIC_DEPS += response_generator.v
GENERIC_DEPS += response_handler.v
GENERIC_DEPS += splitter.v
GENERIC_DEPS += src_axi_mm.v
GENERIC_DEPS += src_axi_stream.v
GENERIC_DEPS += src_fifo_inf.v
M_DEPS += ../interfaces/fifo_rd.xml
M_DEPS += ../interfaces/fifo_rd_rtl.xml
M_DEPS += ../interfaces/fifo_wr.xml
M_DEPS += ../interfaces/fifo_wr_rtl.xml
XILINX_DEPS += axi_dmac_constr.ttcl
XILINX_DEPS += axi_dmac_ip.tcl
XILINX_DEPS += bd/bd.tcl
LIB_DEPS += util_axis_fifo
LIB_DEPS += util_axis_resize
LIB_DEPS += util_cdc
XILINX_DEPS += ../interfaces/fifo_rd.xml
XILINX_DEPS += ../interfaces/fifo_rd_rtl.xml
XILINX_DEPS += ../interfaces/fifo_wr.xml
XILINX_DEPS += ../interfaces/fifo_wr_rtl.xml
XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_axis_resize
XILINX_LIB_DEPS += util_cdc
ALTERA_DEPS += ../util_axis_fifo/address_gray.v
ALTERA_DEPS += ../util_axis_fifo/address_gray_pipelined.v
ALTERA_DEPS += ../util_axis_fifo/address_sync.v
ALTERA_DEPS += ../util_axis_fifo/util_axis_fifo.v
ALTERA_DEPS += ../util_axis_resize/util_axis_resize.v
ALTERA_DEPS += ../util_cdc/sync_bits.v
ALTERA_DEPS += ../util_cdc/sync_gray.v
ALTERA_DEPS += axi_dmac_constr.sdc
ALTERA_DEPS += axi_dmac_hw.tcl
include ../scripts/library.mk

15
library/axi_fmcadc5_sync/Makefile
View File

@ -5,12 +5,13 @@
LIBRARY_NAME := axi_fmcadc5_sync
M_DEPS += ../common/up_axi.v
M_DEPS += ../xilinx/common/ad_data_out.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += axi_fmcadc5_sync.v
M_DEPS += axi_fmcadc5_sync_calcor.v
M_DEPS += axi_fmcadc5_sync_constr.xdc
M_DEPS += axi_fmcadc5_sync_ip.tcl
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_fmcadc5_sync.v
GENERIC_DEPS += axi_fmcadc5_sync_calcor.v
XILINX_DEPS += ../xilinx/common/ad_data_out.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += axi_fmcadc5_sync_constr.xdc
XILINX_DEPS += axi_fmcadc5_sync_ip.tcl
include ../scripts/library.mk

19
library/axi_generic_adc/Makefile
View File

@ -5,14 +5,15 @@
LIBRARY_NAME := axi_generic_adc
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += axi_generic_adc.v
M_DEPS += axi_generic_adc_ip.tcl
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_generic_adc.v
XILINX_DEPS += axi_generic_adc_ip.tcl
include ../scripts/library.mk

17
library/axi_gpreg/Makefile
View File

@ -5,13 +5,14 @@
LIBRARY_NAME := axi_gpreg
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += axi_gpreg.v
M_DEPS += axi_gpreg_clock_mon.v
M_DEPS += axi_gpreg_constr.xdc
M_DEPS += axi_gpreg_io.v
M_DEPS += axi_gpreg_ip.tcl
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += axi_gpreg.v
GENERIC_DEPS += axi_gpreg_clock_mon.v
GENERIC_DEPS += axi_gpreg_io.v
XILINX_DEPS += axi_gpreg_constr.xdc
XILINX_DEPS += axi_gpreg_ip.tcl
include ../scripts/library.mk

43
library/axi_hdmi_rx/Makefile
View File

@ -5,26 +5,27 @@
LIBRARY_NAME := axi_hdmi_rx
M_DEPS += ../common/ad_csc_1.v
M_DEPS += ../common/ad_csc_1_add.v
M_DEPS += ../common/ad_csc_1_mul.v
M_DEPS += ../common/ad_csc_CrYCb2RGB.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_ss_422to444.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_hdmi_rx.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_hdmi_rx.v
M_DEPS += axi_hdmi_rx_constr.xdc
M_DEPS += axi_hdmi_rx_core.v
M_DEPS += axi_hdmi_rx_es.v
M_DEPS += axi_hdmi_rx_ip.tcl
M_DEPS += axi_hdmi_rx_tpm.v
GENERIC_DEPS += ../common/ad_csc_1.v
GENERIC_DEPS += ../common/ad_csc_1_add.v
GENERIC_DEPS += ../common/ad_csc_1_mul.v
GENERIC_DEPS += ../common/ad_csc_CrYCb2RGB.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_ss_422to444.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_hdmi_rx.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_hdmi_rx.v
GENERIC_DEPS += axi_hdmi_rx_core.v
GENERIC_DEPS += axi_hdmi_rx_es.v
GENERIC_DEPS += axi_hdmi_rx_tpm.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_hdmi_rx_constr.xdc
XILINX_DEPS += axi_hdmi_rx_ip.tcl
include ../scripts/library.mk

55
library/axi_hdmi_tx/Makefile
View File

@ -5,28 +5,37 @@
LIBRARY_NAME := axi_hdmi_tx
M_DEPS += ../common/ad_csc_1.v
M_DEPS += ../common/ad_csc_1_add.v
M_DEPS += ../common/ad_csc_1_mul.v
M_DEPS += ../common/ad_csc_RGB2CrYCb.v
M_DEPS += ../common/ad_mem.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_ss_444to422.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_hdmi_tx.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_hdmi_tx.v
M_DEPS += axi_hdmi_tx_constr.xdc
M_DEPS += axi_hdmi_tx_core.v
M_DEPS += axi_hdmi_tx_es.v
M_DEPS += axi_hdmi_tx_ip.tcl
M_DEPS += axi_hdmi_tx_vdma.v
GENERIC_DEPS += ../common/ad_csc_1.v
GENERIC_DEPS += ../common/ad_csc_1_add.v
GENERIC_DEPS += ../common/ad_csc_1_mul.v
GENERIC_DEPS += ../common/ad_csc_RGB2CrYCb.v
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_ss_444to422.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_hdmi_tx.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_hdmi_tx.v
GENERIC_DEPS += axi_hdmi_tx_core.v
GENERIC_DEPS += axi_hdmi_tx_es.v
GENERIC_DEPS += axi_hdmi_tx_vdma.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_hdmi_tx_constr.xdc
XILINX_DEPS += axi_hdmi_tx_ip.tcl
ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_hdmi_tx_constr.sdc
ALTERA_DEPS += axi_hdmi_tx_hw.tcl
include ../scripts/library.mk

31
library/axi_i2s_adi/Makefile
View File

@ -5,21 +5,22 @@
LIBRARY_NAME := axi_i2s_adi
M_DEPS += ../common/axi_ctrlif.vhd
M_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd
M_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd
M_DEPS += ../common/dma_fifo.vhd
M_DEPS += ../common/pl330_dma_fifo.vhd
M_DEPS += axi_i2s_adi.vhd
M_DEPS += axi_i2s_adi_constr.xdc
M_DEPS += axi_i2s_adi_ip.tcl
M_DEPS += fifo_synchronizer.vhd
M_DEPS += i2s_clkgen.vhd
M_DEPS += i2s_controller.vhd
M_DEPS += i2s_rx.vhd
M_DEPS += i2s_tx.vhd
GENERIC_DEPS += ../common/axi_ctrlif.vhd
GENERIC_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd
GENERIC_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd
GENERIC_DEPS += ../common/dma_fifo.vhd
GENERIC_DEPS += ../common/pl330_dma_fifo.vhd
GENERIC_DEPS += axi_i2s_adi.vhd
GENERIC_DEPS += fifo_synchronizer.vhd
GENERIC_DEPS += i2s_clkgen.vhd
GENERIC_DEPS += i2s_controller.vhd
GENERIC_DEPS += i2s_rx.vhd
GENERIC_DEPS += i2s_tx.vhd
M_DEPS += ../axi_i2s_adi/i2s.xml
M_DEPS += ../axi_i2s_adi/i2s_rtl.xml
XILINX_DEPS += axi_i2s_adi_constr.xdc
XILINX_DEPS += axi_i2s_adi_ip.tcl
XILINX_DEPS += ../axi_i2s_adi/i2s.xml
XILINX_DEPS += ../axi_i2s_adi/i2s_rtl.xml
include ../scripts/library.mk

7
library/axi_intr_monitor/Makefile
View File

@ -5,8 +5,9 @@
LIBRARY_NAME := axi_intr_monitor
M_DEPS += ../common/up_axi.v
M_DEPS += axi_intr_monitor.v
M_DEPS += axi_intr_monitor_ip.tcl
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_intr_monitor.v
XILINX_DEPS += axi_intr_monitor_ip.tcl
include ../scripts/library.mk

25
library/axi_logic_analyzer/Makefile
View File

@ -5,17 +5,18 @@
LIBRARY_NAME := axi_logic_analyzer
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_logic_analyzer.v
M_DEPS += axi_logic_analyzer_constr.xdc
M_DEPS += axi_logic_analyzer_ip.tcl
M_DEPS += axi_logic_analyzer_reg.v
M_DEPS += axi_logic_analyzer_trigger.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_logic_analyzer.v
GENERIC_DEPS += axi_logic_analyzer_reg.v
GENERIC_DEPS += axi_logic_analyzer_trigger.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_logic_analyzer_constr.xdc
XILINX_DEPS += axi_logic_analyzer_ip.tcl
include ../scripts/library.mk

15
library/axi_mc_controller/Makefile
View File

@ -5,12 +5,13 @@
LIBRARY_NAME := axi_mc_controller
M_DEPS += ../common/up_axi.v
M_DEPS += axi_mc_controller.v
M_DEPS += axi_mc_controller_constr.xdc
M_DEPS += axi_mc_controller_ip.tcl
M_DEPS += control_registers.v
M_DEPS += delay.v
M_DEPS += motor_driver.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_mc_controller.v
GENERIC_DEPS += control_registers.v
GENERIC_DEPS += delay.v
GENERIC_DEPS += motor_driver.v
XILINX_DEPS += axi_mc_controller_constr.xdc
XILINX_DEPS += axi_mc_controller_ip.tcl
include ../scripts/library.mk

25
library/axi_mc_current_monitor/Makefile
View File

@ -5,17 +5,18 @@
LIBRARY_NAME := axi_mc_current_monitor
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ad7401.v
M_DEPS += axi_mc_current_monitor.v
M_DEPS += axi_mc_current_monitor_constr.xdc
M_DEPS += axi_mc_current_monitor_ip.tcl
M_DEPS += dec256sinc24b.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += ad7401.v
GENERIC_DEPS += axi_mc_current_monitor.v
GENERIC_DEPS += dec256sinc24b.v
XILINX_DEPS += axi_mc_current_monitor_constr.xdc
XILINX_DEPS += axi_mc_current_monitor_ip.tcl
include ../scripts/library.mk

25
library/axi_mc_speed/Makefile
View File

@ -5,17 +5,18 @@
LIBRARY_NAME := axi_mc_speed
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += axi_mc_speed.v
M_DEPS += axi_mc_speed_constr.xdc
M_DEPS += axi_mc_speed_ip.tcl
M_DEPS += debouncer.v
M_DEPS += delay_30_degrees.v
M_DEPS += speed_detector.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_mc_speed.v
GENERIC_DEPS += debouncer.v
GENERIC_DEPS += delay_30_degrees.v
GENERIC_DEPS += speed_detector.v
XILINX_DEPS += axi_mc_speed_constr.xdc
XILINX_DEPS += axi_mc_speed_ip.tcl
include ../scripts/library.mk

5
library/axi_rd_wr_combiner/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := axi_rd_wr_combiner
M_DEPS += axi_rd_wr_combiner.v
M_DEPS += axi_rd_wr_combiner_ip.tcl
GENERIC_DEPS += axi_rd_wr_combiner.v
XILINX_DEPS += axi_rd_wr_combiner_ip.tcl
include ../scripts/library.mk

23
library/axi_spdif_rx/Makefile
View File

@ -5,16 +5,17 @@
LIBRARY_NAME := axi_spdif_rx
M_DEPS += ../common/axi_ctrlif.vhd
M_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd
M_DEPS += ../common/dma_fifo.vhd
M_DEPS += ../common/pl330_dma_fifo.vhd
M_DEPS += axi_spdif_rx.vhd
M_DEPS += axi_spdif_rx_constr.xdc
M_DEPS += axi_spdif_rx_ip.tcl
M_DEPS += rx_decode.vhd
M_DEPS += rx_package.vhd
M_DEPS += rx_phase_det.vhd
M_DEPS += rx_status_reg.vhd
GENERIC_DEPS += ../common/axi_ctrlif.vhd
GENERIC_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd
GENERIC_DEPS += ../common/dma_fifo.vhd
GENERIC_DEPS += ../common/pl330_dma_fifo.vhd
GENERIC_DEPS += axi_spdif_rx.vhd
GENERIC_DEPS += rx_decode.vhd
GENERIC_DEPS += rx_package.vhd
GENERIC_DEPS += rx_phase_det.vhd
GENERIC_DEPS += rx_status_reg.vhd
XILINX_DEPS += axi_spdif_rx_constr.xdc
XILINX_DEPS += axi_spdif_rx_ip.tcl
include ../scripts/library.mk

19
library/axi_spdif_tx/Makefile
View File

@ -5,14 +5,15 @@
LIBRARY_NAME := axi_spdif_tx
M_DEPS += ../common/axi_ctrlif.vhd
M_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd
M_DEPS += ../common/dma_fifo.vhd
M_DEPS += ../common/pl330_dma_fifo.vhd
M_DEPS += axi_spdif_tx.vhd
M_DEPS += axi_spdif_tx_constr.xdc
M_DEPS += axi_spdif_tx_ip.tcl
M_DEPS += tx_encoder.vhd
M_DEPS += tx_package.vhd
GENERIC_DEPS += ../common/axi_ctrlif.vhd
GENERIC_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd
GENERIC_DEPS += ../common/dma_fifo.vhd
GENERIC_DEPS += ../common/pl330_dma_fifo.vhd
GENERIC_DEPS += axi_spdif_tx.vhd
GENERIC_DEPS += tx_encoder.vhd
GENERIC_DEPS += tx_package.vhd
XILINX_DEPS += axi_spdif_tx_constr.xdc
XILINX_DEPS += axi_spdif_tx_ip.tcl
include ../scripts/library.mk

13
library/axi_usb_fx3/Makefile
View File

@ -5,11 +5,12 @@
LIBRARY_NAME := axi_usb_fx3
M_DEPS += ../common/up_axi.v
M_DEPS += axi_usb_fx3.v
M_DEPS += axi_usb_fx3_core.v
M_DEPS += axi_usb_fx3_if.v
M_DEPS += axi_usb_fx3_ip.tcl
M_DEPS += axi_usb_fx3_reg.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_usb_fx3.v
GENERIC_DEPS += axi_usb_fx3_core.v
GENERIC_DEPS += axi_usb_fx3_if.v
GENERIC_DEPS += axi_usb_fx3_reg.v
XILINX_DEPS += axi_usb_fx3_ip.tcl
include ../scripts/library.mk

9
library/cn0363/cn0363_dma_sequencer/Makefile
View File

@ -5,10 +5,11 @@
LIBRARY_NAME := cn0363_dma_sequencer
M_DEPS += cn0363_dma_sequencer.v
M_DEPS += cn0363_dma_sequencer_ip.tcl
GENERIC_DEPS += cn0363_dma_sequencer.v
M_DEPS += ../../interfaces/fifo_wr.xml
M_DEPS += ../../interfaces/fifo_wr_rtl.xml
XILINX_DEPS += cn0363_dma_sequencer_ip.tcl
XILINX_DEPS += ../../interfaces/fifo_wr.xml
XILINX_DEPS += ../../interfaces/fifo_wr_rtl.xml
include ../../scripts/library.mk

5
library/cn0363/cn0363_phase_data_sync/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := cn0363_phase_data_sync
M_DEPS += cn0363_phase_data_sync.v
M_DEPS += cn0363_phase_data_sync_ip.tcl
GENERIC_DEPS += cn0363_phase_data_sync.v
XILINX_DEPS += cn0363_phase_data_sync_ip.tcl
include ../../scripts/library.mk

5
library/cordic_demod/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := cordic_demod
M_DEPS += cordic_demod.v
M_DEPS += cordic_demod_ip.tcl
GENERIC_DEPS += cordic_demod.v
XILINX_DEPS += cordic_demod_ip.tcl
include ../scripts/library.mk

5
library/interfaces/Makefile
View File

@ -29,8 +29,9 @@ M_FLIST += if_gt_rx_ksig.xml
M_FLIST += if_gt_rx_ksig_rtl.xml
.PHONY: all clean clean-all
all: if_xcvr_cm.xml if_xcvr_cm_rtl.xml if_xcvr_ch.xml if_xcvr_ch_rtl.xml if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml
.PHONY: all xilinx clean clean-all
all: xilinx
xilinx: if_xcvr_cm.xml if_xcvr_cm_rtl.xml if_xcvr_ch.xml if_xcvr_ch_rtl.xml if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml
clean:clean-all

7
library/jesd204/axi_jesd204_common/Makefile
View File

@ -5,8 +5,9 @@
LIBRARY_NAME := axi_jesd204_common
M_DEPS += axi_jesd204_common_ip.tcl
M_DEPS += jesd204_up_common.v
M_DEPS += jesd204_up_sysref.v
GENERIC_DEPS += jesd204_up_common.v
GENERIC_DEPS += jesd204_up_sysref.v
XILINX_DEPS += axi_jesd204_common_ip.tcl
include ../../scripts/library.mk

50
library/jesd204/axi_jesd204_rx/Makefile
View File

@ -5,28 +5,38 @@
LIBRARY_NAME := axi_jesd204_rx
M_DEPS += ../../common/up_axi.v
M_DEPS += ../../common/up_clock_mon.v
M_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += axi_jesd204_rx.v
M_DEPS += axi_jesd204_rx_constr.xdc
M_DEPS += axi_jesd204_rx_ip.tcl
M_DEPS += jesd204_up_ilas_mem.v
M_DEPS += jesd204_up_rx.v
M_DEPS += jesd204_up_rx_lane.v
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += ../../common/up_clock_mon.v
GENERIC_DEPS += axi_jesd204_rx.v
GENERIC_DEPS += jesd204_up_ilas_mem.v
GENERIC_DEPS += jesd204_up_rx.v
GENERIC_DEPS += jesd204_up_rx_lane.v
M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += axi_jesd204_rx_constr.xdc
XILINX_DEPS += axi_jesd204_rx_ip.tcl
LIB_DEPS += jesd204/axi_jesd204_common
LIB_DEPS += util_cdc
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
INTERFACE_DEPS += jesd204/interfaces
XILINX_LIB_DEPS += jesd204/axi_jesd204_common
XILINX_LIB_DEPS += util_cdc
XILINX_INTERFACE_DEPS += jesd204/interfaces
ALTERA_DEPS += ../../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../../util_cdc/sync_bits.v
ALTERA_DEPS += ../../util_cdc/sync_data.v
ALTERA_DEPS += ../../util_cdc/sync_event.v
ALTERA_DEPS += ../axi_jesd204_common/jesd204_up_common.v
ALTERA_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v
ALTERA_DEPS += axi_jesd204_rx_constr.sdc
ALTERA_DEPS += axi_jesd204_rx_hw.tcl
include ../../scripts/library.mk

50
library/jesd204/axi_jesd204_tx/Makefile
View File

@ -5,28 +5,38 @@
LIBRARY_NAME := axi_jesd204_tx
M_DEPS += ../../common/up_axi.v
M_DEPS += ../../common/up_clock_mon.v
M_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += axi_jesd204_tx.v
M_DEPS += axi_jesd204_tx_constr.xdc
M_DEPS += axi_jesd204_tx_ip.tcl
M_DEPS += jesd204_up_tx.v
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += ../../common/up_clock_mon.v
GENERIC_DEPS += axi_jesd204_tx.v
GENERIC_DEPS += jesd204_up_tx.v
M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += axi_jesd204_tx_constr.xdc
XILINX_DEPS += axi_jesd204_tx_ip.tcl
LIB_DEPS += jesd204/axi_jesd204_common
LIB_DEPS += util_cdc
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml
INTERFACE_DEPS += jesd204/interfaces
XILINX_LIB_DEPS += jesd204/axi_jesd204_common
XILINX_LIB_DEPS += util_cdc
XILINX_INTERFACE_DEPS += jesd204/interfaces
ALTERA_DEPS += ../../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../../util_cdc/sync_bits.v
ALTERA_DEPS += ../../util_cdc/sync_data.v
ALTERA_DEPS += ../../util_cdc/sync_event.v
ALTERA_DEPS += ../axi_jesd204_common/jesd204_up_common.v
ALTERA_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v
ALTERA_DEPS += axi_jesd204_tx_constr.sdc
ALTERA_DEPS += axi_jesd204_tx_hw.tcl
include ../../scripts/library.mk

6
library/jesd204/interfaces/Makefile
View File

@ -34,8 +34,10 @@ M_FLIST := *.log
M_FLIST += *.jou
M_FLIST += $(XML_FLIST)
.PHONY: all clean clean-all
all: $(XML_FLIST)
.PHONY: all xilinx clean clean-all
all: xilinx
xilinx: $(XML_FLIST)
clean:clean-all

11
library/jesd204/jesd204_common/Makefile
View File

@ -5,10 +5,11 @@
LIBRARY_NAME := jesd204_common
M_DEPS += eof.v
M_DEPS += jesd204_common_ip.tcl
M_DEPS += lmfc.v
M_DEPS += pipeline_stage.v
M_DEPS += scrambler.v
GENERIC_DEPS += eof.v
GENERIC_DEPS += lmfc.v
GENERIC_DEPS += pipeline_stage.v
GENERIC_DEPS += scrambler.v
XILINX_DEPS += jesd204_common_ip.tcl
include ../../scripts/library.mk

48
library/jesd204/jesd204_rx/Makefile
View File

@ -5,28 +5,36 @@
LIBRARY_NAME := jesd204_rx
M_DEPS += align_mux.v
M_DEPS += elastic_buffer.v
M_DEPS += ilas_monitor.v
M_DEPS += jesd204_rx_constr.xdc
M_DEPS += jesd204_rx_ip.tcl
M_DEPS += lane_latency_monitor.v
M_DEPS += rx.v
M_DEPS += rx_cgs.v
M_DEPS += rx_ctrl.v
M_DEPS += rx_lane.v
GENERIC_DEPS += align_mux.v
GENERIC_DEPS += elastic_buffer.v
GENERIC_DEPS += ilas_monitor.v
GENERIC_DEPS += lane_latency_monitor.v
GENERIC_DEPS += rx.v
GENERIC_DEPS += rx_cgs.v
GENERIC_DEPS += rx_ctrl.v
GENERIC_DEPS += rx_lane.v
M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
XILINX_DEPS += jesd204_rx_constr.xdc
XILINX_DEPS += jesd204_rx_ip.tcl
LIB_DEPS += jesd204/jesd204_common
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
INTERFACE_DEPS += jesd204/interfaces
XILINX_LIB_DEPS += jesd204/jesd204_common
XILINX_INTERFACE_DEPS += jesd204/interfaces
ALTERA_DEPS += ../jesd204_common/eof.v
ALTERA_DEPS += ../jesd204_common/lmfc.v
ALTERA_DEPS += ../jesd204_common/pipeline_stage.v
ALTERA_DEPS += ../jesd204_common/scrambler.v
ALTERA_DEPS += jesd204_rx_constr.sdc
ALTERA_DEPS += jesd204_rx_hw.tcl
include ../../scripts/library.mk

11
library/jesd204/jesd204_rx_static_config/Makefile
View File

@ -5,12 +5,13 @@
LIBRARY_NAME := jesd204_rx_static_config
M_DEPS += jesd204_rx_static_config_ip.tcl
M_DEPS += rx_static_config.v
GENERIC_DEPS += rx_static_config.v
M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
M_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
XILINX_DEPS += jesd204_rx_static_config_ip.tcl
INTERFACE_DEPS += jesd204/interfaces
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
XILINX_INTERFACE_DEPS += jesd204/interfaces
include ../../scripts/library.mk

14
library/jesd204/jesd204_soft_pcs_rx/Makefile Normal file
View File

@ -0,0 +1,14 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := jesd204_soft_pcs_rx
GENERIC_DEPS += 8b10b_decoder.v
GENERIC_DEPS += jesd204_soft_pcs_rx.v
GENERIC_DEPS += pattern_align.v
ALTERA_DEPS += jesd204_soft_pcs_rx_hw.tcl
include ../../scripts/library.mk

13
library/jesd204/jesd204_soft_pcs_tx/Makefile Normal file
View File

@ -0,0 +1,13 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := jesd204_soft_pcs_tx
GENERIC_DEPS += 8b10b_encoder.v
GENERIC_DEPS += jesd204_soft_pcs_tx.v
ALTERA_DEPS += jesd204_soft_pcs_tx_hw.tcl
include ../../scripts/library.mk

44
library/jesd204/jesd204_tx/Makefile
View File

@ -5,26 +5,34 @@
LIBRARY_NAME := jesd204_tx
M_DEPS += jesd204_tx_constr.xdc
M_DEPS += jesd204_tx_ip.tcl
M_DEPS += tx.v
M_DEPS += tx_ctrl.v
M_DEPS += tx_lane.v
GENERIC_DEPS += tx.v
GENERIC_DEPS += tx_ctrl.v
GENERIC_DEPS += tx_lane.v
M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml
XILINX_DEPS += jesd204_tx_constr.xdc
XILINX_DEPS += jesd204_tx_ip.tcl
LIB_DEPS += jesd204/jesd204_common
LIB_DEPS += util_cdc
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml
INTERFACE_DEPS += jesd204/interfaces
XILINX_LIB_DEPS += jesd204/jesd204_common
XILINX_LIB_DEPS += util_cdc
XILINX_INTERFACE_DEPS += jesd204/interfaces
ALTERA_DEPS += ../../util_cdc/sync_bits.v
ALTERA_DEPS += ../jesd204_common/eof.v
ALTERA_DEPS += ../jesd204_common/lmfc.v
ALTERA_DEPS += ../jesd204_common/scrambler.v
ALTERA_DEPS += jesd204_tx_constr.sdc
ALTERA_DEPS += jesd204_tx_hw.tcl
include ../../scripts/library.mk

17
library/jesd204/jesd204_tx_static_config/Makefile
View File

@ -5,15 +5,16 @@
LIBRARY_NAME := jesd204_tx_static_config
M_DEPS += ilas_cfg_static.v
M_DEPS += jesd204_tx_static_config_ip.tcl
M_DEPS += tx_static_config.v
GENERIC_DEPS += ilas_cfg_static.v
GENERIC_DEPS += tx_static_config.v
M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
M_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
XILINX_DEPS += jesd204_tx_static_config_ip.tcl
INTERFACE_DEPS += jesd204/interfaces
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
XILINX_INTERFACE_DEPS += jesd204/interfaces
include ../../scripts/library.mk

47
library/scripts/library.mk
View File

@ -19,28 +19,53 @@ CLEAN_TARGET += *.srcs
CLEAN_TARGET += *.hw
CLEAN_TARGET += *.sim
CLEAN_TARGET += .Xil
CLEAN_TARGET += .timestamp_altera
M_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_env.tcl
M_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip.tcl
GENERIC_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_env.tcl
M_DEPS += $(foreach dep,$(LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/component.xml)
.PHONY: all altera altera_dep xilinx xilinx_dep clean clean-all
.PHONY: all dep clean clean-all
all: dep component.xml
all: altera xilinx
clean: clean-all
clean-all:
rm -rf $(CLEAN_TARGET)
component.xml: $(M_DEPS)
ifneq ($(ALTERA_DEPS),)
ALTERA_DEPS += $(GENERIC_DEPS)
ALTERA_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip_alt.tcl
ALTERA_DEPS += $(foreach dep,$(ALTERA_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/.timestamp_altera)
altera: altera_dep .timestamp_altera
.timestamp_altera: $(ALTERA_DEPS)
touch $@
altera_dep:
@for lib in $(ALTERA_LIB_DEPS); do \
$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} altera || exit $$?; \
done
endif
ifneq ($(XILINX_DEPS),)
XILINX_DEPS += $(GENERIC_DEPS)
XILINX_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip.tcl
XILINX_DEPS += $(foreach dep,$(XILINX_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/component.xml)
xilinx: xilinx_dep component.xml
component.xml: $(XILINX_DEPS)
-rm -rf $(CLEAN_TARGET)
$(VIVADO) $(LIBRARY_NAME)_ip.tcl >> $(LIBRARY_NAME)_ip.log 2>&1
dep:
@for lib in $(LIB_DEPS); do \
$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} || exit $$?; \
xilinx_dep:
@for lib in $(XILINX_LIB_DEPS); do \
$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} xilinx || exit $$?; \
done
@for intf in $(INTERFACE_DEPS); do \
$(MAKE) -C $(HDL_LIBRARY_PATH)$${intf} || exit $$?; \
@for intf in $(XILINX_INTERFACE_DEPS); do \
$(MAKE) -C $(HDL_LIBRARY_PATH)$${intf} xilinx || exit $$?; \
done
endif

21
library/spi_engine/axi_spi_engine/Makefile
View File

@ -5,17 +5,18 @@
LIBRARY_NAME := axi_spi_engine
M_DEPS += ../../common/ad_rst.v
M_DEPS += ../../common/up_axi.v
M_DEPS += axi_spi_engine.v
M_DEPS += axi_spi_engine_ip.tcl
GENERIC_DEPS += axi_spi_engine.v
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_DEPS += ../../common/ad_rst.v
XILINX_DEPS += ../../common/up_axi.v
XILINX_DEPS += axi_spi_engine_ip.tcl
LIB_DEPS += util_axis_fifo
LIB_DEPS += util_cdc
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_cdc
include ../../scripts/library.mk

13
library/spi_engine/spi_engine_execution/Makefile
View File

@ -5,12 +5,13 @@
LIBRARY_NAME := spi_engine_execution
M_DEPS += spi_engine_execution.v
M_DEPS += spi_engine_execution_ip.tcl
GENERIC_DEPS += spi_engine_execution.v
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
M_DEPS += ../../spi_engine/interfaces/spi_master.xml
M_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml
XILINX_DEPS += spi_engine_execution_ip.tcl
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_master.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml
include ../../scripts/library.mk

9
library/spi_engine/spi_engine_interconnect/Makefile
View File

@ -5,10 +5,11 @@
LIBRARY_NAME := spi_engine_interconnect
M_DEPS += spi_engine_interconnect.v
M_DEPS += spi_engine_interconnect_ip.tcl
GENERIC_DEPS += spi_engine_interconnect.v
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += spi_engine_interconnect_ip.tcl
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
include ../../scripts/library.mk

15
library/spi_engine/spi_engine_offload/Makefile
View File

@ -5,14 +5,15 @@
LIBRARY_NAME := spi_engine_offload
M_DEPS += spi_engine_offload.v
M_DEPS += spi_engine_offload_ip.tcl
GENERIC_DEPS += spi_engine_offload.v
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_DEPS += spi_engine_offload_ip.tcl
LIB_DEPS += util_cdc
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_cdc
include ../../scripts/library.mk

14
library/util_adcfifo/Makefile
View File

@ -5,10 +5,14 @@
LIBRARY_NAME := util_adcfifo
M_DEPS += ../common/ad_axis_inf_rx.v
M_DEPS += ../common/ad_mem_asym.v
M_DEPS += util_adcfifo.v
M_DEPS += util_adcfifo_constr.xdc
M_DEPS += util_adcfifo_ip.tcl
GENERIC_DEPS += ../common/ad_axis_inf_rx.v
GENERIC_DEPS += util_adcfifo.v
XILINX_DEPS += ../common/ad_mem_asym.v
XILINX_DEPS += util_adcfifo_constr.xdc
XILINX_DEPS += util_adcfifo_ip.tcl
ALTERA_DEPS += util_adcfifo_constr.sdc
ALTERA_DEPS += util_adcfifo_hw.tcl
include ../scripts/library.mk

15
library/util_axis_fifo/Makefile
View File

@ -5,13 +5,14 @@
LIBRARY_NAME := util_axis_fifo
M_DEPS += ../common/ad_mem.v
M_DEPS += address_gray.v
M_DEPS += address_gray_pipelined.v
M_DEPS += address_sync.v
M_DEPS += util_axis_fifo.v
M_DEPS += util_axis_fifo_ip.tcl
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += address_gray.v
GENERIC_DEPS += address_gray_pipelined.v
GENERIC_DEPS += address_sync.v
GENERIC_DEPS += util_axis_fifo.v
LIB_DEPS += util_cdc
XILINX_DEPS += util_axis_fifo_ip.tcl
XILINX_LIB_DEPS += util_cdc
include ../scripts/library.mk

5
library/util_axis_resize/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := util_axis_resize
M_DEPS += util_axis_resize.v
M_DEPS += util_axis_resize_ip.tcl
GENERIC_DEPS += util_axis_resize.v
XILINX_DEPS += util_axis_resize_ip.tcl
include ../scripts/library.mk

5
library/util_axis_upscale/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := util_axis_upscale
M_DEPS += ../common/util_axis_upscale.v
M_DEPS += util_axis_upscale_ip.tcl
GENERIC_DEPS += ../common/util_axis_upscale.v
XILINX_DEPS += util_axis_upscale_ip.tcl
include ../scripts/library.mk

9
library/util_bsplit/Makefile
View File

@ -5,8 +5,11 @@
LIBRARY_NAME := util_bsplit
M_DEPS += util_bsplit.v
M_DEPS += util_bsplit_constr.xdc
M_DEPS += util_bsplit_ip.tcl
GENERIC_DEPS += util_bsplit.v
XILINX_DEPS += util_bsplit_constr.xdc
XILINX_DEPS += util_bsplit_ip.tcl
ALTERA_DEPS += util_bsplit_hw.tcl
include ../scripts/library.mk

11
library/util_cdc/Makefile
View File

@ -5,10 +5,11 @@
LIBRARY_NAME := util_cdc
M_DEPS += sync_bits.v
M_DEPS += sync_data.v
M_DEPS += sync_event.v
M_DEPS += sync_gray.v
M_DEPS += util_cdc_ip.tcl
GENERIC_DEPS += sync_bits.v
GENERIC_DEPS += sync_data.v
GENERIC_DEPS += sync_event.v
GENERIC_DEPS += sync_gray.v
XILINX_DEPS += util_cdc_ip.tcl
include ../scripts/library.mk

7
library/util_cic/Makefile
View File

@ -5,8 +5,9 @@
LIBRARY_NAME := util_cic
M_DEPS += cic_comb.v
M_DEPS += cic_int.v
M_DEPS += util_cic_ip.tcl
GENERIC_DEPS += cic_comb.v
GENERIC_DEPS += cic_int.v
XILINX_DEPS += util_cic_ip.tcl
include ../scripts/library.mk

10
library/util_clkdiv/Makefile
View File

@ -5,8 +5,12 @@
LIBRARY_NAME := util_clkdiv
M_DEPS += util_clkdiv.v
M_DEPS += util_clkdiv_constr.xdc
M_DEPS += util_clkdiv_ip.tcl
XILINX_DEPS += util_clkdiv.v
XILINX_DEPS += util_clkdiv_constr.xdc
XILINX_DEPS += util_clkdiv_ip.tcl
ALTERA_DEPS += util_clkdiv_alt.v
ALTERA_DEPS += util_clkdiv_hw.tcl
include ../scripts/library.mk

13
library/util_cpack/Makefile
View File

@ -5,10 +5,13 @@
LIBRARY_NAME := util_cpack
M_DEPS += util_cpack.v
M_DEPS += util_cpack_constr.xdc
M_DEPS += util_cpack_dsf.v
M_DEPS += util_cpack_ip.tcl
M_DEPS += util_cpack_mux.v
GENERIC_DEPS += util_cpack.v
GENERIC_DEPS += util_cpack_dsf.v
GENERIC_DEPS += util_cpack_mux.v
XILINX_DEPS += util_cpack_constr.xdc
XILINX_DEPS += util_cpack_ip.tcl
ALTERA_DEPS += util_cpack_hw.tcl
include ../scripts/library.mk

16
library/util_dacfifo/Makefile
View File

@ -5,11 +5,15 @@
LIBRARY_NAME := util_dacfifo
M_DEPS += ../common/ad_b2g.v
M_DEPS += ../common/ad_g2b.v
M_DEPS += ../common/ad_mem.v
M_DEPS += util_dacfifo.v
M_DEPS += util_dacfifo_constr.xdc
M_DEPS += util_dacfifo_ip.tcl
GENERIC_DEPS += ../common/ad_b2g.v
GENERIC_DEPS += ../common/ad_g2b.v
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += util_dacfifo.v
XILINX_DEPS += util_dacfifo_constr.xdc
XILINX_DEPS += util_dacfifo_ip.tcl
ALTERA_DEPS += util_dacfifo_constr.sdc
ALTERA_DEPS += util_dacfifo_hw.tcl
include ../scripts/library.mk

5
library/util_delay/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := util_delay
M_DEPS += ../common/util_delay.v
M_DEPS += util_delay_ip.tcl
GENERIC_DEPS += ../common/util_delay.v
XILINX_DEPS += util_delay_ip.tcl
include ../scripts/library.mk

5
library/util_extract/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := util_extract
M_DEPS += util_extract.v
M_DEPS += util_extract_ip.tcl
GENERIC_DEPS += util_extract.v
XILINX_DEPS += util_extract_ip.tcl
include ../scripts/library.mk

5
library/util_fir_dec/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := util_fir_dec
M_DEPS += util_fir_dec.v
M_DEPS += util_fir_dec_ip.tcl
GENERIC_DEPS += util_fir_dec.v
XILINX_DEPS += util_fir_dec_ip.tcl
include ../scripts/library.mk

5
library/util_fir_int/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := util_fir_int
M_DEPS += util_fir_int.v
M_DEPS += util_fir_int_ip.tcl
GENERIC_DEPS += util_fir_int.v
XILINX_DEPS += util_fir_int_ip.tcl
include ../scripts/library.mk

9
library/util_gmii_to_rgmii/Makefile
View File

@ -5,9 +5,10 @@
LIBRARY_NAME := util_gmii_to_rgmii
M_DEPS += mdc_mdio.v
M_DEPS += util_gmii_to_rgmii.v
M_DEPS += util_gmii_to_rgmii_constr.xdc
M_DEPS += util_gmii_to_rgmii_ip.tcl
GENERIC_DEPS += mdc_mdio.v
GENERIC_DEPS += util_gmii_to_rgmii.v
XILINX_DEPS += util_gmii_to_rgmii_constr.xdc
XILINX_DEPS += util_gmii_to_rgmii_ip.tcl
include ../scripts/library.mk

5
library/util_i2c_mixer/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := util_i2c_mixer
M_DEPS += util_i2c_mixer.vhd
M_DEPS += util_i2c_mixer_ip.tcl
GENERIC_DEPS += util_i2c_mixer.vhd
XILINX_DEPS += util_i2c_mixer_ip.tcl
include ../scripts/library.mk

7
library/util_mfifo/Makefile
View File

@ -5,8 +5,9 @@
LIBRARY_NAME := util_mfifo
M_DEPS += ../common/ad_mem.v
M_DEPS += util_mfifo.v
M_DEPS += util_mfifo_ip.tcl
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += util_mfifo.v
XILINX_DEPS += util_mfifo_ip.tcl
include ../scripts/library.mk

5
library/util_pulse_gen/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := util_pulse_gen
M_DEPS += ../common/util_pulse_gen.v
M_DEPS += util_pulse_gen_ip.tcl
GENERIC_DEPS += ../common/util_pulse_gen.v
XILINX_DEPS += util_pulse_gen_ip.tcl
include ../scripts/library.mk

12
library/util_rfifo/Makefile
View File

@ -5,9 +5,13 @@
LIBRARY_NAME := util_rfifo
M_DEPS += ../common/ad_mem.v
M_DEPS += util_rfifo.v
M_DEPS += util_rfifo_constr.xdc
M_DEPS += util_rfifo_ip.tcl
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += util_rfifo.v
XILINX_DEPS += util_rfifo_constr.xdc
XILINX_DEPS += util_rfifo_ip.tcl
ALTERA_DEPS += util_rfifo_constr.sdc
ALTERA_DEPS += util_rfifo_hw.tcl
include ../scripts/library.mk

9
library/util_sigma_delta_spi/Makefile
View File

@ -5,10 +5,11 @@
LIBRARY_NAME := util_sigma_delta_spi
M_DEPS += util_sigma_delta_spi.v
M_DEPS += util_sigma_delta_spi_ip.tcl
GENERIC_DEPS += util_sigma_delta_spi.v
M_DEPS += ../spi_engine/interfaces/spi_master.xml
M_DEPS += ../spi_engine/interfaces/spi_master_rtl.xml
XILINX_DEPS += util_sigma_delta_spi_ip.tcl
XILINX_DEPS += ../spi_engine/interfaces/spi_master.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_master_rtl.xml
include ../scripts/library.mk

9
library/util_tdd_sync/Makefile
View File

@ -5,9 +5,10 @@
LIBRARY_NAME := util_tdd_sync
M_DEPS += ../common/util_pulse_gen.v
M_DEPS += util_tdd_sync.v
M_DEPS += util_tdd_sync_constr.xdc
M_DEPS += util_tdd_sync_ip.tcl
GENERIC_DEPS += ../common/util_pulse_gen.v
GENERIC_DEPS += util_tdd_sync.v
XILINX_DEPS += util_tdd_sync_constr.xdc
XILINX_DEPS += util_tdd_sync_ip.tcl
include ../scripts/library.mk

13
library/util_upack/Makefile
View File

@ -5,10 +5,13 @@
LIBRARY_NAME := util_upack
M_DEPS += util_upack.v
M_DEPS += util_upack_constr.xdc
M_DEPS += util_upack_dmx.v
M_DEPS += util_upack_dsf.v
M_DEPS += util_upack_ip.tcl
GENERIC_DEPS += util_upack.v
GENERIC_DEPS += util_upack_dmx.v
GENERIC_DEPS += util_upack_dsf.v
XILINX_DEPS += util_upack_constr.xdc
XILINX_DEPS += util_upack_ip.tcl
ALTERA_DEPS += util_upack_hw.tcl
include ../scripts/library.mk

5
library/util_var_fifo/Makefile
View File

@ -5,7 +5,8 @@
LIBRARY_NAME := util_var_fifo
M_DEPS += util_var_fifo.v
M_DEPS += util_var_fifo_ip.tcl
GENERIC_DEPS += util_var_fifo.v
XILINX_DEPS += util_var_fifo_ip.tcl
include ../scripts/library.mk

12
library/util_wfifo/Makefile
View File

@ -5,9 +5,13 @@
LIBRARY_NAME := util_wfifo
M_DEPS += ../common/ad_mem.v
M_DEPS += util_wfifo.v
M_DEPS += util_wfifo_constr.xdc
M_DEPS += util_wfifo_ip.tcl
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += util_wfifo.v
XILINX_DEPS += util_wfifo_constr.xdc
XILINX_DEPS += util_wfifo_ip.tcl
ALTERA_DEPS += util_wfifo_constr.sdc
ALTERA_DEPS += util_wfifo_hw.tcl
include ../scripts/library.mk

22
library/xilinx/axi_adcfifo/Makefile
View File

@ -5,16 +5,16 @@
LIBRARY_NAME := axi_adcfifo
M_DEPS += ../../common/ad_axis_inf_rx.v
M_DEPS += ../../common/ad_mem.v
M_DEPS += ../../common/ad_mem_asym.v
M_DEPS += ../../common/up_xfer_status.v
M_DEPS += axi_adcfifo.v
M_DEPS += axi_adcfifo_adc.v
M_DEPS += axi_adcfifo_constr.xdc
M_DEPS += axi_adcfifo_dma.v
M_DEPS += axi_adcfifo_ip.tcl
M_DEPS += axi_adcfifo_rd.v
M_DEPS += axi_adcfifo_wr.v
XILINX_DEPS += ../../common/ad_axis_inf_rx.v
XILINX_DEPS += ../../common/ad_mem.v
XILINX_DEPS += ../../common/ad_mem_asym.v
XILINX_DEPS += ../../common/up_xfer_status.v
XILINX_DEPS += axi_adcfifo.v
XILINX_DEPS += axi_adcfifo_adc.v
XILINX_DEPS += axi_adcfifo_constr.xdc
XILINX_DEPS += axi_adcfifo_dma.v
XILINX_DEPS += axi_adcfifo_ip.tcl
XILINX_DEPS += axi_adcfifo_rd.v
XILINX_DEPS += axi_adcfifo_wr.v
include ../../scripts/library.mk

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