From 2a34f9baa8a20320a36468d36ff0a8e323b99e9f Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 12 Sep 2016 11:45:23 -0400 Subject: [PATCH] alt-serdes, in & out --- library/altera/alt_serdes/alt_serdes_hw.tcl | 49 +++++--- library/altera/common/ad_serdes_in.v | 123 +++++++------------- library/altera/common/ad_serdes_out.v | 96 ++++++--------- 3 files changed, 111 insertions(+), 157 deletions(-) diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl index cdc6b8f37..a9ec823ec 100644 --- a/library/altera/alt_serdes/alt_serdes_hw.tcl +++ b/library/altera/alt_serdes/alt_serdes_hw.tcl @@ -99,31 +99,52 @@ proc p_alt_serdes {} { if {$m_mode == "IN"} { add_hdl_instance alt_serdes_in altera_lvds - set_instance_parameter_value alt_serdes_in {DATA_RATE} {600.0} set_instance_parameter_value alt_serdes_in {MODE} {dpa_mode_fifo} set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1} - set_instance_parameter_value alt_serdes_in {J_FACTOR} {8} - set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} {100} - set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false} - set_instance_parameter_value alt_serdes_in {TX_EXPORT_CORECLOCK} {false} - set_instance_parameter_value alt_serdes_in {TX_USE_OUTCLOCK} {false} + set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true} - set_instance_parameter_value alt_serdes_in {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY + set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false} + add_interface data_in conduit end + set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in + add_interface clk clock sink + set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden + add_interface div_clk clock sink + set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock + add_interface hs_phase conduit end + set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph + add_interface locked conduit end + set_interface_property locked EXPORT_OF alt_serdes_in.ext_pll_locked + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out + add_interface delay_locked conduit end + set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked } if {$m_mode == "OUT"} { add_hdl_instance alt_serdes_out altera_lvds - set_instance_parameter_value alt_serdes_out {DATA_RATE} {600.0} set_instance_parameter_value alt_serdes_out {MODE} {TX} set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1} - set_instance_parameter_value alt_serdes_out {J_FACTOR} {8} - set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} {100} - set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false} - set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false} - set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false} + set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true} - set_instance_parameter_value alt_serdes_out {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY + set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false} + set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false} + add_interface data_out conduit end + set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out + add_interface clk clock sink + set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden + add_interface div_clk clock sink + set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in } } diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v index 57e9da911..9b99895a8 100644 --- a/library/altera/common/ad_serdes_in.v +++ b/library/altera/common/ad_serdes_in.v @@ -35,108 +35,69 @@ // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** + `timescale 1ps/1ps module ad_serdes_in ( // reset and clocks - rst, - clk, - div_clk, - loaden, - clk_phase, + input rst, + input clk, + input div_clk, + input loaden, + input hs_phase, // data interface - data_s0, - data_s1, - data_s2, - data_s3, - data_s4, - data_s5, - data_s6, - data_s7, - data_in_p, - data_in_n, + output data_s0, + output data_s1, + output data_s2, + output data_s3, + output data_s4, + output data_s5, + output data_s6, + output data_s7, + input data_in_p, + input data_in_n, // delay-data interface - up_clk, - up_dld, - up_dwdata, - up_drdata, + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, // delay-control interface - delay_clk, - delay_rst, - delay_locked); + input delay_clk, + input delay_rst, + output delay_locked); // parameters parameter DEVICE_TYPE = 0; - // reset and clocks + // instantiations - input rst; - input clk; - input div_clk; - input loaden; - input clk_phase; - - // data interface - - output data_s0; - output data_s1; - output data_s2; - output data_s3; - output data_s4; - output data_s5; - output data_s6; - output data_s7; - input data_in_p; - input data_in_n; - - // delay-data interface - - input up_clk; - input up_dld; - input [ 4:0] up_dwdata; - output [ 4:0] up_drdata; - - // delay-control interface - - input delay_clk; - input delay_rst; - output delay_locked; - - // internal signals - - wire [ 7:0] data_out_s; - - assign data_s0 = data_out_s[0]; - assign data_s1 = data_out_s[1]; - assign data_s2 = data_out_s[2]; - assign data_s2 = data_out_s[2]; - assign data_s3 = data_out_s[3]; - assign data_s4 = data_out_s[4]; - assign data_s5 = data_out_s[5]; - assign data_s6 = data_out_s[6]; - assign data_s7 = data_out_s[7]; - - altera_lvds_in i_altera_lvds_in ( - .ext_coreclock (div_clk), // ext_coreclock.export - .ext_fclk (clk), // ext_fclk.export - .ext_loaden (loaden), // ext_loaden.export - .ext_pll_locked (), // ext_pll_locked.export - .ext_vcoph (clk_phase), // ext_vcoph.export - .rx_dpa_locked (delay_locked), // rx_dpa_locked.export - .rx_in (data_in_p), // rx_in.export - .rx_out (data_out_s) // rx_out.export - ); + alt_serdes_in_core i_core ( + .data_in (data_in_p), + .clk (clk), + .loaden (loaden), + .div_clk (div_clk), + .hs_phase (hs_phase), + .locked (locked), + .data_s ({data_s7, + data_s6, + data_s5, + data_s4, + data_s3, + data_s2, + data_s1, + data_s0}), + .delay_locked (delay_locked)); endmodule +// *************************************************************************** +// *************************************************************************** diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v index e89c8ea05..45ccc4036 100644 --- a/library/altera/common/ad_serdes_out.v +++ b/library/altera/common/ad_serdes_out.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** // serial data output interface: serdes(x8) `timescale 1ps/1ps @@ -44,82 +42,56 @@ module ad_serdes_out ( // reset and clocks - rst, - clk, - div_clk, - loaden, + input rst, + input clk, + input div_clk, + input loaden, // data interface - data_s0, - data_s1, - data_s2, - data_s3, - data_s4, - data_s5, - data_s6, - data_s7, - data_out_p, - data_out_n); + input [(DATA_WIDTH-1):0] data_s0, + input [(DATA_WIDTH-1):0] data_s1, + input [(DATA_WIDTH-1):0] data_s2, + input [(DATA_WIDTH-1):0] data_s3, + input [(DATA_WIDTH-1):0] data_s4, + input [(DATA_WIDTH-1):0] data_s5, + input [(DATA_WIDTH-1):0] data_s6, + input [(DATA_WIDTH-1):0] data_s7, + output [(DATA_WIDTH-1):0] data_out_p, + output [(DATA_WIDTH-1):0] data_out_n); // parameters parameter DEVICE_TYPE = 0; parameter DATA_WIDTH = 16; - localparam DW = DATA_WIDTH - 1; - - // reset and clocks - - input rst; - input clk; - input div_clk; - input loaden; - - // data interface - - input [DW:0] data_s0; - input [DW:0] data_s1; - input [DW:0] data_s2; - input [DW:0] data_s3; - input [DW:0] data_s4; - input [DW:0] data_s5; - input [DW:0] data_s6; - input [DW:0] data_s7; - output [DW:0] data_out_p; - output [DW:0] data_out_n; - // internal signals - wire [DW:0] data_out_s; - wire [ 7:0] data_in_s[DW:0]; + wire [(DATA_WIDTH-1):0] data_out_s; + wire [ 7:0] data_in_s[(DATA_WIDTH-1):0]; + + // defaults + + assign data_out_n = 'd0; // instantiations - assign data_out_p = data_out_s; - assign data_out_n = 0; // differential pair will be defined by the Pin Planner - genvar l_inst; generate - for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data - - assign data_in_s[l_inst] = {data_s7[l_inst], - data_s6[l_inst], - data_s5[l_inst], - data_s4[l_inst], - data_s3[l_inst], - data_s2[l_inst], - data_s1[l_inst], - data_s0[l_inst]}; - - alt_serdes_out i_alt_serdes_out ( - .ext_coreclock (div_clk), // ext_coreclock.export - .ext_fclk (clk), // ext_fclk.export - .ext_loaden (loaden), // ext_loaden.export - .tx_in (data_in_s[l_inst]), // tx_in.export - .tx_out (data_out_s[l_inst]) // tx_out.export - ); - + for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data + alt_serdes_out_core i_core ( + .data_out (data_out_p[l_inst]), + .clk (clk), + .loaden (loaden), + .div_clk (div_clk), + .data_s ({data_s7[l_inst], + data_s6[l_inst], + data_s5[l_inst], + data_s4[l_inst], + data_s3[l_inst], + data_s2[l_inst], + data_s1[l_inst], + data_s0[l_inst]})); end endgenerate