zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fifo2s: flush if no request, c5soc: 14.0

main
Rejeesh Kutty 2014-07-15 16:24:26 -04:00
parent e7d5d79e42
commit 2955b9db78
8 changed files with 150 additions and 80 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
library/axi_ad9361/axi_ad9361_dev_if.v
View File

@ -158,8 +158,6 @@ module axi_ad9361_dev_if (
// internal registers
reg [ 5:0] rx_data_n = 'd0;
reg rx_frame_n = 'd0;
reg [11:0] rx_data = 'd0;
reg [ 1:0] rx_frame = 'd0;
reg [11:0] rx_data_d = 'd0;
@ -240,10 +238,8 @@ module axi_ad9361_dev_if (
assign rx_frame_s = {rx_frame_d, rx_frame};
always @(posedge l_clk) begin
rx_data_n <= rx_data_n_s;
rx_frame_n <= rx_frame_n_s;
rx_data <= {rx_data_n, rx_data_p_s};
rx_frame <= {rx_frame_n, rx_frame_p_s};
rx_data <= {rx_data_n_s, rx_data_p_s};
rx_frame <= {rx_frame_n_s, rx_frame_p_s};
rx_data_d <= rx_data;
rx_frame_d <= rx_frame;
end

3
library/axi_fifo2s/axi_fifo2s.v
View File

@ -49,6 +49,7 @@ module axi_fifo2s (
m_wdata,
m_wovf,
axi_mrstn,
axi_mwr,
axi_mwdata,
axi_mwovf,
@ -122,6 +123,7 @@ module axi_fifo2s (
input [DATA_WIDTH-1:0] m_wdata;
output m_wovf;
output axi_mrstn;
output axi_mwr;
output [DATA_WIDTH-1:0] axi_mwdata;
input axi_mwovf;
@ -304,6 +306,7 @@ module axi_fifo2s (
.axi_rdata (axi_rdata),
.axi_rready (axi_rready),
.axi_rerror (axi_rerror_s),
.axi_mrstn (axi_mrstn),
.axi_mwr (axi_mwr),
.axi_mwdata (axi_mwdata),
.axi_mwpfull (axi_mwpfull));

23
library/axi_fifo2s/axi_fifo2s_rd.v
View File

@ -77,6 +77,7 @@ module axi_fifo2s_rd (
// fifo interface
axi_mrstn,
axi_mwr,
axi_mwdata,
axi_mwpfull);
@ -128,6 +129,7 @@ module axi_fifo2s_rd (
// fifo interface
output axi_mrstn;
output axi_mwr;
output [DATA_WIDTH-1:0] axi_mwdata;
input axi_mwpfull;
@ -139,13 +141,14 @@ module axi_fifo2s_rd (
reg axi_rd_active = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg axi_xfer_enable = 'd0;
reg axi_arvalid = 'd0;
reg [ 31:0] axi_araddr = 'd0;
reg axi_mrstn = 'd0;
reg axi_mwr = 'd0;
reg [DATA_WIDTH-1:0] axi_mwdata = 'd0;
reg axi_rready = 'd0;
reg axi_rerror = 'd0;
reg axi_reset = 'd0;
// internal signals
@ -162,6 +165,7 @@ module axi_fifo2s_rd (
axi_rd_active <= 'd0;
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
axi_xfer_enable <= 'd0;
end else begin
if (axi_xfer_init == 1'b1) begin
axi_rd_addr_h <= AXI_ADDRESS;
@ -174,11 +178,12 @@ module axi_fifo2s_rd (
axi_rd_active <= 1'b0;
end
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin
axi_rd <= 1'b1;
axi_rd_active <= 1'b1;
axi_rd <= axi_xfer_enable;
axi_rd_active <= axi_xfer_enable;
end
axi_xfer_req_m <= {axi_xfer_req_m[1:0], axi_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
axi_xfer_enable <= axi_xfer_req_m[2];
end
end
@ -220,10 +225,12 @@ module axi_fifo2s_rd (
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_mrstn <= 'd0;
axi_mwr <= 'd0;
axi_mwdata <= 'd0;
axi_rready <= 'd0;
end else begin
axi_mrstn <= axi_xfer_enable;
axi_mwr <= axi_rvalid & axi_rready;
axi_mwdata <= axi_rdata;
axi_rready <= 1'b1;
@ -238,16 +245,6 @@ module axi_fifo2s_rd (
end
end
// fifo needs a reset
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_reset <= 1'b1;
end else begin
axi_reset <= 1'b0;
end
end
endmodule
// ***************************************************************************

11
library/common/ad_lvds_in.v
View File

@ -83,8 +83,13 @@ module ad_lvds_in (
output [ 4:0] delay_rdata;
output delay_locked;
// internal registers
reg rx_data_n;
// internal signals
wire rx_data_n_s;
wire rx_data_ibuf_s;
wire rx_data_idelay_s;
@ -173,7 +178,11 @@ module ad_lvds_in (
.C (rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n));
.Q2 (rx_data_n_s));
always @(posedge rx_clk) begin
rx_data_n <= rx_data_n_s;
end
endmodule

6
projects/common/zc706/zc706_system_plddr3.tcl
View File

@ -44,7 +44,7 @@ proc p_plddr3_fifo {p_name m_name m_width} {
set_property -dict [list CONFIG.INTERFACE_TYPE {Native}] $wfifo_mem
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $wfifo_mem
set_property -dict [list CONFIG.Input_Data_Width $m_width] $wfifo_mem
set_property -dict [list CONFIG.Input_Depth {32}] $wfifo_mem
set_property -dict [list CONFIG.Input_Depth {64}] $wfifo_mem
set_property -dict [list CONFIG.Output_Data_Width {512}] $wfifo_mem
set_property -dict [list CONFIG.Overflow_Flag {true}] $wfifo_mem
@ -91,7 +91,6 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_net -net dma_rstn [get_bd_pins dma_rstn]
connect_bd_net -net dma_rstn [get_bd_pins axi_ddr_cntrl/aresetn]
connect_bd_net -net dma_rstn [get_bd_pins axi_fifo2s/axi_resetn]
connect_bd_net -net dma_rstn [get_bd_pins rfifo_ctl/rstn]
connect_bd_net -net dma_rstn [get_bd_pins wfifo_ctl/rstn]
connect_bd_net -net dma_clk [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0]
connect_bd_net -net dma_clk [get_bd_pins rfifo_ctl/s_clk]
@ -117,7 +116,7 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_net -net wfifo_ctl_fifo_rd [get_bd_pins wfifo_ctl/fifo_rd] [get_bd_pins wfifo_mem/rd_en]
connect_bd_net -net wfifo_ctl_fifo_rdata [get_bd_pins wfifo_ctl/fifo_rdata] [get_bd_pins wfifo_mem/dout]
connect_bd_net -net wfifo_ctl_fifo_rempty [get_bd_pins wfifo_ctl/fifo_rempty] [get_bd_pins wfifo_mem/empty]
connect_bd_net -net rfifo_ctl_fifo_rst [get_bd_pins rfifo_ctl/fifo_rst] [get_bd_pins rfifo_mem/rst]
connect_bd_net -net rfifo_ctl_fifo_rst [get_bd_pins rfifo_ctl/fifo_rst] [get_bd_pins rfifo_mem/rst]
connect_bd_net -net rfifo_ctl_fifo_wr [get_bd_pins rfifo_ctl/fifo_wr] [get_bd_pins rfifo_mem/wr_en]
connect_bd_net -net rfifo_ctl_fifo_wdata [get_bd_pins rfifo_ctl/fifo_wdata] [get_bd_pins rfifo_mem/din]
connect_bd_net -net rfifo_ctl_fifo_wfull [get_bd_pins rfifo_ctl/fifo_wfull] [get_bd_pins rfifo_mem/full]
@ -125,6 +124,7 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_net -net axi_fifo2s_swr [get_bd_pins axi_fifo2s/m_wr] [get_bd_pins wfifo_ctl/s_wr]
connect_bd_net -net axi_fifo2s_swdata [get_bd_pins axi_fifo2s/m_wdata] [get_bd_pins wfifo_ctl/s_wdata]
connect_bd_net -net axi_fifo2s_swovf [get_bd_pins axi_fifo2s/m_wovf] [get_bd_pins wfifo_ctl/s_wovf]
connect_bd_net -net axi_fifo2s_axi_mrst [get_bd_pins axi_fifo2s/axi_mrst] [get_bd_pins rfifo_ctl/rstn]
connect_bd_net -net axi_fifo2s_axi_mwr [get_bd_pins axi_fifo2s/axi_mwr] [get_bd_pins rfifo_ctl/m_wr]
connect_bd_net -net axi_fifo2s_axi_mwdata [get_bd_pins axi_fifo2s/axi_mwdata] [get_bd_pins rfifo_ctl/m_wdata]
connect_bd_net -net axi_fifo2s_axi_mwovf [get_bd_pins axi_fifo2s/axi_mwovf] [get_bd_pins rfifo_ctl/m_wovf]

4
projects/daq2/zc706/system_constr.xdc
View File

@ -57,10 +57,14 @@ create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk]
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk]
create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0]
set_clock_groups -asynchronous -group {tx_div_clk}
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_clock_groups -asynchronous -group {pl_ddr_clk}
set_clock_groups -asynchronous -group {pl_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]

172
projects/fmcomms2/c5soc/system_bd.qsys
View File

File diff suppressed because one or more lines are too long

3
projects/fmcomms2/c5soc/system_top.v
View File

@ -279,6 +279,7 @@ module system_top (
assign ad9361_resetb = 1'b1;
// instantiations
/*
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
@ -326,6 +327,8 @@ module system_top (
.acq_data_in (dev_dbg_data),
.acq_trigger_in (adc_valid));
*/
system_bd i_system_bd (
.clk_clk (sys_clk),
.reset_reset_n (sys_resetn),