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axi_ad9361: Fix altera lvds interface, reverting to an older working version

main
Adrian Costina 2017-07-28 10:09:17 +01:00
parent 31143cb893
commit 289b170dfd
4 changed files with 554 additions and 400 deletions
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202
library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_alt_lvds_rx (
// physical interface (receive)
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
// data interface
clk,
rx_frame,
rx_data_0,
rx_data_1,
rx_data_2,
rx_data_3,
rx_locked);
// physical interface (receive)
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
// data interface
output clk;
output [ 3:0] rx_frame;
output [ 5:0] rx_data_0;
output [ 5:0] rx_data_1;
output [ 5:0] rx_data_2;
output [ 5:0] rx_data_3;
output rx_locked;
// internal signals
wire [27:0] rx_data_s;
// instantiations
assign rx_frame[3] = rx_data_s[24];
assign rx_frame[2] = rx_data_s[25];
assign rx_frame[1] = rx_data_s[26];
assign rx_frame[0] = rx_data_s[27];
assign rx_data_3[5] = rx_data_s[20];
assign rx_data_3[4] = rx_data_s[16];
assign rx_data_3[3] = rx_data_s[12];
assign rx_data_3[2] = rx_data_s[ 8];
assign rx_data_3[1] = rx_data_s[ 4];
assign rx_data_3[0] = rx_data_s[ 0];
assign rx_data_2[5] = rx_data_s[21];
assign rx_data_2[4] = rx_data_s[17];
assign rx_data_2[3] = rx_data_s[13];
assign rx_data_2[2] = rx_data_s[ 9];
assign rx_data_2[1] = rx_data_s[ 5];
assign rx_data_2[0] = rx_data_s[ 1];
assign rx_data_1[5] = rx_data_s[22];
assign rx_data_1[4] = rx_data_s[18];
assign rx_data_1[3] = rx_data_s[14];
assign rx_data_1[2] = rx_data_s[10];
assign rx_data_1[1] = rx_data_s[ 6];
assign rx_data_1[0] = rx_data_s[ 2];
assign rx_data_0[5] = rx_data_s[23];
assign rx_data_0[4] = rx_data_s[19];
assign rx_data_0[3] = rx_data_s[15];
assign rx_data_0[2] = rx_data_s[11];
assign rx_data_0[1] = rx_data_s[ 7];
assign rx_data_0[0] = rx_data_s[ 3];
altlvds_rx #(
.buffer_implementation ("RAM"),
.cds_mode ("UNUSED"),
.common_rx_tx_pll ("ON"),
.data_align_rollover (4),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.dpa_initial_phase_value (0),
.dpll_lock_count (0),
.dpll_lock_window (0),
.enable_clock_pin_mode ("UNUSED"),
.enable_dpa_align_to_rising_edge_only ("OFF"),
.enable_dpa_calibration ("ON"),
.enable_dpa_fifo ("UNUSED"),
.enable_dpa_initial_phase_selection ("OFF"),
.enable_dpa_mode ("OFF"),
.enable_dpa_pll_calibration ("OFF"),
.enable_soft_cdr_mode ("OFF"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.input_data_rate (500),
.intended_device_family ("Cyclone V"),
.lose_lock_on_one_change ("UNUSED"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_rx"),
.lpm_type ("altlvds_rx"),
.number_of_channels (7),
.outclock_resource ("Regional clock"),
.pll_operation_mode ("NORMAL"),
.pll_self_reset_on_loss_lock ("UNUSED"),
.port_rx_channel_data_align ("PORT_UNUSED"),
.port_rx_data_align ("PORT_UNUSED"),
.refclk_frequency ("250.000000 MHz"),
.registered_data_align_input ("UNUSED"),
.registered_output ("ON"),
.reset_fifo_at_first_lock ("UNUSED"),
.rx_align_data_reg ("RISING_EDGE"),
.sim_dpa_is_negative_ppm_drift ("OFF"),
.sim_dpa_net_ppm_variation (0),
.sim_dpa_output_clock_phase_shift (0),
.use_coreclock_input ("OFF"),
.use_dpll_rawperror ("OFF"),
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.x_on_bitslip ("ON"),
.clk_src_is_pll ("off"))
i_altlvds_rx (
.rx_inclock (rx_clk_in_p),
.rx_in ({rx_frame_in_p, rx_data_in_p}),
.rx_outclock (clk),
.rx_out (rx_data_s),
.rx_locked (rx_locked),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_areset (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset ({7{1'b0}}),
.rx_channel_data_align ({7{1'b0}}),
.rx_coreclk ({7{1'b1}}),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_divfwdclk (),
.rx_dpa_lock_reset ({7{1'b0}}),
.rx_dpa_locked (),
.rx_dpaclock (1'b0),
.rx_dpll_enable ({7{1'b1}}),
.rx_dpll_hold ({7{1'b0}}),
.rx_dpll_reset ({7{1'b0}}),
.rx_enable (1'b1),
.rx_fifo_reset ({7{1'b0}}),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_reset ({7{1'b0}}),
.rx_syncclock (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_alt_lvds_tx (
// physical interface (transmit)
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
// data interface
tx_clk,
clk,
tx_frame,
tx_data_0,
tx_data_1,
tx_data_2,
tx_data_3,
tx_locked);
// physical interface (transmit)
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
// data interface
input tx_clk;
input clk;
input [ 3:0] tx_frame;
input [ 5:0] tx_data_0;
input [ 5:0] tx_data_1;
input [ 5:0] tx_data_2;
input [ 5:0] tx_data_3;
output tx_locked;
// internal registers
reg [27:0] tx_data_n = 'd0;
reg [27:0] tx_data_p = 'd0;
// internal signals
wire core_clk;
wire [27:0] tx_data_s;
// instantiations
assign tx_clk_out_n = 1'd0;
assign tx_frame_out_n = 1'd0;
assign tx_data_out_n = 6'd0;
assign tx_data_s[24] = tx_frame[3];
assign tx_data_s[25] = tx_frame[2];
assign tx_data_s[26] = tx_frame[1];
assign tx_data_s[27] = tx_frame[0];
assign tx_data_s[20] = tx_data_3[5];
assign tx_data_s[16] = tx_data_3[4];
assign tx_data_s[12] = tx_data_3[3];
assign tx_data_s[ 8] = tx_data_3[2];
assign tx_data_s[ 4] = tx_data_3[1];
assign tx_data_s[ 0] = tx_data_3[0];
assign tx_data_s[21] = tx_data_2[5];
assign tx_data_s[17] = tx_data_2[4];
assign tx_data_s[13] = tx_data_2[3];
assign tx_data_s[ 9] = tx_data_2[2];
assign tx_data_s[ 5] = tx_data_2[1];
assign tx_data_s[ 1] = tx_data_2[0];
assign tx_data_s[22] = tx_data_1[5];
assign tx_data_s[18] = tx_data_1[4];
assign tx_data_s[14] = tx_data_1[3];
assign tx_data_s[10] = tx_data_1[2];
assign tx_data_s[ 6] = tx_data_1[1];
assign tx_data_s[ 2] = tx_data_1[0];
assign tx_data_s[23] = tx_data_0[5];
assign tx_data_s[19] = tx_data_0[4];
assign tx_data_s[15] = tx_data_0[3];
assign tx_data_s[11] = tx_data_0[2];
assign tx_data_s[ 7] = tx_data_0[1];
assign tx_data_s[ 3] = tx_data_0[0];
always @(negedge clk) begin
tx_data_n <= tx_data_s;
end
always @(posedge core_clk) begin
tx_data_p <= tx_data_n;
end
altlvds_tx #(
.center_align_msb ("UNUSED"),
.common_rx_tx_pll ("ON"),
.coreclock_divide_by (1),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.differential_drive (0),
.enable_clock_pin_mode ("UNUSED"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.intended_device_family ("Cyclone V"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_tx"),
.lpm_type ("altlvds_tx"),
.multi_clock ("OFF"),
.number_of_channels (7),
.outclock_alignment ("EDGE_ALIGNED"),
.outclock_divide_by (2),
.outclock_duty_cycle (50),
.outclock_multiply_by (1),
.outclock_phase_shift (0),
.outclock_resource ("Regional clock"),
.output_data_rate (500),
.pll_compensation_mode ("AUTO"),
.pll_self_reset_on_loss_lock ("OFF"),
.preemphasis_setting (0),
.refclk_frequency ("250.000000 MHz"),
.registered_input ("TX_CORECLK"),
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.vod_setting (0),
.clk_src_is_pll ("off"))
i_altlvds_tx (
.tx_inclock (tx_clk),
.tx_coreclock (core_clk),
.tx_in (tx_data_p),
.tx_outclock (tx_clk_out_p),
.tx_out ({tx_frame_out_p, tx_data_out_p}),
.tx_locked (tx_locked),
.pll_areset (1'b0),
.sync_inclock (1'b0),
.tx_data_reset (1'b0),
.tx_enable (1'b1),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************

475
library/axi_ad9361/altera/axi_ad9361_lvds_if.v
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@ -120,393 +120,168 @@ module axi_ad9361_lvds_if #(
// internal registers
reg [ 3:0] rx_frame = 'd0;
reg rx_error = 'd0;
reg rx_valid = 'd0;
reg [ 5:0] rx_data_3 = 'd0;
reg [ 5:0] rx_data_2 = 'd0;
reg [ 5:0] rx_data_1 = 'd0;
reg [ 5:0] rx_data_0 = 'd0;
reg [23:0] rx_data = 'd0;
reg [ 3:0] tx_frame = 'd0;
reg [ 3:0] tx_p_frame = 'd0;
reg [ 3:0] tx_n_frame = 'd0;
reg [ 5:0] tx_data_d_0 = 'd0;
reg [ 5:0] tx_data_d_1 = 'd0;
reg [ 5:0] tx_data_d_2 = 'd0;
reg [ 5:0] tx_data_d_3 = 'd0;
reg tx_data_sel = 'd0;
reg up_enable_int = 'd0;
reg up_txnrx_int = 'd0;
reg enable_up_m1 = 'd0;
reg txnrx_up_m1 = 'd0;
reg enable_up = 'd0;
reg txnrx_up = 'd0;
reg enable_int = 'd0;
reg txnrx_int = 'd0;
reg enable_n_int = 'd0;
reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0;
reg [ 5:0] tx_p_data_d_0 = 'd0;
reg [ 5:0] tx_p_data_d_1 = 'd0;
reg [ 5:0] tx_p_data_d_2 = 'd0;
reg [ 5:0] tx_p_data_d_3 = 'd0;
reg [ 5:0] tx_n_data_d_0 = 'd0;
reg [ 5:0] tx_n_data_d_1 = 'd0;
reg [ 5:0] tx_n_data_d_2 = 'd0;
reg [ 5:0] tx_n_data_d_3 = 'd0;
reg adc_n_valid = 'd0;
reg adc_p_valid = 'd0;
reg adc_n_status = 'd0;
reg adc_p_status = 'd0;
reg [47:0] adc_n_data = 'd0;
reg [47:0] adc_p_data = 'd0;
reg [ 3:0] rx_frame = 'd0;
reg [ 5:0] rx_data_3 = 'd0;
reg [ 5:0] rx_data_2 = 'd0;
reg [ 5:0] rx_data_1 = 'd0;
reg [ 5:0] rx_data_0 = 'd0;
reg rx_error_r2 = 'd0;
reg rx_valid_r2 = 'd0;
reg [23:0] rx_data_r2 = 'd0;
reg tx_data_sel = 'd0;
reg [47:0] tx_data = 'd0;
reg [ 3:0] tx_frame = 'd0;
reg [ 5:0] tx_data_0 = 'd0;
reg [ 5:0] tx_data_1 = 'd0;
reg [ 5:0] tx_data_2 = 'd0;
reg [ 5:0] tx_data_3 = 'd0;
// internal signals
wire s_clk;
wire loaden;
wire [ 7:0] phase_s;
wire [ 3:0] rx_frame_s;
wire [ 5:0] rx_data_s_3;
wire [ 5:0] rx_data_s_2;
wire [ 5:0] rx_data_s_1;
wire [ 5:0] rx_data_s_0;
wire [ 3:0] rx_frame_inv_s;
wire [ 3:0] rx_frame_inv_s;
wire tx_locked_s;
wire [ 3:0] rx_frame_s;
wire [ 5:0] rx_data_0_s;
wire [ 5:0] rx_data_1_s;
wire [ 5:0] rx_data_2_s;
wire [ 5:0] rx_data_3_s;
wire rx_locked_s;
// unused interface signals
// tdd support-
assign up_adc_drdata = 35'b0;
assign up_dac_drdata = 50'b0;
assign delay_locked = 1'b1;
assign enable = up_enable;
assign txnrx = up_txnrx;
// defaults
assign delay_locked = 1'd1;
// receive data path interface
assign rx_frame_inv_s = ~rx_frame;
always @(posedge l_clk) begin
rx_frame <= rx_frame_s;
rx_data_3 <= rx_data_s_3;
rx_data_2 <= rx_data_s_2;
rx_data_1 <= rx_data_s_1;
rx_data_0 <= rx_data_s_0;
rx_data_3 <= rx_data_3_s;
rx_data_2 <= rx_data_2_s;
rx_data_1 <= rx_data_1_s;
rx_data_0 <= rx_data_0_s;
if (rx_frame_inv_s == rx_frame_s) begin
rx_error <= 1'b0;
rx_error_r2 <= 1'b0;
end else begin
rx_error <= 1'b1;
rx_error_r2 <= 1'b1;
end
case ({adc_r1_mode, rx_frame})
// R2 Mode
5'b01111: begin
rx_valid <= 1'b1;
rx_data[23:12] <= {rx_data_1, rx_data_3};
rx_data[11: 0] <= {rx_data_0, rx_data_2};
case (rx_frame)
4'b1111: begin
rx_valid_r2 <= 1'b1;
rx_data_r2[23:12] <= {rx_data_1, rx_data_3};
rx_data_r2[11: 0] <= {rx_data_0, rx_data_2};
end
5'b01110: begin
rx_valid <= 1'b1;
rx_data[23:12] <= {rx_data_2, rx_data_s_0};
rx_data[11: 0] <= {rx_data_1, rx_data_3};
4'b1110: begin
rx_valid_r2 <= 1'b1;
rx_data_r2[23:12] <= {rx_data_2, rx_data_0_s};
rx_data_r2[11: 0] <= {rx_data_1, rx_data_3};
end
5'b01100: begin
rx_valid <= 1'b1;
rx_data[23:12] <= {rx_data_3, rx_data_s_1};
rx_data[11: 0] <= {rx_data_2, rx_data_s_0};
4'b1100: begin
rx_valid_r2 <= 1'b1;
rx_data_r2[23:12] <= {rx_data_3, rx_data_1_s};
rx_data_r2[11: 0] <= {rx_data_2, rx_data_0_s};
end
5'b01000: begin
rx_valid <= 1'b1;
rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
rx_data[11: 0] <= {rx_data_3, rx_data_s_1};
4'b1000: begin
rx_valid_r2 <= 1'b1;
rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s};
rx_data_r2[11: 0] <= {rx_data_3, rx_data_1_s};
end
5'b00000: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_1, rx_data_3};
rx_data[11: 0] <= {rx_data_0, rx_data_2};
4'b0000: begin
rx_valid_r2 <= 1'b0;
rx_data_r2[23:12] <= {rx_data_1, rx_data_3};
rx_data_r2[11: 0] <= {rx_data_0, rx_data_2};
end
5'b00001: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_2, rx_data_s_0};
rx_data[11: 0] <= {rx_data_1, rx_data_3};
4'b0001: begin
rx_valid_r2 <= 1'b0;
rx_data_r2[23:12] <= {rx_data_2, rx_data_0_s};
rx_data_r2[11: 0] <= {rx_data_1, rx_data_3};
end
5'b00011: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_3, rx_data_s_1};
rx_data[11: 0] <= {rx_data_2, rx_data_s_0};
4'b0011: begin
rx_valid_r2 <= 1'b0;
rx_data_r2[23:12] <= {rx_data_3, rx_data_1_s};
rx_data_r2[11: 0] <= {rx_data_2, rx_data_0_s};
end
5'b00111: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
rx_data[11: 0] <= {rx_data_3, rx_data_s_1};
end
// R1 Mode
5'b11100: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_s_1, rx_data_s_3};
rx_data[11: 0] <= {rx_data_s_0, rx_data_s_2};
end
5'b10110: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_2, rx_data_s_0};
rx_data[11: 0] <= {rx_data_1, rx_data_3};
end
5'b11001: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_s_0, rx_data_s_2};
rx_data[11: 0] <= {rx_data_3, rx_data_s_1};
end
5'b10011: begin
rx_valid <= 1'b0;
rx_data[23:12] <= {rx_data_3, rx_data_s_1};
rx_data[11: 0] <= {rx_data_2, rx_data_s_0};
4'b0111: begin
rx_valid_r2 <= 1'b0;
rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s};
rx_data_r2[11: 0] <= {rx_data_3, rx_data_1_s};
end
default: begin
rx_valid <= 1'b0;
rx_data[23:12] <= 12'd0;
rx_data[11: 0] <= 12'd0;
rx_valid_r2 <= 1'b0;
rx_data_r2[23:12] <= 12'd0;
rx_data_r2[11: 0] <= 12'd0;
end
endcase
if (rx_valid == 1'b1) begin
adc_p_valid <= 1'b0;
adc_p_data <= {24'd0, rx_data};
if (rx_valid_r2 == 1'b1) begin
adc_valid <= 1'b0;
adc_data <= {24'd0, rx_data_r2};
end else begin
adc_p_valid <= 1'b1;
adc_p_data <= (adc_r1_mode) ? {24'd0, rx_data} : {rx_data, adc_p_data[23:0]};
adc_valid <= 1'b1;
adc_data <= {rx_data_r2, adc_data[23:0]};
end
adc_p_status <= ~rx_error & up_drp_locked;
adc_status <= ~rx_error_r2 & rx_locked_s & tx_locked_s;
end
// transfer to a synchronous common clock
always @(negedge l_clk) begin
adc_n_valid <= adc_p_valid;
adc_n_data <= adc_p_data;
adc_n_status <= adc_p_status;
end
always @(posedge clk) begin
adc_valid <= adc_n_valid;
adc_data <= adc_n_data;
adc_status <= adc_n_status;
end
always @(posedge clk) begin
if (dac_r1_mode == 1'b0) begin
tx_data_sel <= ~tx_data_sel;
end else begin
tx_data_sel <= 1'b0;
end
case ({dac_r1_mode, tx_data_sel})
2'b10: begin
tx_frame <= 4'b1100;
tx_data_d_0 <= dac_data[11: 6]; // i msb
tx_data_d_1 <= dac_data[23:18]; // q msb
tx_data_d_2 <= dac_data[ 5: 0]; // i lsb
tx_data_d_3 <= dac_data[17:12]; // q lsb
end
2'b00: begin
tx_frame <= 4'b1111;
tx_data_d_0 <= dac_data[11: 6]; // i msb 0
tx_data_d_1 <= dac_data[23:18]; // q msb 0
tx_data_d_2 <= dac_data[ 5: 0]; // i lsb 0
tx_data_d_3 <= dac_data[17:12]; // q lsb 0
end
2'b01: begin
tx_frame <= 4'b0000;
tx_data_d_0 <= dac_data[35:30]; // i msb 1
tx_data_d_1 <= dac_data[47:42]; // q msb 1
tx_data_d_2 <= dac_data[29:24]; // i lsb 1
tx_data_d_3 <= dac_data[41:36]; // q lsb 1
end
endcase
end
// transfer data from a synchronous clock (skew less than 2ns)
always @(negedge clk) begin
tx_n_frame <= tx_frame;
tx_n_data_d_0 <= tx_data_d_0;
tx_n_data_d_1 <= tx_data_d_1;
tx_n_data_d_2 <= tx_data_d_2;
tx_n_data_d_3 <= tx_data_d_3;
end
// transmit data path mux
always @(posedge l_clk) begin
tx_p_frame <= tx_n_frame;
tx_p_data_d_0 <= tx_n_data_d_0;
tx_p_data_d_1 <= tx_n_data_d_1;
tx_p_data_d_2 <= tx_n_data_d_2;
tx_p_data_d_3 <= tx_n_data_d_3;
end
// tdd/ensm control
always @(posedge up_clk) begin
up_enable_int <= up_enable;
up_txnrx_int <= up_txnrx;
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
enable_up_m1 <= 1'b0;
txnrx_up_m1 <= 1'b0;
enable_up <= 1'b0;
txnrx_up <= 1'b0;
tx_data_sel <= dac_valid;
tx_data <= dac_data;
if (tx_data_sel == 1'b1) begin
tx_frame <= 4'b1111;
tx_data_0 <= tx_data[11: 6];
tx_data_1 <= tx_data[23:18];
tx_data_2 <= tx_data[ 5: 0];
tx_data_3 <= tx_data[17:12];
end else begin
enable_up_m1 <= up_enable_int;
txnrx_up_m1 <= up_txnrx_int;
enable_up <= enable_up_m1;
txnrx_up <= txnrx_up_m1;
tx_frame <= 4'b0000;
tx_data_0 <= tx_data[35:30];
tx_data_1 <= tx_data[47:42];
tx_data_2 <= tx_data[29:24];
tx_data_3 <= tx_data[41:36];
end
end
always @(posedge clk) begin
if (tdd_mode == 1'b1) begin
enable_int <= tdd_enable;
txnrx_int <= tdd_txnrx;
end else begin
enable_int <= enable_up;
txnrx_int <= txnrx_up;
end
end
// interface (transmit)
always @(negedge clk) begin
enable_n_int <= enable_int;
txnrx_n_int <= txnrx_int;
end
axi_ad9361_alt_lvds_tx i_tx (
.tx_clk_out_p (tx_clk_out_p),
.tx_clk_out_n (tx_clk_out_n),
.tx_frame_out_p (tx_frame_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_data_out_n (tx_data_out_n),
.tx_clk (rx_clk_in_p),
.clk (l_clk),
.tx_frame (tx_frame),
.tx_data_0 (tx_data_0),
.tx_data_1 (tx_data_1),
.tx_data_2 (tx_data_2),
.tx_data_3 (tx_data_3),
.tx_locked (tx_locked_s));
always @(posedge l_clk) begin
enable_p_int <= enable_n_int;
txnrx_p_int <= txnrx_n_int;
end
// interface (receive)
// receive data path interface
axi_ad9361_serdes_in #(
.DEVICE_TYPE (DEVICE_TYPE),
.DATA_WIDTH (6))
ad_serdes_data_in (
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.phase (phase_s),
.locked (up_drp_locked),
.data_s0 (rx_data_s_0),
.data_s1 (rx_data_s_1),
.data_s2 (rx_data_s_2),
.data_s3 (rx_data_s_3),
.data_in_p (rx_data_in_p),
.data_in_n (rx_data_in_n),
.delay_locked ());
// receive frame interface
axi_ad9361_serdes_in #(
.DEVICE_TYPE (DEVICE_TYPE),
.DATA_WIDTH (1))
ad_serdes_frame_in (
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.phase (phase_s),
.locked (up_drp_locked),
.data_s0 (rx_frame_s[0]),
.data_s1 (rx_frame_s[1]),
.data_s2 (rx_frame_s[2]),
.data_s3 (rx_frame_s[3]),
.data_in_p (rx_frame_in_p),
.data_in_n (rx_frame_in_n),
.delay_locked ());
// transmit data interface
axi_ad9361_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.DATA_WIDTH (6))
ad_serdes_data_out (
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (tx_p_data_d_0),
.data_s1 (tx_p_data_d_1),
.data_s2 (tx_p_data_d_2),
.data_s3 (tx_p_data_d_3),
.data_out_p (tx_data_out_p),
.data_out_n (tx_data_out_n));
// transmit frame interface
axi_ad9361_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.DATA_WIDTH (1))
ad_serdes_frame_out (
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (tx_p_frame[0]),
.data_s1 (tx_p_frame[1]),
.data_s2 (tx_p_frame[2]),
.data_s3 (tx_p_frame[3]),
.data_out_p (tx_frame_out_p),
.data_out_n (tx_frame_out_n));
// transmit clock interface
axi_ad9361_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.DATA_WIDTH (1))
ad_serdes_tx_clock_out(
.clk (s_clk),
.div_clk (l_clk),
.loaden (loaden),
.data_s0 (dac_clksel),
.data_s1 (~dac_clksel),
.data_s2 (dac_clksel),
.data_s3 (~dac_clksel),
.data_out_p (tx_clk_out_p),
.data_out_n (tx_clk_out_n));
// serdes clock interface
axi_ad9361_serdes_clk #(
.DEVICE_TYPE (DEVICE_TYPE))
ad_serdes_clk (
.rst (mmcm_rst),
.clk_in_p (rx_clk_in_p),
.clk_in_n (rx_clk_in_n),
.clk (s_clk),
.div_clk (l_clk),
.out_clk (),
.loaden (loaden),
.phase (phase_s),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
// enable
axi_ad9361_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE))
ad_serdes_enable (
.tx_clk (l_clk),
.tx_data_p (enable_p_int),
.tx_data_n (enable_p_int),
.tx_data_out (enable));
// txnrx
axi_ad9361_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE))
ad_serdes_txnrx (
.tx_clk (l_clk),
.tx_data_p (txnrx_p_int),
.tx_data_n (txnrx_p_int),
.tx_data_out (txnrx));
axi_ad9361_alt_lvds_rx i_rx (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
.rx_frame_in_p (rx_frame_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_data_in_n (rx_data_in_n),
.clk (l_clk),
.rx_frame (rx_frame_s),
.rx_data_0 (rx_data_0_s),
.rx_data_1 (rx_data_1_s),
.rx_data_2 (rx_data_2_s),
.rx_data_3 (rx_data_3_s),
.rx_locked (rx_locked_s));
endmodule

91
library/axi_ad9361/axi_ad9361_hw.tcl
View File

@ -1,10 +1,13 @@
package require qsys
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab
ad_ip_files axi_ad9361 [list\
$ad_hdl_dir/library/altera/common/ad_lvds_clk.v \
$ad_hdl_dir/library/altera/common/ad_lvds_in.v \
$ad_hdl_dir/library/altera/common/ad_lvds_out.v \
$ad_hdl_dir/library/altera/common/ad_mul.v \
$ad_hdl_dir/library/altera/common/ad_dcfilter.v \
$ad_hdl_dir/library/common/ad_rst.v \
@ -26,12 +29,9 @@ ad_ip_files axi_ad9361 [list\
$ad_hdl_dir/library/common/up_dac_common.v \
$ad_hdl_dir/library/common/up_dac_channel.v \
$ad_hdl_dir/library/common/up_tdd_cntrl.v \
altera/axi_ad9361_serdes_clk.v \
altera/axi_ad9361_serdes_out.v \
altera/axi_ad9361_serdes_in.v \
altera/axi_ad9361_cmos_out.v \
altera/axi_ad9361_alt_lvds_tx.v \
altera/axi_ad9361_alt_lvds_rx.v \
altera/axi_ad9361_lvds_if.v \
altera/axi_ad9361_cmos_if.v \
axi_ad9361_rx_pnmon.v \
axi_ad9361_rx_channel.v \
axi_ad9361_rx.v \
@ -44,7 +44,7 @@ ad_ip_files axi_ad9361 [list\
$ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc \
$ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc \
$ad_hdl_dir/library/altera/common/up_rst_constr.sdc \
axi_ad9361_constr.sdc] \
axi_ad9361_constr.sdc]
# parameters
@ -69,7 +69,7 @@ ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group}
# interfaces
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
ad_alt_intf signal dac_sync_in input 1
ad_alt_intf signal dac_sync_out output 1
ad_alt_intf signal tdd_sync input 1
@ -161,54 +161,38 @@ ad_alt_intf signal up_dac_gpio_out output 32
ad_alt_intf signal up_adc_gpio_in input 32
ad_alt_intf signal up_adc_gpio_out output 32
# generated cores
add_hdl_instance ad_serdes_clk_core alt_serdes
set_instance_parameter_value ad_serdes_clk_core {MODE} {CLK}
set_instance_parameter_value ad_serdes_clk_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_clk_core {SERDES_FACTOR} {4}
set_instance_parameter_value ad_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance ad_serdes_in_core_a10 alt_serdes
set_instance_parameter_value ad_serdes_in_core_a10 {MODE} {IN}
set_instance_parameter_value ad_serdes_in_core_a10 {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_in_core_a10 {SERDES_FACTOR} {4}
set_instance_parameter_value ad_serdes_in_core_a10 {CLKIN_FREQUENCY} {250.0}
add_hdl_instance ad_serdes_out_core_a10 alt_serdes
set_instance_parameter_value ad_serdes_out_core_a10 {MODE} {OUT}
set_instance_parameter_value ad_serdes_out_core_a10 {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_out_core_a10 {SERDES_FACTOR} {4}
set_instance_parameter_value ad_serdes_out_core_a10 {CLKIN_FREQUENCY} {250.0}
add_hdl_instance ad_cmos_out_core_a10 alt_serdes
set_instance_parameter_value ad_cmos_out_core_a10 {MODE} {OUT}
set_instance_parameter_value ad_cmos_out_core_a10 {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_cmos_out_core_a10 {SERDES_FACTOR} {2}
set_instance_parameter_value ad_cmos_out_core_a10 {CLKIN_FREQUENCY} {250.0}
# updates
proc axi_ad9361_elab {} {
set m_device_family [get_parameter_value "DEVICE_FAMILY"]
set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N]
if {$m_device_family eq "Cyclone V"} {
add_hdl_instance axi_ad9361_serdes_clk_pll alt_serdes
set_instance_parameter_value axi_ad9361_serdes_clk_pll {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_clk_pll {MODE} {CLK}
set_instance_parameter_value axi_ad9361_serdes_clk_pll {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_clk_pll {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_clk_pll {CLKIN_FREQUENCY} {250.0}
}
if {$m_device_family eq "Arria 10"} {
add_hdl_instance axi_ad9361_serdes_clk_core alt_serdes
set_instance_parameter_value axi_ad9361_serdes_clk_core {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_clk_core {MODE} {CLK}
set_instance_parameter_value axi_ad9361_serdes_clk_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_clk_core {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_serdes_in_core alt_serdes
set_instance_parameter_value axi_ad9361_serdes_in_core {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_in_core {MODE} {IN}
set_instance_parameter_value axi_ad9361_serdes_in_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_in_core {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_in_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_serdes_out_core alt_serdes
set_instance_parameter_value axi_ad9361_serdes_out_core {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_serdes_out_core {MODE} {OUT}
set_instance_parameter_value axi_ad9361_serdes_out_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_serdes_out_core {SERDES_FACTOR} {4}
set_instance_parameter_value axi_ad9361_serdes_out_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance axi_ad9361_cmos_out_core alt_serdes
set_instance_parameter_value axi_ad9361_cmos_out_core {DEVICE_FAMILY} $m_device_family
set_instance_parameter_value axi_ad9361_cmos_out_core {MODE} {OUT}
set_instance_parameter_value axi_ad9361_cmos_out_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value axi_ad9361_cmos_out_core {SERDES_FACTOR} {2}
set_instance_parameter_value axi_ad9361_cmos_out_core {CLKIN_FREQUENCY} {250.0}
}
add_interface device_if conduit end
set_interface_property device_if associatedClock none
set_interface_property device_if associatedReset none
@ -243,3 +227,10 @@ proc axi_ad9361_elab {} {
add_interface_port device_if txnrx txnrx Output 1
}
proc axi_ad9361_fileset {entityName} {
ad_ip_modfile ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core_a10
ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core_a10
ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core_a10
ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
}