From 2816812e0afdd618b9fb967a2e807976a0c75d1f Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 25 Sep 2015 17:16:31 +0300 Subject: [PATCH] axi_ad9625: Updated constraints and added adc reset port --- library/axi_ad9625/Makefile | 1 + library/axi_ad9625/axi_ad9625.v | 2 ++ library/axi_ad9625/axi_ad9625_constr.xdc | 43 ------------------------ library/axi_ad9625/axi_ad9625_ip.tcl | 2 ++ 4 files changed, 5 insertions(+), 43 deletions(-) diff --git a/library/axi_ad9625/Makefile b/library/axi_ad9625/Makefile index f5e5e78ba..23f0a474b 100644 --- a/library/axi_ad9625/Makefile +++ b/library/axi_ad9625/Makefile @@ -18,6 +18,7 @@ M_DEPS += ../common/up_xfer_status.v M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += axi_ad9625_pnmon.v M_DEPS += axi_ad9625_channel.v M_DEPS += axi_ad9625_if.v diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v index 4c6689c02..9f7be37ba 100644 --- a/library/axi_ad9625/axi_ad9625.v +++ b/library/axi_ad9625/axi_ad9625.v @@ -50,6 +50,7 @@ module axi_ad9625 ( // dma interface adc_clk, + adc_rst, adc_valid, adc_enable, adc_data, @@ -94,6 +95,7 @@ module axi_ad9625 ( // dma interface output adc_clk; + output adc_rst; output adc_valid; output adc_enable; output [255:0] adc_data; diff --git a/library/axi_ad9625/axi_ad9625_constr.xdc b/library/axi_ad9625/axi_ad9625_constr.xdc index e482815b1..8b1378917 100644 --- a/library/axi_ad9625/axi_ad9625_constr.xdc +++ b/library/axi_ad9625/axi_ad9625_constr.xdc @@ -1,44 +1 @@ -set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]] -set ad9625_clk [get_clocks -of_objects [get_ports rx_clk]] -set_property ASYNC_REG TRUE \ - [get_cells -hier *toggle_m1_reg*] \ - [get_cells -hier *toggle_m2_reg*] \ - [get_cells -hier *state_m1_reg*] \ - [get_cells -hier *state_m2_reg*] - -set_false_path \ - -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $ad9625_clk] - -set_false_path \ - -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $up_clk] - -set_false_path \ - -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $up_clk] - -set_false_path \ - -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}] diff --git a/library/axi_ad9625/axi_ad9625_ip.tcl b/library/axi_ad9625/axi_ad9625_ip.tcl index 05f4749ae..c046b62ba 100644 --- a/library/axi_ad9625/axi_ad9625_ip.tcl +++ b/library/axi_ad9625/axi_ad9625_ip.tcl @@ -15,6 +15,7 @@ adi_ip_files axi_ad9625 [list \ "$ad_hdl_dir/library/common/up_clock_mon.v" \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad9625_pnmon.v" \ "axi_ad9625_channel.v" \ "axi_ad9625_if.v" \ @@ -24,6 +25,7 @@ adi_ip_files axi_ad9625 [list \ adi_ip_properties axi_ad9625 adi_ip_constraints axi_ad9625 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad9625_constr.xdc" ] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]