common: Initial check in of ad_serdes_in.v
A generic serdes module for input interface, support both 6 and 7 series.main
Istvan Csomortani
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683561b67d
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module ad_serdes_in (
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// reset and clocks
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rst,
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clk,
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div_clk,
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// data interface
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data_s0,
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data_s1,
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data_s2,
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data_s3,
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data_s4,
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data_s5,
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data_s6,
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data_s7,
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data_in_p,
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data_in_n);
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// parameters
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parameter DEVICE_TYPE = 0;
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parameter SERDES = 1;
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parameter DATA_WIDTH = 16;
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parameter PARALLEL_DATA_WIDTH = 8;
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localparam DEVICE_6SERIES = 1;
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localparam DEVICE_7SERIES = 0;
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localparam DW = DATA_WIDTH - 1;
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// reset and clocks
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input rst;
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input clk;
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input div_clk;
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// data interface
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output [DW:0] data_s0;
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output [DW:0] data_s1;
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output [DW:0] data_s2;
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output [DW:0] data_s3;
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output [DW:0] data_s4;
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output [DW:0] data_s5;
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output [DW:0] data_s6;
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output [DW:0] data_s7;
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input [DW:0] data_in_p;
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input [DW:0] data_in_n;
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// internal signals
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wire [DW:0] data_in_s;
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wire [DW:0] data_shift1_s;
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wire [DW:0] data_shift2_s;
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// instantiations
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genvar l_inst;
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generate
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for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin
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if (SERDES == 0) begin
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IDDR #(
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.DDR_CLK_EDGE("SAME_EDGE"),
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.SRTYPE("ASYNC"))
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i_iddr (
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.Q1(data_s0[l_inst]),
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.Q2(data_s1[l_inst]),
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.C(clk),
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.CE(1'b1),
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.D(data_in_s[l_inst]),
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.R(rst),
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.S(1'b0)
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);
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end
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if ((SERDES == 1) && (DEVICE_TYPE == DEVICE_7SERIES)) begin
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ISERDESE2 #(
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.DATA_RATE("SDR"),
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.DATA_WIDTH(PARALLEL_DATA_WIDTH),
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.DYN_CLKDIV_INV_EN("FALSE"),
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.DYN_CLK_INV_EN("FALSE"),
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("NETWORKING"),
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.IOBDELAY("NONE"),
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.NUM_CE(1),
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.OFB_USED("FALSE"),
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.SERDES_MODE("MASTER"),
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0)
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)
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ISERDESE2_inst (
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.O(),
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.Q1(data_s0[l_inst]),
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.Q2(data_s1[l_inst]),
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.Q3(data_s2[l_inst]),
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.Q4(data_s3[l_inst]),
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.Q5(data_s4[l_inst]),
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.Q6(data_s5[l_inst]),
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.Q7(data_s6[l_inst]),
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.Q8(data_s7[l_inst]),
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.BITSLIP(1'b0),
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.CE1(1'b1),
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.CE2(1'b0),
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.CLKDIVP(1'b0),
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.CLK(clk),
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.CLKB(1'b0),
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.CLKDIV(div_clk),
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.OCLK(1'b0),
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.DYNCLKDIVSEL(1'b0),
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.DYNCLKSEL(1'b0),
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.D(data_in_s[l_inst]),
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.DDLY(1'b0),
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.OFB(1'b0),
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.OCLKB(1'b0),
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.RST(rst),
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0)
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);
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end
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if ((SERDES == 1) && (DEVICE_TYPE == DEVICE_6SERIES)) begin
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if (PARALLEL_DATA_WIDTH <= 6) begin
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ISERDESE1 #(
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.DATA_RATE("SDR"),
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.DATA_WIDTH(PARALLEL_DATA_WIDTH),
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.DYN_CLKDIV_INV_EN("FALSE"),
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.DYN_CLK_INV_EN("FALSE"),
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("NETWORKING"),
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.IOBDELAY("NONE"),
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.NUM_CE(1),
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.OFB_USED("FALSE"),
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.SERDES_MODE("MASTER"),
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0))
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i_serdes (
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.O(),
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.Q1(data_s0[l_inst]),
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.Q2(data_s1[l_inst]),
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.Q3(data_s2[l_inst]),
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.Q4(data_s3[l_inst]),
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.Q5(data_s4[l_inst]),
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.Q6(data_s5[l_inst]),
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.SHIFTOUT1(data_shift1_s[l_inst]),
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.SHIFTOUT2(data_shift2_s[l_inst]),
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.BITSLIP(1'b0),
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.CE1(1'b1),
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.CE2(1'b1),
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.CLK(clk),
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.CLKB(1'b0),
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.CLKDIV(div_clk),
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.OCLK(1'b0),
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.DYNCLKDIVSEL(1'b0),
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.DYNCLKSEL(1'b0),
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.D(data_in_s[l_inst]),
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.DDLY(1'b0),
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.OFB(1'b0),
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.RST(rst),
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0)
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);
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end else begin
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ISERDESE1 #(
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.DATA_RATE("SDR"),
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.DATA_WIDTH(PARALLEL_DATA_WIDTH),
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.DYN_CLKDIV_INV_EN("FALSE"),
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.DYN_CLK_INV_EN("FALSE"),
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("NETWORKING"),
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.IOBDELAY("NONE"),
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.NUM_CE(1),
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.OFB_USED("FALSE"),
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.SERDES_MODE("MASTER"),
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0))
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i_serdes_m (
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.O(),
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.Q1(data_s0[l_inst]),
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.Q2(data_s1[l_inst]),
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.Q3(data_s2[l_inst]),
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.Q4(data_s3[l_inst]),
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.Q5(data_s4[l_inst]),
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.Q6(data_s5[l_inst]),
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.SHIFTOUT1(data_shift1_s[l_inst]),
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.SHIFTOUT2(data_shift2_s[l_inst]),
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.BITSLIP(1'b0),
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.CE1(1'b1),
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.CE2(1'b1),
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.CLK(clk),
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.CLKB(1'b0),
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.CLKDIV(div_clk),
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.OCLK(1'b0),
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.DYNCLKDIVSEL(1'b0),
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.DYNCLKSEL(1'b0),
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.D(data_in_s[l_inst]),
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.DDLY(1'b0),
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.OFB(1'b0),
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.RST(rst),
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0)
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);
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ISERDESE1 #(
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.DATA_RATE("SDR"),
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.DATA_WIDTH(PARALLEL_DATA_WIDTH),
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.DYN_CLKDIV_INV_EN("FALSE"),
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.DYN_CLK_INV_EN("FALSE"),
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("NETWORKING"),
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.IOBDELAY("NONE"),
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.NUM_CE(1),
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.OFB_USED("FALSE"),
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.SERDES_MODE("SLAVE"),
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0))
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i_serdes_s (
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.O(),
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.Q1(),
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.Q2(),
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.Q3(data_s6),
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.Q4(data_s7),
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.Q5(),
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.Q6(),
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.BITSLIP(1'b0),
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.CE1(1'b1),
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.CE2(1'b1),
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.CLK(clk),
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.CLKB(1'b0),
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.CLKDIV(div_clk),
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.OCLK(1'b0),
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.DYNCLKDIVSEL(1'b0),
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.DYNCLKSEL(1'b0),
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.D(1'b0),
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.DDLY(1'b0),
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.OFB(1'b0),
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.RST(rst),
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.SHIFTIN1(data_shift1_s[l_inst]),
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.SHIFTIN2(data_shift2_s[l_inst]));
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end
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end
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IBUFDS i_ibuf (
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.O(data_in_s[l_inst]),
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.I(data_in_p[l_inst]),
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.IB(data_in_n[l_inst])
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);
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end
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endgenerate
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endmodule
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