ad9467_kc705: Update project to the new frame work.

main
Istvan Csomortani 2015-04-01 17:16:47 +03:00
parent ae26c7817e
commit 271a383012
2 changed files with 225 additions and 232 deletions

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@ -1,12 +1,14 @@
# load script # load script
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set project_name ad9467_fmc_kc705 set project_name ad9467_fmc_kc705
adi_project_create $project_name adi_project_create $project_name
adi_project_files $project_name [list "../common/ad9467_spi.v" \ adi_project_files $project_name [list "../common/ad9467_spi.v" \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"system_top.v" \ "system_top.v" \
"system_constr.xdc" \ "system_constr.xdc" \
"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc"] "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc"]

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@ -40,265 +40,256 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module system_top ( module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin, sys_rst,
uart_sout, sys_clk_p,
sys_clk_n,
ddr3_1_n, uart_sin,
ddr3_1_p, uart_sout,
ddr3_reset_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ras_n,
ddr3_we_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
mdio_mdc, ddr3_1_n,
mdio_mdio_io, ddr3_1_p,
mii_rst_n, ddr3_reset_n,
mii_col, ddr3_addr,
mii_crs, ddr3_ba,
mii_rx_clk, ddr3_cas_n,
mii_rx_er, ddr3_ras_n,
mii_rx_dv, ddr3_we_n,
mii_rxd, ddr3_ck_n,
mii_tx_clk, ddr3_ck_p,
mii_tx_en, ddr3_cke,
mii_txd, ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
linear_flash_addr, mdio_mdc,
linear_flash_adv_ldn, mdio_mdio_io,
linear_flash_ce_n, mii_rst_n,
linear_flash_dq_io, mii_col,
linear_flash_oen, mii_crs,
linear_flash_wen, mii_rx_clk,
mii_rx_er,
mii_rx_dv,
mii_rxd,
mii_tx_clk,
mii_tx_en,
mii_txd,
fan_pwm, linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_dq_io,
linear_flash_oen,
linear_flash_wen,
gpio_lcd, fan_pwm,
gpio_led,
gpio_sw,
iic_rstn, gpio_lcd,
iic_scl, gpio_bd,
iic_sda,
hdmi_out_clk, iic_rstn,
hdmi_hsync, iic_scl,
hdmi_vsync, iic_sda,
hdmi_data_e,
hdmi_data,
spdif, hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
adc_clk_in_n, spdif,
adc_clk_in_p,
adc_data_in_n, adc_clk_in_n,
adc_data_in_p, adc_clk_in_p,
adc_data_or_n, adc_data_in_n,
adc_data_or_p, adc_data_in_p,
spi_clk, adc_data_or_n,
spi_csn_adc, adc_data_or_p,
spi_csn_clk, spi_clk,
spi_sdio spi_csn_adc,
spi_csn_clk,
spi_sdio
); );
input sys_rst; input sys_rst;
input sys_clk_p; input sys_clk_p;
input sys_clk_n; input sys_clk_n;
input uart_sin; input uart_sin;
output uart_sout; output uart_sout;
output [ 2:0] ddr3_1_n; output [ 2:0] ddr3_1_n;
output [ 1:0] ddr3_1_p; output [ 1:0] ddr3_1_p;
output ddr3_reset_n; output ddr3_reset_n;
output [13:0] ddr3_addr; output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba; output [ 2:0] ddr3_ba;
output ddr3_cas_n; output ddr3_cas_n;
output ddr3_ras_n; output ddr3_ras_n;
output ddr3_we_n; output ddr3_we_n;
output [ 0:0] ddr3_ck_n; output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p; output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke; output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n; output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm; output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq; inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n; inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p; inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt; output [ 0:0] ddr3_odt;
output mdio_mdc; output mdio_mdc;
inout mdio_mdio_io; inout mdio_mdio_io;
output mii_rst_n; output mii_rst_n;
input mii_col; input mii_col;
input mii_crs; input mii_crs;
input mii_rx_clk; input mii_rx_clk;
input mii_rx_er; input mii_rx_er;
input mii_rx_dv; input mii_rx_dv;
input [ 3:0] mii_rxd; input [ 3:0] mii_rxd;
input mii_tx_clk; input mii_tx_clk;
output mii_tx_en; output mii_tx_en;
output [ 3:0] mii_txd; output [ 3:0] mii_txd;
output [26:1] linear_flash_addr; output [26:1] linear_flash_addr;
output linear_flash_adv_ldn; output linear_flash_adv_ldn;
output linear_flash_ce_n; output linear_flash_ce_n;
inout [15:0] linear_flash_dq_io; inout [15:0] linear_flash_dq_io;
output linear_flash_oen; output linear_flash_oen;
output linear_flash_wen; output linear_flash_wen;
output fan_pwm; output fan_pwm;
inout [ 6:0] gpio_lcd; inout [ 6:0] gpio_lcd;
inout [ 7:0] gpio_led; inout [16:0] gpio_bd;
inout [ 8:0] gpio_sw;
output iic_rstn; output iic_rstn;
inout iic_scl; inout iic_scl;
inout iic_sda; inout iic_sda;
output hdmi_out_clk; output hdmi_out_clk;
output hdmi_hsync; output hdmi_hsync;
output hdmi_vsync; output hdmi_vsync;
output hdmi_data_e; output hdmi_data_e;
output [15:0] hdmi_data; output [15:0] hdmi_data;
output spdif; output spdif;
input adc_clk_in_n; input adc_clk_in_n;
input adc_clk_in_p; input adc_clk_in_p;
input [ 7:0] adc_data_in_n; input [ 7:0] adc_data_in_n;
input [ 7:0] adc_data_in_p; input [ 7:0] adc_data_in_p;
input adc_data_or_n; input adc_data_or_n;
input adc_data_or_p; input adc_data_or_p;
output spi_clk; output spi_clk;
output spi_csn_adc; output spi_csn_adc;
output spi_csn_clk; output spi_csn_clk;
inout spi_sdio; inout spi_sdio;
// internal signals // internal signals
wire [ 1:0] spi_csn; wire [ 1:0] spi_csn;
wire spi_miso; wire spi_miso;
wire spi_mosi; wire spi_mosi;
wire [31:0] mb_intrs;
assign spi_csn_adc = spi_csn[0]; wire [63:0] gpio_i;
assign spi_csn_clk = spi_csn[1]; wire [63:0] gpio_o;
wire [63:0] gpio_t;
ad9467_spi i_spi ( assign ddr3_1_p = 2'b11;
.spi_csn(spi_csn), assign ddr3_1_n = 3'b000;
.spi_clk(spi_clk), assign fan_pwm = 1'b1;
.spi_mosi(spi_mosi), assign iic_rstn = 1'b1;
.spi_miso(spi_miso),
.spi_sdio(spi_sdio)
);
system_wrapper i_system_wrapper ( assign spi_csn_adc = spi_csn[0];
.ddr3_1_n (ddr3_1_n), assign spi_csn_clk = spi_csn[1];
.ddr3_1_p (ddr3_1_p),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.fan_pwm (fan_pwm),
.gpio_lcd_tri_io (gpio_lcd),
.gpio_led_tri_io (gpio_led),
.gpio_sw_tri_io (gpio_sw),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.iic_rstn (iic_rstn),
.mb_intr_10 (mb_intrs[10]),
.mb_intr_11 (mb_intrs[11]),
.mb_intr_12 (mb_intrs[12]),
.mb_intr_13 (mb_intrs[13]),
.mb_intr_14 (mb_intrs[14]),
.mb_intr_15 (mb_intrs[15]),
.mb_intr_16 (mb_intrs[16]),
.mb_intr_17 (mb_intrs[17]),
.mb_intr_18 (mb_intrs[18]),
.mb_intr_19 (mb_intrs[19]),
.mb_intr_20 (mb_intrs[20]),
.mb_intr_21 (mb_intrs[21]),
.mb_intr_22 (mb_intrs[22]),
.mb_intr_23 (mb_intrs[23]),
.mb_intr_24 (mb_intrs[24]),
.mb_intr_25 (mb_intrs[25]),
.mb_intr_26 (mb_intrs[26]),
.mb_intr_27 (mb_intrs[27]),
.mb_intr_28 (mb_intrs[28]),
.mb_intr_29 (mb_intrs[29]),
.mb_intr_30 (mb_intrs[30]),
.mb_intr_31 (mb_intrs[31]),
.ad9467_dma_irq (mb_intrs[10]),
.ad9467_spi_irq (mb_intrs[13]),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio_io),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rst_n (mii_rst_n),
.mii_rx_clk (mii_rx_clk),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rxd (mii_rxd),
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io (linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.adc_clk_in_n(adc_clk_in_n),
.adc_clk_in_p(adc_clk_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_or_n(adc_data_or_n),
.adc_data_or_p(adc_data_or_p),
.spi_clk_i(1'b0),
.spi_clk_o(spi_clk),
.spi_csn_i(1'b1),
.spi_csn_o(spi_csn),
.spi_sdi_i(spi_miso),
.spi_sdo_i(1'b0),
.spi_sdo_o(spi_mosi));
endmodule ad9467_spi i_spi (
.spi_csn(spi_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio)
);
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_sw_led (
.dt (gpio_t[16:0]),
.di (gpio_o[16:0]),
.do (gpio_i[16:0]),
.dio(gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio_lcd_tri_io (gpio_lcd),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mb_intr_02 (1'b0),
.mb_intr_03 (1'b0),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),
.mb_intr_08 (1'b0),
.mb_intr_13 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio_io),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rst_n (mii_rst_n),
.mii_rx_clk (mii_rx_clk),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rxd (mii_rxd),
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io (linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.adc_clk_in_n(adc_clk_in_n),
.adc_clk_in_p(adc_clk_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_or_n(adc_data_or_n),
.adc_data_or_p(adc_data_or_p),
.spi_clk_i(1'b0),
.spi_clk_o(spi_clk),
.spi_csn_i(1'b1),
.spi_csn_o(spi_csn),
.spi_sdi_i(spi_miso),
.spi_sdo_i(1'b0),
.spi_sdo_o(spi_mosi));
endmodule
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************