From 255b0ebd40609996d33c552b0211aec2e8df9e3c Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 29 Mar 2016 16:50:00 +0300
Subject: [PATCH] util_dacfifo: Add dac_xfer_out control

The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
---
 library/util_dacfifo/util_dacfifo.v    | 17 +++++++++++++++--
 projects/common/xilinx/sys_dmafifo.tcl |  2 ++
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v
index d08c8b833..e73eb0091 100644
--- a/library/util_dacfifo/util_dacfifo.v
+++ b/library/util_dacfifo/util_dacfifo.v
@@ -56,11 +56,13 @@ module util_dacfifo (
   dac_clk,
   dac_valid,
   dac_data,
+  dac_xfer_out,
 
   dac_fifo_bypass
 );
 
   // depth of the FIFO
+
   parameter       ADDRESS_WIDTH = 6;
   parameter       DATA_WIDTH = 128;
 
@@ -81,6 +83,7 @@ module util_dacfifo (
   input                               dac_clk;
   input                               dac_valid;
   output  [(DATA_WIDTH-1):0]          dac_data;
+  output                              dac_xfer_out;
 
   input                               dac_fifo_bypass;
 
@@ -94,12 +97,16 @@ module util_dacfifo (
   reg                                 dma_ready_d = 1'b0;
 
   reg     [(ADDRESS_WIDTH-1):0]       dac_raddr = 'b0;
+  reg                                 dma_xfer_out = 1'b0;
+  reg     [ 2:0]                      dac_xfer_out_m = 3'b0;
 
   // internal wires
+
   wire                                dma_wren;
   wire    [(DATA_WIDTH-1):0]          dac_data_s;
 
   // write interface
+
   always @(posedge dma_clk) begin
     if(dma_rst == 1'b1) begin
       dma_ready_d <= 1'b0;
@@ -114,28 +121,34 @@ module util_dacfifo (
     if(dma_rst == 1'b1) begin
       dma_waddr <= 'b0;
       dma_lastaddr <= 'b0;
+      dma_xfer_out <= 1'b0;
     end else begin
       if (dma_valid && dma_xfer_req) begin
         dma_waddr <= dma_waddr + 1;
+        dma_xfer_out <= 1'b0;
       end
       if (dma_xfer_last) begin
         dma_lastaddr <= dma_waddr;
         dma_waddr <= 'b0;
+        dma_xfer_out <= 1'b1;
       end
     end
   end
 
   assign dma_wren = dma_valid & dma_xfer_req;
 
-  // read interface
-
   // sync lastaddr to dac clock domain
+
   always @(posedge dac_clk) begin
     dma_lastaddr_d <= dma_lastaddr;
     dma_lastaddr_2d <= dma_lastaddr_d;
+    dac_xfer_out_m <= {dac_xfer_out_m[1:0], dma_xfer_out};
   end
 
+  assign dac_xfer_out = dac_xfer_out_m[2];
+
   // generate dac read address
+
   always @(posedge dac_clk) begin
     if(dac_valid == 1'b1) begin
       if (dma_lastaddr_2d == 'h0) begin
diff --git a/projects/common/xilinx/sys_dmafifo.tcl b/projects/common/xilinx/sys_dmafifo.tcl
index 671b781bb..f6876fd9b 100644
--- a/projects/common/xilinx/sys_dmafifo.tcl
+++ b/projects/common/xilinx/sys_dmafifo.tcl
@@ -72,6 +72,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
   create_bd_pin -dir I  dac_clk
   create_bd_pin -dir I  dac_valid
   create_bd_pin -dir O  -from [expr ($data_width - 1)] -to 0 dac_data
+  create_bd_pin -dir O dac_xfer_out
 
   set util_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:util_dacfifo:1.0 util_dacfifo]
   set_property -dict [list CONFIG.DATA_WIDTH $data_width] $util_dacfifo
@@ -87,6 +88,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
   ad_connect  dma_xfer_last util_dacfifo/dma_xfer_last
   ad_connect  dac_valid util_dacfifo/dac_valid
   ad_connect  dac_data util_dacfifo/dac_data
+  ad_connect  dac_xfer_out util_dacfifo/dac_xfer_out
   ad_connect  dac_fifo_bypass util_dacfifo/dac_fifo_bypass
 
   current_bd_instance $c_instance