util_dacfifo: Add dac_xfer_out control
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.main
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46eddd04be
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255b0ebd40
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@ -56,11 +56,13 @@ module util_dacfifo (
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dac_clk,
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dac_valid,
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dac_data,
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dac_xfer_out,
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dac_fifo_bypass
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);
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// depth of the FIFO
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parameter ADDRESS_WIDTH = 6;
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parameter DATA_WIDTH = 128;
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@ -81,6 +83,7 @@ module util_dacfifo (
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input dac_clk;
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input dac_valid;
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output [(DATA_WIDTH-1):0] dac_data;
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output dac_xfer_out;
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input dac_fifo_bypass;
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@ -94,12 +97,16 @@ module util_dacfifo (
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reg dma_ready_d = 1'b0;
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reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;
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reg dma_xfer_out = 1'b0;
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reg [ 2:0] dac_xfer_out_m = 3'b0;
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// internal wires
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wire dma_wren;
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wire [(DATA_WIDTH-1):0] dac_data_s;
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// write interface
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always @(posedge dma_clk) begin
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if(dma_rst == 1'b1) begin
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dma_ready_d <= 1'b0;
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@ -114,28 +121,34 @@ module util_dacfifo (
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if(dma_rst == 1'b1) begin
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dma_waddr <= 'b0;
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dma_lastaddr <= 'b0;
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dma_xfer_out <= 1'b0;
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end else begin
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if (dma_valid && dma_xfer_req) begin
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dma_waddr <= dma_waddr + 1;
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dma_xfer_out <= 1'b0;
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end
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if (dma_xfer_last) begin
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dma_lastaddr <= dma_waddr;
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dma_waddr <= 'b0;
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dma_xfer_out <= 1'b1;
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end
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end
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end
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assign dma_wren = dma_valid & dma_xfer_req;
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// read interface
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// sync lastaddr to dac clock domain
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always @(posedge dac_clk) begin
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dma_lastaddr_d <= dma_lastaddr;
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dma_lastaddr_2d <= dma_lastaddr_d;
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dac_xfer_out_m <= {dac_xfer_out_m[1:0], dma_xfer_out};
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end
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assign dac_xfer_out = dac_xfer_out_m[2];
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// generate dac read address
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always @(posedge dac_clk) begin
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if(dac_valid == 1'b1) begin
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if (dma_lastaddr_2d == 'h0) begin
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@ -72,6 +72,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
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create_bd_pin -dir I dac_clk
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create_bd_pin -dir I dac_valid
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create_bd_pin -dir O -from [expr ($data_width - 1)] -to 0 dac_data
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create_bd_pin -dir O dac_xfer_out
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set util_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:util_dacfifo:1.0 util_dacfifo]
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set_property -dict [list CONFIG.DATA_WIDTH $data_width] $util_dacfifo
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@ -87,6 +88,7 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
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ad_connect dma_xfer_last util_dacfifo/dma_xfer_last
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ad_connect dac_valid util_dacfifo/dac_valid
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ad_connect dac_data util_dacfifo/dac_data
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ad_connect dac_xfer_out util_dacfifo/dac_xfer_out
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ad_connect dac_fifo_bypass util_dacfifo/dac_fifo_bypass
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current_bd_instance $c_instance
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