Istvan
parent
fb287d0178
commit
252c67ceff
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@ -32,7 +32,6 @@ all:
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-make -C fmcomms11 all
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-make -C fmcomms2 all
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-make -C fmcomms5 all
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-make -C fmcomms6 all
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-make -C fmcomms7 all
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-make -C imageon all
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-make -C motcon2_fmc all
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@ -70,7 +69,6 @@ clean:
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make -C fmcomms11 clean
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make -C fmcomms2 clean
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make -C fmcomms5 clean
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make -C fmcomms6 clean
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make -C fmcomms7 clean
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make -C imageon clean
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make -C motcon2_fmc clean
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@ -108,7 +106,6 @@ clean-all:
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make -C fmcomms11 clean-all
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make -C fmcomms2 clean-all
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make -C fmcomms5 clean-all
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make -C fmcomms6 clean-all
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make -C fmcomms7 clean-all
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make -C imageon clean-all
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make -C motcon2_fmc clean-all
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@ -1,21 +0,0 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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.PHONY: all clean clean-all
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all:
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-make -C zc706 all
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clean:
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make -C zc706 clean
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clean-all:
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make -C zc706 clean-all
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####################################################################################
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####################################################################################
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@ -1,88 +0,0 @@
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# adc interface
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create_bd_port -dir I adc_clk_in_p
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create_bd_port -dir I adc_clk_in_n
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create_bd_port -dir I adc_or_in_p
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create_bd_port -dir I adc_or_in_n
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create_bd_port -dir I -from 15 -to 0 adc_data_in_p
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create_bd_port -dir I -from 15 -to 0 adc_data_in_n
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# adc peripherals
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set axi_ad9652 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9652:1.0 axi_ad9652]
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set axi_ad9652_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9652_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9652_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9652_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9652_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9652_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma
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set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9652_dma
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set axi_ad9652_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 axi_ad9652_adc_fifo]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9652_adc_fifo
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set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $axi_ad9652_adc_fifo
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set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $axi_ad9652_adc_fifo
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set_property -dict [list CONFIG.DOUT_DATA_WIDTH {32}] $axi_ad9652_adc_fifo
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set data_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack
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# connections (adc)
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ad_connect adc_clk_in_p axi_ad9652/adc_clk_in_p
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ad_connect adc_clk_in_n axi_ad9652/adc_clk_in_n
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ad_connect adc_or_in_p axi_ad9652/adc_or_in_p
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ad_connect adc_or_in_n axi_ad9652/adc_or_in_n
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ad_connect adc_data_in_p axi_ad9652/adc_data_in_p
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ad_connect adc_data_in_n axi_ad9652/adc_data_in_n
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ad_connect axi_ad9652/adc_clk axi_ad9652_adc_fifo/din_clk
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ad_connect axi_ad9652/adc_rst axi_ad9652_adc_fifo/din_rst
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ad_connect sys_200m_clk axi_ad9652/delay_clk
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ad_connect sys_200m_clk axi_ad9652_dma/fifo_wr_clk
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ad_connect sys_200m_clk data_pack/adc_clk
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ad_connect sys_cpu_reset data_pack/adc_rst
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ad_connect axi_ad9652/adc_enable_0 axi_ad9652_adc_fifo/din_enable_0
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ad_connect axi_ad9652/adc_valid_0 axi_ad9652_adc_fifo/din_valid_0
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ad_connect axi_ad9652/adc_data_0 axi_ad9652_adc_fifo/din_data_0
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ad_connect axi_ad9652/adc_enable_1 axi_ad9652_adc_fifo/din_enable_1
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ad_connect axi_ad9652/adc_valid_1 axi_ad9652_adc_fifo/din_valid_1
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ad_connect axi_ad9652/adc_data_1 axi_ad9652_adc_fifo/din_data_1
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ad_connect sys_200m_clk axi_ad9652_adc_fifo/dout_clk
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ad_connect sys_cpu_resetn axi_ad9652_adc_fifo/dout_rstn
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ad_connect axi_ad9652_adc_fifo/dout_valid_0 data_pack/adc_valid_0
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ad_connect axi_ad9652_adc_fifo/dout_enable_0 data_pack/adc_enable_0
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ad_connect axi_ad9652_adc_fifo/dout_data_0 data_pack/adc_data_0
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ad_connect axi_ad9652_adc_fifo/dout_valid_1 data_pack/adc_valid_1
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ad_connect axi_ad9652_adc_fifo/dout_enable_1 data_pack/adc_enable_1
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ad_connect axi_ad9652_adc_fifo/dout_data_1 data_pack/adc_data_1
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ad_connect axi_ad9652_adc_fifo/din_ovf axi_ad9652/adc_dovf
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ad_connect data_pack/adc_valid axi_ad9652_dma/fifo_wr_en
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ad_connect data_pack/adc_sync axi_ad9652_dma/fifo_wr_sync
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ad_connect data_pack/adc_data axi_ad9652_dma/fifo_wr_din
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ad_connect axi_ad9652_adc_fifo/dout_ovf axi_ad9652_dma/fifo_wr_overflow
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# interconnect (cpu)
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ad_cpu_interconnect 0x79020000 axi_ad9652
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ad_cpu_interconnect 0x7c420000 axi_ad9652_dma
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# interconnect (mem/adc)
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ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_200m_clk axi_ad9652_dma/m_dest_axi
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ad_connect sys_cpu_resetn axi_ad9652_dma/m_dest_axi_aresetn
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# interrupts
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ad_cpu_interrupt ps-13 mb-13 axi_ad9652_dma/irq
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@ -1,109 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module fmcomms6_spi (
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso,
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spi_sdio);
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// 4 wire
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input [ 2:0] spi_csn;
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input spi_clk;
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input spi_mosi;
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output spi_miso;
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// 3 wire
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inout spi_sdio;
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// internal registers
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reg [ 5:0] spi_count = 'd0;
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reg spi_rd_wr_n = 'd0;
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reg spi_enable = 'd0;
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// internal signals
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wire spi_csn_s;
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wire spi_enable_s;
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// check on rising edge and change on falling edge
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assign spi_csn_s = & spi_csn;
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assign spi_enable_s = spi_enable & ~spi_csn_s;
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always @(posedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_count <= 6'd0;
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spi_rd_wr_n <= 1'd0;
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end else begin
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spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
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if (spi_count == 6'd0) begin
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spi_rd_wr_n <= spi_mosi;
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end
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end
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end
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always @(negedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_enable <= 1'b0;
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end else begin
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if ((spi_count == 6'd16) && (spi_csn[2] == 1'b1)) begin
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spi_enable <= spi_rd_wr_n;
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end
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end
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end
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// io butter
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IOBUF i_iobuf_sdio (
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.T (spi_enable_s),
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.I (spi_mosi),
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.O (spi_miso),
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.IO (spi_sdio));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -1,79 +0,0 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.xdc
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M_DEPS += system_bd.tcl
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M_DEPS += ../common/fmcomms6_spi.v
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M_DEPS += ../common/fmcomms6_bd.tcl
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M_DEPS += ../../scripts/adi_project.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../scripts/adi_board.tcl
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M_DEPS += ../../common/zc706/zc706_system_constr.xdc
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M_DEPS += ../../common/zc706/zc706_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_ad9652/axi_ad9652.xpr
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M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
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M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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M_FLIST += *.ip_user_files
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.PHONY: all lib clean clean-all
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all: lib fmcomms6_zc706.sdk/system_top.hdf
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clean:
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rm -rf $(M_FLIST)
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clean-all:clean
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make -C ../../../library/axi_ad9652 clean
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make -C ../../../library/axi_clkgen clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_hdmi_tx clean
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make -C ../../../library/axi_spdif_tx clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_wfifo clean
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fmcomms6_zc706.sdk/system_top.hdf: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> fmcomms6_zc706_vivado.log 2>&1
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lib:
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make -C ../../../library/axi_ad9652
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make -C ../../../library/axi_clkgen
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_hdmi_tx
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make -C ../../../library/axi_spdif_tx
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make -C ../../../library/util_cpack
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make -C ../../../library/util_wfifo
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####################################################################################
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####################################################################################
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@ -1,4 +0,0 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source ../common/fmcomms6_bd.tcl
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@ -1,57 +0,0 @@
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# adc
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set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## G06 FMC_LPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## G07 FMC_LPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## H22 FMC_LPC_LA19_P
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set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## H23 FMC_LPC_LA19_N
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set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## D08 FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## D09 FMC_LPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## H07 FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## H08 FMC_LPC_LA02_N
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set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## G09 FMC_LPC_LA03_P
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set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## G10 FMC_LPC_LA03_N
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set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## H10 FMC_LPC_LA04_P
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set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## H11 FMC_LPC_LA04_N
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set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## D11 FMC_LPC_LA05_P
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set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## D12 FMC_LPC_LA05_N
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set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## C10 FMC_LPC_LA06_P
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set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## C11 FMC_LPC_LA06_N
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set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H13 FMC_LPC_LA07_P
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set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H14 FMC_LPC_LA07_N
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set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G12 FMC_LPC_LA08_P
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set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G13 FMC_LPC_LA08_N
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set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## D14 FMC_LPC_LA09_P
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set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## D15 FMC_LPC_LA09_N
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set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## C14 FMC_LPC_LA10_P
|
||||
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## C15 FMC_LPC_LA10_N
|
||||
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## H16 FMC_LPC_LA11_P
|
||||
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## H17 FMC_LPC_LA11_N
|
||||
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## G15 FMC_LPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## G16 FMC_LPC_LA12_N
|
||||
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## D17 FMC_LPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## D18 FMC_LPC_LA13_N
|
||||
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## C18 FMC_LPC_LA14_P
|
||||
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## C19 FMC_LPC_LA14_N
|
||||
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[14]] ; ## H19 FMC_LPC_LA15_P
|
||||
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[14]] ; ## H20 FMC_LPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[15]] ; ## G18 FMC_LPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[15]] ; ## G19 FMC_LPC_LA16_N
|
||||
|
||||
# spi
|
||||
|
||||
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25} [get_ports spi_ad9517_csn] ; ## G24 FMC_LPC_LA22_P
|
||||
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports spi_ad9652_csn] ; ## H25 FMC_LPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports spi_adf4351_csn] ; ## H26 FMC_LPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D23 FMC_LPC_LA23_P
|
||||
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## G25 FMC_LPC_LA22_N
|
||||
|
||||
# gpio
|
||||
|
||||
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports adf4351_ld] ; ## D24 FMC_LPC_LA23_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name adc_clk_in -period 3.22 [get_ports adc_clk_in_p]
|
||||
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
|
||||
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
adi_project_create fmcomms6_zc706
|
||||
adi_project_files fmcomms6_zc706 [list \
|
||||
"../common/fmcomms6_spi.v" \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc"\
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||
|
||||
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
|
||||
|
||||
adi_project_run fmcomms6_zc706
|
||||
|
||||
|
||||
|
|
@ -1,263 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
ddr_addr,
|
||||
ddr_ba,
|
||||
ddr_cas_n,
|
||||
ddr_ck_n,
|
||||
ddr_ck_p,
|
||||
ddr_cke,
|
||||
ddr_cs_n,
|
||||
ddr_dm,
|
||||
ddr_dq,
|
||||
ddr_dqs_n,
|
||||
ddr_dqs_p,
|
||||
ddr_odt,
|
||||
ddr_ras_n,
|
||||
ddr_reset_n,
|
||||
ddr_we_n,
|
||||
|
||||
fixed_io_ddr_vrn,
|
||||
fixed_io_ddr_vrp,
|
||||
fixed_io_mio,
|
||||
fixed_io_ps_clk,
|
||||
fixed_io_ps_porb,
|
||||
fixed_io_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
hdmi_out_clk,
|
||||
hdmi_vsync,
|
||||
hdmi_hsync,
|
||||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
|
||||
spdif,
|
||||
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
|
||||
adc_clk_in_p,
|
||||
adc_clk_in_n,
|
||||
adc_or_in_p,
|
||||
adc_or_in_n,
|
||||
adc_data_in_p,
|
||||
adc_data_in_n,
|
||||
|
||||
spi_adf4351_csn,
|
||||
spi_ad9652_csn,
|
||||
spi_ad9517_csn,
|
||||
spi_clk,
|
||||
spi_sdio,
|
||||
adf4351_ld);
|
||||
|
||||
inout [14:0] ddr_addr;
|
||||
inout [ 2:0] ddr_ba;
|
||||
inout ddr_cas_n;
|
||||
inout ddr_ck_n;
|
||||
inout ddr_ck_p;
|
||||
inout ddr_cke;
|
||||
inout ddr_cs_n;
|
||||
inout [ 3:0] ddr_dm;
|
||||
inout [31:0] ddr_dq;
|
||||
inout [ 3:0] ddr_dqs_n;
|
||||
inout [ 3:0] ddr_dqs_p;
|
||||
inout ddr_odt;
|
||||
inout ddr_ras_n;
|
||||
inout ddr_reset_n;
|
||||
inout ddr_we_n;
|
||||
|
||||
inout fixed_io_ddr_vrn;
|
||||
inout fixed_io_ddr_vrp;
|
||||
inout [53:0] fixed_io_mio;
|
||||
inout fixed_io_ps_clk;
|
||||
inout fixed_io_ps_porb;
|
||||
inout fixed_io_ps_srstb;
|
||||
|
||||
inout [14:0] gpio_bd;
|
||||
|
||||
output hdmi_out_clk;
|
||||
output hdmi_vsync;
|
||||
output hdmi_hsync;
|
||||
output hdmi_data_e;
|
||||
output [23:0] hdmi_data;
|
||||
|
||||
output spdif;
|
||||
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
input adc_clk_in_p;
|
||||
input adc_clk_in_n;
|
||||
input adc_or_in_p;
|
||||
input adc_or_in_n;
|
||||
input [15:0] adc_data_in_p;
|
||||
input [15:0] adc_data_in_n;
|
||||
|
||||
output spi_adf4351_csn;
|
||||
output spi_ad9652_csn;
|
||||
output spi_ad9517_csn;
|
||||
output spi_clk;
|
||||
inout spi_sdio;
|
||||
inout adf4351_ld;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [ 2:0] spi0_csn;
|
||||
wire spi0_clk;
|
||||
wire spi0_mosi;
|
||||
wire spi0_miso;
|
||||
wire [ 2:0] spi1_csn;
|
||||
wire spi1_clk;
|
||||
wire spi1_mosi;
|
||||
wire spi1_miso;
|
||||
|
||||
assign gpio_i[63:33] = gpio_o[63:33];
|
||||
assign gpio_i[31:15] = gpio_o[31:15];
|
||||
|
||||
// spi
|
||||
|
||||
assign spi_clk = spi0_clk;
|
||||
assign spi_ad9517_csn = spi0_csn[0];
|
||||
assign spi_ad9652_csn = spi0_csn[1];
|
||||
assign spi_adf4351_csn = spi0_csn[2];
|
||||
|
||||
// instantiations
|
||||
|
||||
fmcomms6_spi i_spi (
|
||||
.spi_csn (spi0_csn),
|
||||
.spi_clk (spi0_clk),
|
||||
.spi_mosi (spi0_mosi),
|
||||
.spi_miso (spi0_miso),
|
||||
.spi_sdio (spi_sdio));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf (
|
||||
.dio_t (gpio_t[32]),
|
||||
.dio_i (gpio_o[32]),
|
||||
.dio_o (gpio_i[32]),
|
||||
.dio_p (adf4351_ld));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
|
||||
.dio_t (gpio_t[14:0]),
|
||||
.dio_i (gpio_o[14:0]),
|
||||
.dio_o (gpio_i[14:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.adc_clk_in_n (adc_clk_in_n),
|
||||
.adc_clk_in_p (adc_clk_in_p),
|
||||
.adc_data_in_n (adc_data_in_n),
|
||||
.adc_data_in_p (adc_data_in_p),
|
||||
.adc_or_in_n (adc_or_in_n),
|
||||
.adc_or_in_p (adc_or_in_p),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.ps_intr_11 (1'b0),
|
||||
.ps_intr_12 (1'b0),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (spi0_clk),
|
||||
.spi0_clk_o (spi0_clk),
|
||||
.spi0_csn_0_o (spi0_csn[0]),
|
||||
.spi0_csn_1_o (spi0_csn[1]),
|
||||
.spi0_csn_2_o (spi0_csn[2]),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi0_miso),
|
||||
.spi0_sdo_i (spi0_mosi),
|
||||
.spi0_sdo_o (spi0_mosi),
|
||||
.spi1_clk_i (spi1_clk),
|
||||
.spi1_clk_o (spi1_clk),
|
||||
.spi1_csn_0_o (spi1_csn[0]),
|
||||
.spi1_csn_1_o (spi1_csn[1]),
|
||||
.spi1_csn_2_o (spi1_csn[2]),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b1),
|
||||
.spi1_sdo_i (spi1_mosi),
|
||||
.spi1_sdo_o (spi1_mosi));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue