sysid: Specified clock interface for input clk

2019-11-18 10:58:17 +00:00 · 2019-11-18 10:58:17 +00:00 · 24b5de4438
parent dfe3258a4f
commit 24b5de4438
1 changed files with 2 additions and 0 deletions
--- a/library/sysid_rom/sysid_rom_ip.tcl
+++ b/library/sysid_rom/sysid_rom_ip.tcl
@ -10,4 +10,6 @@ adi_ip_files sysid_rom [list \
 adi_ip_properties_lite sysid_rom
 set cc [ipx::current_core]

+ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core $cc