ad_gt_es: status asserted early for latency
parent
04df908fbf
commit
2472d61daf
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@ -131,6 +131,8 @@ module ad_gt_es (
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// state machine
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// state machine
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parameter ES_FSM_IDLE = 6'h00;
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parameter ES_FSM_IDLE = 6'h00;
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parameter ES_FSM_STATUS = 6'h30;
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parameter ES_FSM_INIT = 6'h31;
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parameter ES_FSM_CTRLINIT_READ = 6'h01;
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parameter ES_FSM_CTRLINIT_READ = 6'h01;
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parameter ES_FSM_CTRLINIT_RRDY = 6'h02;
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parameter ES_FSM_CTRLINIT_RRDY = 6'h02;
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parameter ES_FSM_CTRLINIT_WRITE = 6'h03;
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parameter ES_FSM_CTRLINIT_WRITE = 6'h03;
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@ -451,15 +453,25 @@ module ad_gt_es (
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end else begin
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end else begin
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case (es_fsm)
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case (es_fsm)
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ES_FSM_IDLE: begin // idle
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ES_FSM_IDLE: begin // idle
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if (es_start == 1'b0) begin
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if (es_start == 1'b1) begin
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es_fsm <= ES_FSM_STATUS;
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end else begin
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es_fsm <= ES_FSM_IDLE;
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es_fsm <= ES_FSM_IDLE;
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end else if (es_init == 1'b1) begin
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end
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end
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ES_FSM_STATUS: begin // set status
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es_fsm <= ES_FSM_INIT;
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end
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ES_FSM_INIT: begin // initialize
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if (es_init == 1'b1) begin
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es_fsm <= ES_FSM_CTRLINIT_READ;
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es_fsm <= ES_FSM_CTRLINIT_READ;
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end else begin
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end else begin
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es_fsm <= ES_FSM_HOFFSET_READ;
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es_fsm <= ES_FSM_HOFFSET_READ;
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end
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end
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end
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end
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ES_FSM_CTRLINIT_READ: begin // control read
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ES_FSM_CTRLINIT_READ: begin // control read
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es_fsm <= ES_FSM_CTRLINIT_RRDY;
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es_fsm <= ES_FSM_CTRLINIT_RRDY;
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end
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end
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