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ad9361- a10soc sdc files

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Rejeesh Kutty 2016-04-28 15:44:55 -04:00
parent aa2aa902bf
commit 243d3e6e41
3 changed files with 7 additions and 1 deletions
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2
library/axi_ad9361/axi_ad9361.v
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@ -447,7 +447,7 @@ module axi_ad9361 (
assign up_adc_drdata_s[64:35] = 30'd0; assign up_adc_drdata_s[64:35] = 30'd0;
assign up_dac_drdata_s[79:50] = 30'd0; assign up_dac_drdata_s[79:50] = 30'd0;
axi_ad9361_dev_if #( axi_ad9361_lvds_if #(
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP)) .IO_DELAY_GROUP (IO_DELAY_GROUP))

4
library/axi_ad9361/axi_ad9361_constr.sdc Normal file
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@ -0,0 +1,4 @@
set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*]
set_false_path -from [get_registers *i_dev_if|up_txnrx_int*] -to [get_registers *i_dev_if|txnrx_up_m1*]

2
library/axi_ad9361/axi_ad9361_hw.tcl
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@ -54,6 +54,8 @@ add_fileset_file axi_ad9361_tx.v VERILOG PATH axi_ad9361_tx.v
add_fileset_file axi_ad9361_tdd.v VERILOG PATH axi_ad9361_tdd.v add_fileset_file axi_ad9361_tdd.v VERILOG PATH axi_ad9361_tdd.v
add_fileset_file axi_ad9361_tdd_if.v VERILOG PATH axi_ad9361_tdd_if.v add_fileset_file axi_ad9361_tdd_if.v VERILOG PATH axi_ad9361_tdd_if.v
add_fileset_file axi_ad9361.v VERILOG PATH axi_ad9361.v TOP_LEVEL_FILE add_fileset_file axi_ad9361.v VERILOG PATH axi_ad9361.v TOP_LEVEL_FILE
add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
add_fileset_file axi_ad9361_constr.sdc SDC PATH axi_ad9361_constr.sdc
# parameters # parameters