fmcomms1: AC701 update project to new framework
Adrian Costina
parent
0162009099
commit
243a9bc992
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@ -1,4 +1,5 @@
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source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
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source ../common/fmcomms1_bd.tcl
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@ -157,6 +157,3 @@ set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[13]}]
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create_clock -period 2.000 -name dac_clk_in [get_ports dac_clk_in_p]
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create_clock -period 4.000 -name adc_clk_in [get_ports adc_clk_in_p]
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create_clock -period 8.000 -name dac_div_clk [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
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set_false_path -from [get_pins i_system_wrapper/system_i/axi_ad9643_dma/inst/i_request_arb/i_src_dma_fifo/overflow_reg/C] \
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-to [get_pins i_system_wrapper/system_i/sys_wfifo/wfifo_ctl/inst/m_wovf_m1_reg/D]
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@ -1,13 +1,13 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_create fmcomms1_ac701
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adi_project_files fmcomms1_ac701 [list \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ]
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc]
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@ -77,8 +77,7 @@ module system_top (
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fan_pwm,
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gpio_lcd,
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gpio_led,
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gpio_sw,
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gpio_bd,
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iic_rstn,
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iic_scl,
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@ -101,15 +100,7 @@ module system_top (
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adc_data_in_n,
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ref_clk_out_p,
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ref_clk_out_n,
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hdmi_out_clk,
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hdmi_hsync,
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hdmi_vsync,
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hdmi_data_e,
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hdmi_data,
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spdif);
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ref_clk_out_n);
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input sys_rst;
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input sys_clk_p;
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@ -147,8 +138,7 @@ module system_top (
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output fan_pwm;
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inout [ 6:0] gpio_lcd;
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inout [ 3:0] gpio_led;
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inout [ 8:0] gpio_sw;
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inout [12:0] gpio_bd;
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output iic_rstn;
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inout iic_scl;
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@ -173,14 +163,6 @@ module system_top (
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output ref_clk_out_p;
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output ref_clk_out_n;
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output hdmi_out_clk;
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output hdmi_hsync;
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output hdmi_vsync;
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output hdmi_data_e;
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output [23:0] hdmi_data;
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output spdif;
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// internal registers
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reg [63:0] dac_ddata_0 = 'd0;
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@ -192,6 +174,9 @@ module system_top (
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire dac_clk;
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wire dac_valid_0;
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wire dac_enable_0;
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@ -207,14 +192,21 @@ module system_top (
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wire [15:0] adc_data_1;
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wire ref_clk;
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wire oddr_ref_clk;
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wire [31:0] mb_intrs;
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// assignments
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assign mgt_clk_sel = 2'd0;
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assign mgt_clk_sel = 2'd0;
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assign fan_pwm = 1'b1;
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assign iic_rstn = 1'b1;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_sw_led (
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.dt (gpio_t[12:0]),
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.di (gpio_o[12:0]),
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.do (gpio_i[12:0]),
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.dio(gpio_bd));
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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@ -279,42 +271,20 @@ module system_top (
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.fan_pwm (fan_pwm),
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.gpio_lcd_tri_io (gpio_lcd),
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.gpio_led_tri_io (gpio_led),
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.gpio_sw_tri_io (gpio_sw),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio0_i (gpio_i[31:0]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio1_i (gpio_i[63:32]),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.iic_rstn (iic_rstn),
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.mb_intr_10 (mb_intrs[10]),
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.mb_intr_11 (mb_intrs[11]),
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.mb_intr_12 (mb_intrs[12]),
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.mb_intr_13 (mb_intrs[13]),
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.mb_intr_14 (mb_intrs[14]),
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.mb_intr_15 (mb_intrs[15]),
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.mb_intr_16 (mb_intrs[16]),
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.mb_intr_17 (mb_intrs[17]),
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.mb_intr_18 (mb_intrs[18]),
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.mb_intr_19 (mb_intrs[19]),
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.mb_intr_20 (mb_intrs[20]),
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.mb_intr_21 (mb_intrs[21]),
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.mb_intr_22 (mb_intrs[22]),
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.mb_intr_23 (mb_intrs[23]),
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.mb_intr_24 (mb_intrs[24]),
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.mb_intr_25 (mb_intrs[25]),
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.mb_intr_26 (mb_intrs[26]),
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.mb_intr_27 (mb_intrs[27]),
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.mb_intr_28 (mb_intrs[28]),
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.mb_intr_29 (mb_intrs[29]),
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.mb_intr_30 (mb_intrs[30]),
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.mb_intr_31 (mb_intrs[31]),
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.ad9122_dma_irq (mb_intrs[12]),
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.ad9643_dma_irq (mb_intrs[13]),
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.mb_intr_06 (1'b0),
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.mb_intr_07 (1'b0),
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.mb_intr_08 (1'b0),
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.mb_intr_14 (1'b0),
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.mb_intr_15 (1'b0),
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.adc_clk (adc_clk),
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.adc_clk_in_n (adc_clk_in_n),
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.adc_clk_in_p (adc_clk_in_p),
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@ -322,7 +292,6 @@ module system_top (
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.adc_data_1 (adc_data_1),
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.adc_data_in_n (adc_data_in_n),
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.adc_data_in_p (adc_data_in_p),
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.adc_dma_sync (1'b1),
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.adc_dma_wdata (adc_dma_wdata),
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.adc_dma_wr (adc_dma_wr),
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.adc_enable_0 (adc_enable_0),
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@ -358,7 +327,6 @@ module system_top (
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.rgmii_td (phy_tx_data),
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.rgmii_tx_ctl (phy_tx_ctrl),
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.rgmii_txc (phy_tx_clk),
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.spdif (spdif),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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