diff --git a/library/data_offload/data_offload.v b/library/data_offload/data_offload.v
index 3fc389bce..9dbd45707 100644
--- a/library/data_offload/data_offload.v
+++ b/library/data_offload/data_offload.v
@@ -38,7 +38,7 @@ module data_offload #(
 
   parameter          ID = 0,
   parameter   [ 0:0] MEM_TYPE = 1'b0,               // 1'b0 -FPGA RAM; 1'b1 - external memory
-  parameter   [31:0] MEM_SIZE = 1023,               // memory size in bytes -1 - max 16 GB
+  parameter   [33:0] MEM_SIZE = 1024,               // memory size in bytes -1 - max 16 GB
   parameter          MEMC_UIF_DATA_WIDTH = 512,
   parameter          MEMC_UIF_ADDRESS_WIDTH = 31,
   parameter   [31:0] MEMC_BADDRESS = 32'h00000000,
@@ -182,9 +182,9 @@ module data_offload #(
   wire                                        dst_mem_valid_int_s;
   wire                                        m_axis_reset_int_s;
 
-  wire  [31:0]                                src_transfer_length_s;
+  wire  [33:0]                                src_transfer_length_s;
   wire                                        src_wr_last_int_s;
-  wire  [31:0]                                src_wr_last_beat_s;
+  wire  [33:0]                                src_wr_last_beat_s;
 
   wire                                        int_not_full;
 
@@ -193,7 +193,7 @@ module data_offload #(
 
   // internal registers
 
-  reg [31:0] src_data_counter = 0;
+  reg [33:0] src_data_counter = 0;
   reg        dst_mem_valid_d = 1'b0;
 
   generate
@@ -405,7 +405,7 @@ always @(posedge s_axis_aclk) begin
   end
 end
 // transfer length is in bytes, but counter monitors the source data beats
-assign src_wr_last_beat_s = (src_transfer_length_s == 32'h0) ? MEM_SIZE[31:SRC_BEAT_BYTE]-1 : src_transfer_length_s[31:SRC_BEAT_BYTE];
+assign src_wr_last_beat_s = (src_transfer_length_s == 'h0) ? MEM_SIZE[33:SRC_BEAT_BYTE]-1 : src_transfer_length_s[33:SRC_BEAT_BYTE]-1;
 assign src_wr_last_int_s = (src_data_counter == src_wr_last_beat_s) ?  1'b1 : 1'b0;
 
 endmodule
diff --git a/library/data_offload/data_offload_fsm.v b/library/data_offload/data_offload_fsm.v
index d40fe2fa9..814ebfad7 100644
--- a/library/data_offload/data_offload_fsm.v
+++ b/library/data_offload/data_offload_fsm.v
@@ -183,7 +183,7 @@ module data_offload_fsm #(
           end
 
           WR_WRITE_TO_MEM: begin
-            if ((wr_almost_full || wr_last) && wr_valid_out) begin
+            if ((wr_full || wr_last) && wr_valid_out) begin
               wr_fsm_state <= WR_WAIT_TO_END;
             end else begin
               wr_fsm_state <= WR_WRITE_TO_MEM;
diff --git a/library/data_offload/data_offload_regmap.v b/library/data_offload/data_offload_regmap.v
index 630082723..fa9471898 100644
--- a/library/data_offload/data_offload_regmap.v
+++ b/library/data_offload/data_offload_regmap.v
@@ -77,7 +77,7 @@ module data_offload_regmap #(
   output                  sync,
   output      [ 1:0]      sync_config,
 
-  output reg  [31:0]      src_transfer_length,
+  output reg  [33:0]      src_transfer_length,
 
   // FSM control and status
   input       [ 1:0]      src_fsm_status,
@@ -101,7 +101,7 @@ module data_offload_regmap #(
   reg           up_sync = 'd0;
   reg   [ 1:0]  up_sync_config = 'd0;
   reg           up_oneshot = 1'b0;
-  reg   [31:0]  up_transfer_length = 'd0;
+  reg   [33:0]  up_transfer_length = 'd0;
 
   //internal signals
 
@@ -112,7 +112,7 @@ module data_offload_regmap #(
   wire  [31:0]  up_sample_count_lsb_s;
   wire          src_sw_resetn_s;
   wire          dst_sw_resetn_s;
-  wire  [31:0]  src_transfer_length_s;
+  wire  [33:0]  src_transfer_length_s;
 
   // write interface
   always @(posedge up_clk) begin
@@ -124,7 +124,7 @@ module data_offload_regmap #(
       up_bypass <= 'd0;
       up_sync <= 'd0;
       up_sync_config <= 'd0;
-      up_transfer_length <= 32'h0;
+      up_transfer_length <= 34'h0;
     end else begin
       up_wack <= up_wreq;
       /* Scratch Register */
@@ -133,7 +133,7 @@ module data_offload_regmap #(
       end
       /* Transfer Length Register */
       if ((up_wreq == 1'b1) && (up_waddr[11:0] == 14'h07)) begin
-        up_transfer_length <= up_wdata;
+        up_transfer_length <= {up_wdata[27:0], 6'b0};
       end
       /* Reset Offload Register */
       if ((up_wreq == 1'b1) && (up_waddr[11:0] == 14'h21)) begin
@@ -197,7 +197,7 @@ module data_offload_regmap #(
         };
 
         /* Configuration data transfer length */
-        14'h007:  up_rdata <= up_transfer_length;
+        14'h007:  up_rdata <= {4'b0, up_transfer_length[33:6]};
 
         /* 0x08-0x1f reserved for future use */
 
@@ -357,7 +357,7 @@ module data_offload_regmap #(
   );
 
   sync_data #(
-    .NUM_OF_BITS (32),
+    .NUM_OF_BITS (34),
     .ASYNC_CLK (1))
   i_sync_src_transfer_length (
     .in_clk (up_clk),