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avl_adxcfg- compile fixes

main
Rejeesh Kutty 2016-09-01 10:02:14 -04:00
parent 93fa5aeec3
commit 230f1526c0
2 changed files with 106 additions and 111 deletions
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112
library/altera/avl_adxcfg/avl_adxcfg.v
View File

@ -48,112 +48,112 @@ module avl_adxcfg (
input rcfg_in_write_0,
input [11:0] rcfg_in_address_0,
input [31:0] rcfg_in_writedata_0,
output [31:0] rcfg_in_readata_0,
output [31:0] rcfg_in_readdata_0,
output rcfg_in_waitrequest_0,
output rcfg_out_read_0,
output rcfg_out_write_0,
output [11:0] rcfg_out_address_0,
output [31:0] rcfg_out_writedata_0,
input [31:0] rcfg_out_readata_0,
input [31:0] rcfg_out_readdata_0,
input rcfg_out_waitrequest_0,
input rcfg_in_read_1,
input rcfg_in_write_1,
input [11:0] rcfg_in_address_1,
input [31:0] rcfg_in_writedata_1,
output [31:0] rcfg_in_readata_1,
output [31:0] rcfg_in_readdata_1,
output rcfg_in_waitrequest_1,
output rcfg_out_read_1,
output rcfg_out_write_1,
output [11:0] rcfg_out_address_1,
output [31:0] rcfg_out_writedata_1,
input [31:0] rcfg_out_readata_1,
input [31:0] rcfg_out_readdata_1,
input rcfg_out_waitrequest_1,
input rcfg_in_read_2,
input rcfg_in_write_2,
input [11:0] rcfg_in_address_2,
input [31:0] rcfg_in_writedata_2,
output [31:0] rcfg_in_readata_2,
output [31:0] rcfg_in_readdata_2,
output rcfg_in_waitrequest_2,
output rcfg_out_read_2,
output rcfg_out_write_2,
output [11:0] rcfg_out_address_2,
output [31:0] rcfg_out_writedata_2,
input [31:0] rcfg_out_readata_2,
input [31:0] rcfg_out_readdata_2,
input rcfg_out_waitrequest_2,
input rcfg_in_read_3,
input rcfg_in_write_3,
input [11:0] rcfg_in_address_3,
input [31:0] rcfg_in_writedata_3,
output [31:0] rcfg_in_readata_3,
output [31:0] rcfg_in_readdata_3,
output rcfg_in_waitrequest_3,
output rcfg_out_read_3,
output rcfg_out_write_3,
output [11:0] rcfg_out_address_3,
output [31:0] rcfg_out_writedata_3,
input [31:0] rcfg_out_readata_3,
input [31:0] rcfg_out_readdata_3,
input rcfg_out_waitrequest_3,
input rcfg_in_read_4,
input rcfg_in_write_4,
input [11:0] rcfg_in_address_4,
input [31:0] rcfg_in_writedata_4,
output [31:0] rcfg_in_readata_4,
output [31:0] rcfg_in_readdata_4,
output rcfg_in_waitrequest_4,
output rcfg_out_read_4,
output rcfg_out_write_4,
output [11:0] rcfg_out_address_4,
output [31:0] rcfg_out_writedata_4,
input [31:0] rcfg_out_readata_4,
input [31:0] rcfg_out_readdata_4,
input rcfg_out_waitrequest_4,
input rcfg_in_read_5,
input rcfg_in_write_5,
input [11:0] rcfg_in_address_5,
input [31:0] rcfg_in_writedata_5,
output [31:0] rcfg_in_readata_5,
output [31:0] rcfg_in_readdata_5,
output rcfg_in_waitrequest_5,
output rcfg_out_read_5,
output rcfg_out_write_5,
output [11:0] rcfg_out_address_5,
output [31:0] rcfg_out_writedata_5,
input [31:0] rcfg_out_readata_5,
input [31:0] rcfg_out_readdata_5,
input rcfg_out_waitrequest_5,
input rcfg_in_read_6,
input rcfg_in_write_6,
input [11:0] rcfg_in_address_6,
input [31:0] rcfg_in_writedata_6,
output [31:0] rcfg_in_readata_6,
output [31:0] rcfg_in_readdata_6,
output rcfg_in_waitrequest_6,
output rcfg_out_read_6,
output rcfg_out_write_6,
output [11:0] rcfg_out_address_6,
output [31:0] rcfg_out_writedata_6,
input [31:0] rcfg_out_readata_6,
input [31:0] rcfg_out_readdata_6,
input rcfg_out_waitrequest_6,
input rcfg_in_read_7,
input rcfg_in_write_7,
input [11:0] rcfg_in_address_7,
input [31:0] rcfg_in_writedata_7,
output [31:0] rcfg_in_readata_7,
output [31:0] rcfg_in_readdata_7,
output rcfg_in_waitrequest_7,
output rcfg_out_read_7,
output rcfg_out_write_7,
output [11:0] rcfg_out_address_7,
output [31:0] rcfg_out_writedata_7,
input [31:0] rcfg_out_readata_7,
input [31:0] rcfg_out_readdata_7,
input rcfg_out_waitrequest_7);
// internal registers
@ -162,67 +162,67 @@ module avl_adxcfg (
reg [31:0] rcfg_out_writedata = 'd0;
reg rcfg_out_iread_0 = 'd0;
reg rcfg_out_iwrite_0 = 'd0;
reg [31:0] rcfg_in_ireadata_0 = 'd0;
reg [31:0] rcfg_in_ireaddata_0 = 'd0;
reg rcfg_in_iwaitrequest_0 = 'd0;
reg rcfg_out_iread_1 = 'd0;
reg rcfg_out_iwrite_1 = 'd0;
reg [31:0] rcfg_in_ireadata_1 = 'd0;
reg [31:0] rcfg_in_ireaddata_1 = 'd0;
reg rcfg_in_iwaitrequest_1 = 'd0;
reg rcfg_out_iread_2 = 'd0;
reg rcfg_out_iwrite_2 = 'd0;
reg [31:0] rcfg_in_ireadata_2 = 'd0;
reg [31:0] rcfg_in_ireaddata_2 = 'd0;
reg rcfg_in_iwaitrequest_2 = 'd0;
reg rcfg_out_iread_3 = 'd0;
reg rcfg_out_iwrite_3 = 'd0;
reg [31:0] rcfg_in_ireadata_3 = 'd0;
reg [31:0] rcfg_in_ireaddata_3 = 'd0;
reg rcfg_in_iwaitrequest_3 = 'd0;
reg rcfg_out_iread_4 = 'd0;
reg rcfg_out_iwrite_4 = 'd0;
reg [31:0] rcfg_in_ireadata_4 = 'd0;
reg [31:0] rcfg_in_ireaddata_4 = 'd0;
reg rcfg_in_iwaitrequest_4 = 'd0;
reg rcfg_out_iread_5 = 'd0;
reg rcfg_out_iwrite_5 = 'd0;
reg [31:0] rcfg_in_ireadata_5 = 'd0;
reg [31:0] rcfg_in_ireaddata_5 = 'd0;
reg rcfg_in_iwaitrequest_5 = 'd0;
reg rcfg_out_iread_6 = 'd0;
reg rcfg_out_iwrite_6 = 'd0;
reg [31:0] rcfg_in_ireadata_6 = 'd0;
reg [31:0] rcfg_in_ireaddata_6 = 'd0;
reg rcfg_in_iwaitrequest_6 = 'd0;
reg rcfg_out_iread_7 = 'd0;
reg rcfg_out_iwrite_7 = 'd0;
reg [31:0] rcfg_in_ireadata_7 = 'd0;
reg [31:0] rcfg_in_ireaddata_7 = 'd0;
reg rcfg_in_iwaitrequest_7 = 'd0;
reg [ 3:0] rcfg_select = 'd0;
// internal signals
wire recfg_in_req_0_s;
wire recfg_in_req_1_s;
wire recfg_in_req_2_s;
wire recfg_in_req_3_s;
wire recfg_in_req_4_s;
wire recfg_in_req_5_s;
wire recfg_in_req_6_s;
wire recfg_in_req_7_s;
wire rcfg_in_req_0_s;
wire rcfg_in_req_1_s;
wire rcfg_in_req_2_s;
wire rcfg_in_req_3_s;
wire rcfg_in_req_4_s;
wire rcfg_in_req_5_s;
wire rcfg_in_req_6_s;
wire rcfg_in_req_7_s;
// xcvr sharing requires same bus with ONLY different write/read signals
assign rcfg_out_address_0 <= rcfg_out_address;
assign rcfg_out_writedata_0 <= rcfg_out_writedata;
assign rcfg_out_address_1 <= rcfg_out_address;
assign rcfg_out_writedata_1 <= rcfg_out_writedata;
assign rcfg_out_address_2 <= rcfg_out_address;
assign rcfg_out_writedata_2 <= rcfg_out_writedata;
assign rcfg_out_address_3 <= rcfg_out_address;
assign rcfg_out_writedata_3 <= rcfg_out_writedata;
assign rcfg_out_address_4 <= rcfg_out_address;
assign rcfg_out_writedata_4 <= rcfg_out_writedata;
assign rcfg_out_address_5 <= rcfg_out_address;
assign rcfg_out_writedata_5 <= rcfg_out_writedata;
assign rcfg_out_address_6 <= rcfg_out_address;
assign rcfg_out_writedata_6 <= rcfg_out_writedata;
assign rcfg_out_address_7 <= rcfg_out_address;
assign rcfg_out_writedata_7 <= rcfg_out_writedata;
assign rcfg_out_address_0 = rcfg_out_address;
assign rcfg_out_writedata_0 = rcfg_out_writedata;
assign rcfg_out_address_1 = rcfg_out_address;
assign rcfg_out_writedata_1 = rcfg_out_writedata;
assign rcfg_out_address_2 = rcfg_out_address;
assign rcfg_out_writedata_2 = rcfg_out_writedata;
assign rcfg_out_address_3 = rcfg_out_address;
assign rcfg_out_writedata_3 = rcfg_out_writedata;
assign rcfg_out_address_4 = rcfg_out_address;
assign rcfg_out_writedata_4 = rcfg_out_writedata;
assign rcfg_out_address_5 = rcfg_out_address;
assign rcfg_out_writedata_5 = rcfg_out_writedata;
assign rcfg_out_address_6 = rcfg_out_address;
assign rcfg_out_writedata_6 = rcfg_out_writedata;
assign rcfg_out_address_7 = rcfg_out_address;
assign rcfg_out_writedata_7 = rcfg_out_writedata;
always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
if (rcfg_reset_n == 0) begin
@ -272,35 +272,35 @@ module avl_adxcfg (
assign rcfg_out_read_0 = rcfg_out_iread_0;
assign rcfg_out_write_0 = rcfg_out_iwrite_0;
assign rcfg_in_readata_0 = rcfg_in_ireadata_0;
assign rcfg_in_readdata_0 = rcfg_in_ireaddata_0;
assign rcfg_in_waitrequest_0 = rcfg_in_iwaitrequest_0;
assign rcfg_out_read_1 = rcfg_out_iread_1;
assign rcfg_out_write_1 = rcfg_out_iwrite_1;
assign rcfg_in_readata_1 = rcfg_in_ireadata_1;
assign rcfg_in_readdata_1 = rcfg_in_ireaddata_1;
assign rcfg_in_waitrequest_1 = rcfg_in_iwaitrequest_1;
assign rcfg_out_read_2 = rcfg_out_iread_2;
assign rcfg_out_write_2 = rcfg_out_iwrite_2;
assign rcfg_in_readata_2 = rcfg_in_ireadata_2;
assign rcfg_in_readdata_2 = rcfg_in_ireaddata_2;
assign rcfg_in_waitrequest_2 = rcfg_in_iwaitrequest_2;
assign rcfg_out_read_3 = rcfg_out_iread_3;
assign rcfg_out_write_3 = rcfg_out_iwrite_3;
assign rcfg_in_readata_3 = rcfg_in_ireadata_3;
assign rcfg_in_readdata_3 = rcfg_in_ireaddata_3;
assign rcfg_in_waitrequest_3 = rcfg_in_iwaitrequest_3;
assign rcfg_out_read_4 = rcfg_out_iread_4;
assign rcfg_out_write_4 = rcfg_out_iwrite_4;
assign rcfg_in_readata_4 = rcfg_in_ireadata_4;
assign rcfg_in_readdata_4 = rcfg_in_ireaddata_4;
assign rcfg_in_waitrequest_4 = rcfg_in_iwaitrequest_4;
assign rcfg_out_read_5 = rcfg_out_iread_5;
assign rcfg_out_write_5 = rcfg_out_iwrite_5;
assign rcfg_in_readata_5 = rcfg_in_ireadata_5;
assign rcfg_in_readdata_5 = rcfg_in_ireaddata_5;
assign rcfg_in_waitrequest_5 = rcfg_in_iwaitrequest_5;
assign rcfg_out_read_6 = rcfg_out_iread_6;
assign rcfg_out_write_6 = rcfg_out_iwrite_6;
assign rcfg_in_readata_6 = rcfg_in_ireadata_6;
assign rcfg_in_readdata_6 = rcfg_in_ireaddata_6;
assign rcfg_in_waitrequest_6 = rcfg_in_iwaitrequest_6;
assign rcfg_out_read_7 = rcfg_out_iread_7;
assign rcfg_out_write_7 = rcfg_out_iwrite_7;
assign rcfg_in_readata_7 = rcfg_in_ireadata_7;
assign rcfg_in_readdata_7 = rcfg_in_ireaddata_7;
assign rcfg_in_waitrequest_7 = rcfg_in_iwaitrequest_7;
always @(negedge rcfg_reset_n or posedge rcfg_clk) begin

105
library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
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@ -1,77 +1,72 @@
package require -exact qsys 14.0
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
set_module_property NAME axi_adxcvr
set_module_property DESCRIPTION "AXI ADXCVR Interface"
set_module_property NAME avl_adxcfg
set_module_property DESCRIPTION "Avalon ADXCFG Core"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_adxcvr
set_module_property DISPLAY_NAME avl_adxcfg
set_module_property ELABORATION_CALLBACK p_avl_adxcfg
# files
add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL axi_adxcvr
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file axi_adxcvr_up.v VERILOG PATH axi_adxcvr_up.v
add_fileset_file axi_adxcvr.v VERILOG PATH axi_adxcvr.v TOP_LEVEL_FILE
set_fileset_property quartus_synth TOP_LEVEL avl_adxcfg
add_fileset_file avl_adxcfg.v VERILOG PATH avl_adxcfg.v TOP_LEVEL_FILE
# parameters
add_parameter ID INTEGER 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter NUM_OF_CORES INTEGER 0
set_parameter_property NUM_OF_CORES DISPLAY_NAME NUM_OF_CORES
set_parameter_property NUM_OF_CORES TYPE INTEGER
set_parameter_property NUM_OF_CORES UNITS None
set_parameter_property NUM_OF_CORES HDL_PARAMETER false
add_parameter TX_OR_RX_N INTEGER 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME TX_OR_RX_N
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
# reconfiguration interfaces
# axi4 slave interface
add_interface rcfg_clk clock sink
add_interface_port rcfg_clk rcfg_clk clk Input 1
add_interface s_axi_clock clock end
add_interface_port s_axi_clock s_axi_aclk clk Input 1
add_interface rcfg_reset_n reset end
set_interface_property rcfg_reset_n associatedClock rcfg_clk
add_interface_port rcfg_reset_n rcfg_reset_n reset_n Input 1
add_interface s_axi_reset reset end
set_interface_property s_axi_reset associatedClock s_axi_clock
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
proc p_avl_adxcfg {} {
add_interface s_axi axi4lite end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
add_interface_port s_axi s_axi_wstrb wstrb Input 4
add_interface_port s_axi s_axi_wready wready Output 1
add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
set m_num_of_cores [get_parameter_value NUM_OF_CORES]
# xcvr interface
if {$m_num_of_cores > 8} {
set m_num_of_cores 8
}
add_interface if_xcvr conduit end
add_interface_port if_xcvr up_rst up_rst Output 1
add_interface_port if_xcvr up_ref_pll_locked up_ref_pll_locked Input 1
add_interface_port if_xcvr up_pll_locked up_pll_locked Input 1
add_interface_port if_xcvr up_ready up_ready Input 1
for {set n 0} {$n < $m_num_of_cores} {incr n} {
set_interface_property if_xcvr associatedClock s_axi_clock
add_interface rcfg_s${n} avalon slave
add_interface rcfg_m${n} avalon master
add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1
add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1
add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input 12
add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32
add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32
add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1
add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1
add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1
add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output 12
add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32
add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32
add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1
set_interface_property rcfg_s${n} associatedClock rcfg_clk
set_interface_property rcfg_s${n} associatedReset rcfg_reset_n
set_interface_property rcfg_s${n} addressUnits WORDS
set_interface_property rcfg_s${n} burstCountUnits WORDS
set_interface_property rcfg_s${n} explicitAddressSpan 0
set_interface_property rcfg_m${n} associatedClock rcfg_clk
set_interface_property rcfg_m${n} associatedReset rcfg_reset_n
set_interface_property rcfg_m${n} addressUnits WORDS
set_interface_property rcfg_m${n} burstCountUnits WORDS
}
}