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ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine 

Memory requirements are the same as with the dacfifo (1 MiB).

Signed-off-by: David Winter <david.winter@analog.com>
main
David Winter 2021-04-19 13:58:32 +02:00 committed by Mihaita Nagy
parent 6516b09a31
commit 2178191610
3 changed files with 32 additions and 30 deletions
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46
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
View File

@ -12,6 +12,8 @@
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices # [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
# #
source ../../common/xilinx/data_offload_bd.tcl
# Common parameter for TX and RX # Common parameter for TX and RX
set JESD_MODE $ad_project_params(JESD_MODE) set JESD_MODE $ad_project_params(JESD_MODE)
set RX_LANE_RATE $ad_project_params(RX_LANE_RATE) set RX_LANE_RATE $ad_project_params(RX_LANE_RATE)
@ -100,7 +102,7 @@ set adc_data_width [expr $RX_DMA_SAMPLE_WIDTH*$RX_NUM_OF_CONVERTERS*$RX_SAMPLES_
set adc_dma_data_width $adc_data_width set adc_dma_data_width $adc_data_width
set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))] set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))]
set dac_fifo_name mxfe_dac_fifo set dac_data_offload_name mxfe_tx_data_offload
set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_PER_CHANNEL] set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_PER_CHANNEL]
set dac_dma_data_width $dac_data_width set dac_dma_data_width $dac_data_width
set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))] set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))]
@ -195,7 +197,15 @@ ad_ip_instance util_upack2 util_mxfe_upack [list \
SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \ SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \
] ]
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width set data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width]
ad_data_offload_create $dac_data_offload_name \
1 \
0 \
$data_offload_size \
$dac_data_width \
$dac_data_width
ad_connect $dac_data_offload_name/sync_ext GND
ad_ip_instance axi_dmac axi_mxfe_tx_dma ad_ip_instance axi_dmac axi_mxfe_tx_dma
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_TYPE_SRC 0 ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_TYPE_SRC 0
@ -244,23 +254,25 @@ ad_connect rx_device_clk mxfe_adc_fifo/adc_clk
ad_connect tx_device_clk tx_mxfe_tpl_core/link_clk ad_connect tx_device_clk tx_mxfe_tpl_core/link_clk
ad_connect tx_device_clk util_mxfe_upack/clk ad_connect tx_device_clk util_mxfe_upack/clk
ad_connect tx_device_clk mxfe_dac_fifo/dac_clk ad_connect tx_device_clk $dac_data_offload_name/m_axis_aclk
# dma clock domain # Clocks
ad_connect $sys_cpu_clk mxfe_adc_fifo/dma_clk ad_connect $sys_cpu_clk mxfe_adc_fifo/dma_clk
ad_connect $sys_dma_clk mxfe_dac_fifo/dma_clk ad_connect $sys_dma_clk $dac_data_offload_name/s_axis_aclk
ad_connect $sys_cpu_clk axi_mxfe_rx_dma/s_axis_aclk ad_connect $sys_cpu_clk axi_mxfe_rx_dma/s_axis_aclk
ad_connect $sys_dma_clk axi_mxfe_tx_dma/m_axis_aclk ad_connect $sys_dma_clk axi_mxfe_tx_dma/m_axis_aclk
ad_connect $sys_cpu_clk $dac_data_offload_name/s_axi_aclk
# connect resets # Resets
ad_connect rx_device_clk_rstgen/peripheral_reset mxfe_adc_fifo/adc_rst ad_connect rx_device_clk_rstgen/peripheral_reset mxfe_adc_fifo/adc_rst
ad_connect tx_device_clk_rstgen/peripheral_reset mxfe_dac_fifo/dac_rst ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn
ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn
ad_connect rx_device_clk_rstgen/peripheral_reset util_mxfe_cpack/reset ad_connect rx_device_clk_rstgen/peripheral_reset util_mxfe_cpack/reset
ad_connect tx_device_clk_rstgen/peripheral_reset util_mxfe_upack/reset ad_connect tx_device_clk_rstgen/peripheral_reset util_mxfe_upack/reset
ad_connect $sys_cpu_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn ad_connect $sys_cpu_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn
ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn
ad_connect $sys_dma_reset mxfe_dac_fifo/dma_rst ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn
# #
# connect adc dataflow # connect adc dataflow
@ -299,20 +311,15 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect tx_mxfe_tpl_core/dac_enable_$i util_mxfe_upack/enable_$i ad_connect tx_mxfe_tpl_core/dac_enable_$i util_mxfe_upack/enable_$i
} }
# TODO: Add streaming AXI interface for DAC FIFO ad_connect $dac_data_offload_name/s_axis axi_mxfe_tx_dma/m_axis
ad_connect util_mxfe_upack/s_axis_valid VCC
ad_connect util_mxfe_upack/s_axis_ready mxfe_dac_fifo/dac_valid
ad_connect util_mxfe_upack/s_axis_data mxfe_dac_fifo/dac_data
ad_connect mxfe_dac_fifo/dma_valid axi_mxfe_tx_dma/m_axis_valid ad_connect util_mxfe_upack/s_axis $dac_data_offload_name/m_axis
ad_connect mxfe_dac_fifo/dma_data axi_mxfe_tx_dma/m_axis_data ad_connect util_mxfe_upack/s_axis_valid VCC
ad_connect mxfe_dac_fifo/dma_ready axi_mxfe_tx_dma/m_axis_ready
ad_connect mxfe_dac_fifo/dma_xfer_req axi_mxfe_tx_dma/m_axis_xfer_req ad_connect $dac_data_offload_name/init_req axi_mxfe_tx_dma/m_axis_xfer_req
ad_connect mxfe_dac_fifo/dma_xfer_last axi_mxfe_tx_dma/m_axis_last ad_connect tx_mxfe_tpl_core/dac_dunf GND
ad_connect mxfe_dac_fifo/dac_dunf tx_mxfe_tpl_core/dac_dunf
create_bd_port -dir I dac_fifo_bypass create_bd_port -dir I dac_fifo_bypass
ad_connect mxfe_dac_fifo/bypass dac_fifo_bypass
# interconnect (cpu) # interconnect (cpu)
ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr
@ -323,6 +330,7 @@ ad_cpu_interconnect 0x44a90000 axi_mxfe_rx_jesd
ad_cpu_interconnect 0x44b90000 axi_mxfe_tx_jesd ad_cpu_interconnect 0x44b90000 axi_mxfe_tx_jesd
ad_cpu_interconnect 0x7c420000 axi_mxfe_rx_dma ad_cpu_interconnect 0x7c420000 axi_mxfe_rx_dma
ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma
ad_cpu_interconnect 0x7c440000 $dac_data_offload_name
# interconnect (gt/adc) # interconnect (gt/adc)

2
projects/ad9081_fmca_ebz/zcu102/Makefile
View File

@ -12,6 +12,7 @@ M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v M_DEPS += ../../../library/common/ad_3w_spi.v
@ -31,5 +32,6 @@ LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2 LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr LIB_DEPS += xilinx/util_adxcvr
LIB_DEPS += data_offload
include ../../scripts/project-xilinx.mk include ../../scripts/project-xilinx.mk

14
projects/common/xilinx/data_offload_bd.tcl
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@ -26,8 +26,8 @@ proc ad_data_offload_create {instance_name datapath_type mem_type mem_size sourc
create_bd_pin -dir O init_ack create_bd_pin -dir O init_ack
create_bd_pin -dir I sync_ext create_bd_pin -dir I sync_ext
set source_max_address [expr ($mem_size * 8) / $source_dwidth] set source_addresses [expr ($mem_size * 8) / $source_dwidth]
set source_awidth [log2 $source_max_address] set source_awidth [log2 $source_addresses]
set destination_max_address [expr ($mem_size * 8) / $destination_dwidth] set destination_max_address [expr ($mem_size * 8) / $destination_dwidth]
set destination_awidth [log2 $destination_max_address] set destination_awidth [log2 $destination_max_address]
@ -133,13 +133,5 @@ proc ad_data_offload_create {instance_name datapath_type mem_type mem_size sourc
} }
proc log2 {x} { proc log2 {x} {
if {$x <= 0} {error "log2 requires a positive argument"} return [tcl::mathfunc::int [tcl::mathfunc::ceil [expr [tcl::mathfunc::log $x] / [tcl::mathfunc::log 2]]]]
if {$x < 2} {
return $x
} else {
for {set i 0} {$x > 0} {incr i} {
set x [expr $x >> 1]
}
return $i
}
} }