ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine
Memory requirements are the same as with the dacfifo (1 MiB). Signed-off-by: David Winter <david.winter@analog.com>main
David Winter
Mihaita Nagy
parent
6516b09a31
commit
2178191610
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@ -12,6 +12,8 @@
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# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
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#
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source ../../common/xilinx/data_offload_bd.tcl
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# Common parameter for TX and RX
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set JESD_MODE $ad_project_params(JESD_MODE)
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set RX_LANE_RATE $ad_project_params(RX_LANE_RATE)
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@ -100,7 +102,7 @@ set adc_data_width [expr $RX_DMA_SAMPLE_WIDTH*$RX_NUM_OF_CONVERTERS*$RX_SAMPLES_
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set adc_dma_data_width $adc_data_width
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set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))]
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set dac_fifo_name mxfe_dac_fifo
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set dac_data_offload_name mxfe_tx_data_offload
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set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_PER_CHANNEL]
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set dac_dma_data_width $dac_data_width
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set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))]
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@ -195,7 +197,15 @@ ad_ip_instance util_upack2 util_mxfe_upack [list \
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SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \
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]
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
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set data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width]
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ad_data_offload_create $dac_data_offload_name \
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1 \
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0 \
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$data_offload_size \
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$dac_data_width \
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$dac_data_width
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ad_connect $dac_data_offload_name/sync_ext GND
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ad_ip_instance axi_dmac axi_mxfe_tx_dma
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ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_TYPE_SRC 0
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@ -244,23 +254,25 @@ ad_connect rx_device_clk mxfe_adc_fifo/adc_clk
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ad_connect tx_device_clk tx_mxfe_tpl_core/link_clk
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ad_connect tx_device_clk util_mxfe_upack/clk
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ad_connect tx_device_clk mxfe_dac_fifo/dac_clk
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ad_connect tx_device_clk $dac_data_offload_name/m_axis_aclk
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# dma clock domain
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# Clocks
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ad_connect $sys_cpu_clk mxfe_adc_fifo/dma_clk
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ad_connect $sys_dma_clk mxfe_dac_fifo/dma_clk
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ad_connect $sys_dma_clk $dac_data_offload_name/s_axis_aclk
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ad_connect $sys_cpu_clk axi_mxfe_rx_dma/s_axis_aclk
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ad_connect $sys_dma_clk axi_mxfe_tx_dma/m_axis_aclk
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ad_connect $sys_cpu_clk $dac_data_offload_name/s_axi_aclk
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# connect resets
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# Resets
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ad_connect rx_device_clk_rstgen/peripheral_reset mxfe_adc_fifo/adc_rst
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ad_connect tx_device_clk_rstgen/peripheral_reset mxfe_dac_fifo/dac_rst
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ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn
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ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn
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ad_connect rx_device_clk_rstgen/peripheral_reset util_mxfe_cpack/reset
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ad_connect tx_device_clk_rstgen/peripheral_reset util_mxfe_upack/reset
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ad_connect $sys_cpu_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn
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ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn
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ad_connect $sys_dma_reset mxfe_dac_fifo/dma_rst
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ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn
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#
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# connect adc dataflow
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@ -299,20 +311,15 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect tx_mxfe_tpl_core/dac_enable_$i util_mxfe_upack/enable_$i
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}
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# TODO: Add streaming AXI interface for DAC FIFO
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ad_connect util_mxfe_upack/s_axis_valid VCC
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ad_connect util_mxfe_upack/s_axis_ready mxfe_dac_fifo/dac_valid
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ad_connect util_mxfe_upack/s_axis_data mxfe_dac_fifo/dac_data
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ad_connect $dac_data_offload_name/s_axis axi_mxfe_tx_dma/m_axis
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ad_connect mxfe_dac_fifo/dma_valid axi_mxfe_tx_dma/m_axis_valid
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ad_connect mxfe_dac_fifo/dma_data axi_mxfe_tx_dma/m_axis_data
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ad_connect mxfe_dac_fifo/dma_ready axi_mxfe_tx_dma/m_axis_ready
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ad_connect mxfe_dac_fifo/dma_xfer_req axi_mxfe_tx_dma/m_axis_xfer_req
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ad_connect mxfe_dac_fifo/dma_xfer_last axi_mxfe_tx_dma/m_axis_last
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ad_connect mxfe_dac_fifo/dac_dunf tx_mxfe_tpl_core/dac_dunf
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ad_connect util_mxfe_upack/s_axis $dac_data_offload_name/m_axis
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ad_connect util_mxfe_upack/s_axis_valid VCC
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ad_connect $dac_data_offload_name/init_req axi_mxfe_tx_dma/m_axis_xfer_req
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ad_connect tx_mxfe_tpl_core/dac_dunf GND
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create_bd_port -dir I dac_fifo_bypass
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ad_connect mxfe_dac_fifo/bypass dac_fifo_bypass
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# interconnect (cpu)
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ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr
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@ -323,6 +330,7 @@ ad_cpu_interconnect 0x44a90000 axi_mxfe_rx_jesd
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ad_cpu_interconnect 0x44b90000 axi_mxfe_tx_jesd
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ad_cpu_interconnect 0x7c420000 axi_mxfe_rx_dma
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ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma
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ad_cpu_interconnect 0x7c440000 $dac_data_offload_name
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# interconnect (gt/adc)
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@ -12,6 +12,7 @@ M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
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M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
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M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
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M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
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M_DEPS += ../../common/xilinx/data_offload_bd.tcl
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M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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M_DEPS += ../../../library/common/ad_3w_spi.v
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@ -31,5 +32,6 @@ LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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LIB_DEPS += data_offload
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include ../../scripts/project-xilinx.mk
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@ -26,8 +26,8 @@ proc ad_data_offload_create {instance_name datapath_type mem_type mem_size sourc
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create_bd_pin -dir O init_ack
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create_bd_pin -dir I sync_ext
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set source_max_address [expr ($mem_size * 8) / $source_dwidth]
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set source_awidth [log2 $source_max_address]
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set source_addresses [expr ($mem_size * 8) / $source_dwidth]
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set source_awidth [log2 $source_addresses]
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set destination_max_address [expr ($mem_size * 8) / $destination_dwidth]
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set destination_awidth [log2 $destination_max_address]
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@ -133,13 +133,5 @@ proc ad_data_offload_create {instance_name datapath_type mem_type mem_size sourc
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}
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proc log2 {x} {
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if {$x <= 0} {error "log2 requires a positive argument"}
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if {$x < 2} {
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return $x
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} else {
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for {set i 0} {$x > 0} {incr i} {
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set x [expr $x >> 1]
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}
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return $i
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}
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return [tcl::mathfunc::int [tcl::mathfunc::ceil [expr [tcl::mathfunc::log $x] / [tcl::mathfunc::log 2]]]]
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}
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