zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

motor_control: Initial commit

main
Adrian Costina 2014-04-18 18:57:18 +03:00
parent 503096de18
commit 213e852e11
21 changed files with 4118 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

207
library/axi_mc_current_monitor/ad7401.v Executable file
View File

@ -0,0 +1,207 @@
// -----------------------------------------------------------------------------
//
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : AD7401.v
// MODULE NAME : AD7401
// AUTHOR : Adrian Costina
// AUTHOR'S EMAIL : adrian.costina@analog.com
// -----------------------------------------------------------------------------
// KEYWORDS : Analog Devices, Motor Control, AD7401
// -----------------------------------------------------------------------------
// PURPOSE : Driver for
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy : Active high reset signal
// Clock Domains : fpga_clk_i, 100 MHz
// adc_clk_i, up to 20 MHz
// Critical Timing : N/A
// Test Features : N/A
// Asynchronous I/F : N/A
// Instantiations : N/A
// Synthesizable (y/n) : Y
// Target Device :
// Other :
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
`timescale 1 ns / 100 ps //Use a timescale that is best for simulation.
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module ad7401
//----------- Ports Declarations -----------------------------------------------
(
//clock and reset signals
input fpga_clk_i, // system clock
input adc_clk_i, // up to 20 MHZ clock
input reset_i, // active high reset signal
//IP control and data interface
output reg [15:0] data_o, // data read from the ADC
output reg data_rd_ready_o, // when set to high the data read from the ADC is available on the data_o bus
output reg adc_status_o,
//AD7401 control and data interface
input adc_mdata_i, // AD7401 MDAT pin
output adc_mclkin_o // AD7401 MCLKIN pin
);
//------------------------------------------------------------------------------
//----------- Wire Declarations ------------------------------------------------
//------------------------------------------------------------------------------
wire data_rdy_s;
wire [15:0] data_s ;
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
//State machine
reg [4:0] present_state;
reg [4:0] next_state;
reg [15:0] complemented_data_s;
reg data_rdy_s_d1;
reg data_rdy_s_d2;
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
//States
localparam WAIT_DATA_RDY_HIGH_STATE = 5'b00001;
localparam ACQUIRE_DATA_STATE = 5'b00010;
localparam COMPLEMENT_DATA = 5'b00100;
localparam TRANSFER_DATA_STATE = 5'b01000;
localparam WAIT_DATA_RDY_LOW_STATE = 5'b10000;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign adc_mclkin_o = adc_clk_i; // use clock signal for driver and for ADC
// synchronize data on fpga_clki
always @(posedge fpga_clk_i )
begin
data_rdy_s_d1 <= data_rdy_s;
data_rdy_s_d2 <= data_rdy_s_d1;
end
always @(posedge fpga_clk_i)
begin
if(reset_i == 1'b1)
begin
present_state <= WAIT_DATA_RDY_HIGH_STATE;
adc_status_o <= 1'b0;
end
else
begin
present_state <= next_state;
case (present_state)
WAIT_DATA_RDY_HIGH_STATE:
begin
data_rd_ready_o <= 1'b0;
end
COMPLEMENT_DATA:
begin
complemented_data_s <= ~data_s + 1;
data_rd_ready_o <= 1'b0;
end
ACQUIRE_DATA_STATE: // Acquire data from the filter
begin
data_o <= complemented_data_s;
data_rd_ready_o <= 1'b0;
adc_status_o <= 1'b1;
end
TRANSFER_DATA_STATE: // Transfer data to the upper module to write in memory
begin
data_rd_ready_o <= 1'b1;
end
WAIT_DATA_RDY_LOW_STATE:
begin
data_rd_ready_o <= 1'b0;
end
endcase
end
end
always @(present_state, data_rdy_s_d2 )
begin
next_state <= present_state;
case (present_state)
WAIT_DATA_RDY_HIGH_STATE:
begin
if(data_rdy_s_d2 == 1'b1)
begin
next_state <= COMPLEMENT_DATA;
end
end
COMPLEMENT_DATA:
begin
next_state <= ACQUIRE_DATA_STATE;
end
ACQUIRE_DATA_STATE:
begin
next_state <= TRANSFER_DATA_STATE;
end
TRANSFER_DATA_STATE:
begin
next_state <= WAIT_DATA_RDY_LOW_STATE;
end
WAIT_DATA_RDY_LOW_STATE:
begin
if(data_rdy_s_d2 == 1'b0)
begin
next_state <= WAIT_DATA_RDY_HIGH_STATE;
end
end
default:
begin
next_state <= WAIT_DATA_RDY_HIGH_STATE;
end
endcase
end
dec256sinc24b filter(
.mclkout_i(adc_clk_i),
.reset_i(reset_i),
.mdata_i(adc_mdata_i),
.data_rdy_o(data_rdy_s),
.data_o(data_s));
endmodule

799
library/axi_mc_current_monitor/axi_mc_current_monitor.v Executable file
View File

@ -0,0 +1,799 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_mc_current_monitor
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000
)
(
// physical interface
input adc_ia_dat_i,
output adc_ia_clk_o,
input adc_ib_dat_i,
output adc_ib_clk_o,
input adc_it_dat_i,
output adc_it_clk_o,
input adc_vbus_dat_i,
output adc_vbus_clk_o,
input ref_clk,
output [15:0] ia_o,
output [15:0] ib_o,
output [15:0] it_o,
output i_ready_o,
// dma interface
output adc_clk_o,
output adc_dwr_o,
output [63:0] adc_ddata_o,
output adc_dsync_o,
input adc_dovf_i,
input adc_dunf_i,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
// debug signals
output adc_mon_valid,
output [31:0] adc_mon_data
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg adc_valid = 'd0;
reg [63:0] adc_data = 'd0;
reg [47:0] adc_data_3 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg [1:0] adc_data_cnt = 'd0;
reg [9:0] adc_clk_cnt = 'd0; // used to generate 10 MHz clock for ADCs
reg adc_clk_reg = 'd0; // used to generate 10 MHz clock for ADCs
reg acq_run_reg = 'd0; // register used for synchronizing data acquisition
reg adc_valid_3 = 'd0;
reg [47:0] adc_data_3_1110 = 'd0;
reg [47:0] adc_data_3_1101 = 'd0;
reg [47:0] adc_data_3_1011 = 'd0;
reg [47:0] adc_data_3_0111 = 'd0;
reg [63:0] adc_data_1110 = 'd0;
reg [63:0] adc_data_1101 = 'd0;
reg [63:0] adc_data_1011 = 'd0;
reg [63:0] adc_data_0111 = 'd0;
reg adc_dsync_r_3 = 'd0;
reg adc_dsync_r = 'd0;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire [31:0] up_rdata_0_s;
wire [31:0] up_rdata_1_s;
wire [31:0] up_rdata_2_s;
wire [31:0] up_rdata_3_s;
wire up_ack_0_s;
wire up_ack_1_s;
wire up_ack_2_s;
wire up_ack_3_s;
wire adc_status_a_s;
wire [15:0] adc_data_ia_s ;
wire data_rd_ready_ia_s;
wire adc_status_b_s;
wire [15:0] adc_data_ib_s;
wire adc_status_it_s;
wire [15:0] adc_data_it_s;
wire [15:0] adc_data_it_n_s;
wire adc_status_vbus_s;
wire [15:0] adc_data_vbus_s ;
wire adc_enable_ia;
wire adc_enable_ib;
wire adc_enable_it;
wire adc_enable_vbus;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ref_clk; // use reference clock to send data to the dma
assign adc_dwr_o = adc_valid;
assign adc_ddata_o = adc_data;
assign adc_dsync_o = adc_dsync_r;
// monitor signals
assign adc_mon_valid = data_rd_ready_ia_s;
assign adc_mon_data[15: 0] = adc_data[15:0];
assign adc_mon_data[31:16] = {adc_enable_vbus, adc_enable_it, adc_enable_ib, adc_enable_ia, adc_rst, data_rd_ready_ia_s, adc_data_cnt, adc_ia_clk_o, adc_data_ia_s[6:0]};
// current outputs
assign i_ready_o = data_rd_ready_ia_s;
assign ia_o = adc_data_ia_s;
assign ib_o = adc_data_ib_s;
assign it_o = adc_data_it_n_s;
assign adc_data_it_n_s = 65535 - adc_data_it_s;
// adc clock
assign adc_clk_s = adc_clk_reg;
// ADC clock generation
always @(posedge ref_clk)
begin
if(adc_clk_cnt < 10'd4)
begin
adc_clk_cnt <= adc_clk_cnt + 1;
end
else
begin
adc_clk_cnt <= 10'd0;
adc_clk_reg <= ~adc_clk_reg;
end
end
// adc channels - dma interface
always @(posedge ref_clk)
begin
if(data_rd_ready_ia_s == 1'b1)
begin
adc_valid_3 <= adc_data_cnt[0] | adc_data_cnt[1];
adc_dsync_r_3 <= adc_data_cnt[0] | ~adc_data_cnt[1];
adc_data_3_1110[47:32] <= adc_data_vbus_s;
adc_data_3_1110[31:16] <= adc_data_it_n_s;
adc_data_3_1110[15:0] <= adc_data_ib_s;
adc_data_3_1101[47:32] <= adc_data_vbus_s;
adc_data_3_1101[31:16] <= adc_data_it_n_s;
adc_data_3_1101[15:0] <= adc_data_ia_s;
adc_data_3_1011[47:32] <= adc_data_vbus_s;
adc_data_3_1011[31:16] <= adc_data_ib_s;
adc_data_3_1011[15:0] <= adc_data_ia_s;
adc_data_3_0111[47:32] <= adc_data_it_n_s;
adc_data_3_0111[31:16] <= adc_data_ib_s;
adc_data_3_0111[15:0] <= adc_data_ia_s;
case(adc_data_cnt)
2'b11:
begin
adc_data_1110[63:48] <= adc_data_vbus_s;
adc_data_1110[47:32] <= adc_data_it_n_s;
adc_data_1110[31:16] <= adc_data_ib_s;
adc_data_1110[15:0] <= adc_data_3_1110[47:32];
adc_data_1101[63:48] <= adc_data_vbus_s;
adc_data_1101[47:32] <= adc_data_it_n_s;
adc_data_1101[31:16] <= adc_data_ia_s;
adc_data_1101[15:0] <= adc_data_3_1101[47:32];
adc_data_1011[63:48] <= adc_data_vbus_s;
adc_data_1011[47:32] <= adc_data_ib_s;
adc_data_1011[31:16] <= adc_data_ia_s;
adc_data_1011[15:0] <= adc_data_3_1011[47:32];
adc_data_0111[63:48] <= adc_data_it_n_s;
adc_data_0111[47:32] <= adc_data_ib_s;
adc_data_0111[31:16] <= adc_data_ia_s;
adc_data_0111[15:0] <= adc_data_3_0111[47:32];
end
2'b10:
begin
adc_data_1110[63:48] <= adc_data_it_n_s;
adc_data_1110[47:32] <= adc_data_ib_s;
adc_data_1110[31:16] <= adc_data_3_1110[47:32];
adc_data_1110[15:0] <= adc_data_3_1110[31:16];
adc_data_1101[63:48] <= adc_data_it_n_s;
adc_data_1101[47:32] <= adc_data_ia_s;
adc_data_1101[31:16] <= adc_data_3_1101[47:32];
adc_data_1101[15:0] <= adc_data_3_1101[31:16];
adc_data_1011[63:48] <= adc_data_ib_s;
adc_data_1011[47:32] <= adc_data_ia_s;
adc_data_1011[31:16] <= adc_data_3_1011[47:32];
adc_data_1011[15:0] <= adc_data_3_1011[31:16];
adc_data_0111[63:48] <= adc_data_ib_s;
adc_data_0111[47:32] <= adc_data_ia_s;
adc_data_0111[31:16] <= adc_data_3_0111[47:32];
adc_data_0111[15:0] <= adc_data_3_0111[31:16];
end
2'b01:
begin
adc_data_1110[63:48] <= adc_data_ib_s;
adc_data_1110[47:32] <= adc_data_3_1110[47:32];
adc_data_1110[31:16] <= adc_data_3_1110[31:16];
adc_data_1110[15:0] <= adc_data_3_1110[15:0];
adc_data_1101[63:48] <= adc_data_ia_s;
adc_data_1101[47:32] <= adc_data_3_1101[47:32];
adc_data_1101[31:16] <= adc_data_3_1101[31:16];
adc_data_1101[15:0] <= adc_data_3_1101[15:0];
adc_data_1011[63:48] <= adc_data_ia_s;
adc_data_1011[47:32] <= adc_data_3_1011[47:32];
adc_data_1011[31:16] <= adc_data_3_1011[31:16];
adc_data_1011[15:0] <= adc_data_3_1011[15:0];
adc_data_0111[63:48] <= adc_data_ia_s;
adc_data_0111[47:32] <= adc_data_3_0111[47:32];
adc_data_0111[31:16] <= adc_data_3_0111[31:16];
adc_data_0111[15:0] <= adc_data_3_0111[15:0];
end
2'b00:
begin
adc_data_1110[63:48] <= 16'hdead;
adc_data_1110[47:32] <= 16'hdead;
adc_data_1110[31:16] <= 16'hdead;
adc_data_1110[15:0] <= 16'hdead;
adc_data_1101[63:48] <= 16'hdead;
adc_data_1101[47:32] <= 16'hdead;
adc_data_1101[31:16] <= 16'hdead;
adc_data_1101[15:0] <= 16'hdead;
adc_data_1011[63:48] <= 16'hdead;
adc_data_1011[47:32] <= 16'hdead;
adc_data_1011[31:16] <= 16'hdead;
adc_data_1011[15:0] <= 16'hdead;
adc_data_0111[63:48] <= 16'hdead;
adc_data_0111[47:32] <= 16'hdead;
adc_data_0111[31:16] <= 16'hdead;
adc_data_0111[15:0] <= 16'hdead;
end
endcase
end
end
always @(posedge ref_clk)
begin
if(data_rd_ready_ia_s == 1'b1)
begin
case({adc_enable_vbus, adc_enable_it, adc_enable_ib, adc_enable_ia})
4'b1111:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= 1'b1;
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data_it_n_s;
adc_data[31:16] <= adc_data_ib_s;
adc_data[15: 0] <= adc_data_ia_s;
end
4'b1110:
begin
adc_dsync_r <= adc_dsync_r_3;
adc_valid <= adc_valid_3;
adc_data <= adc_data_1110;
end
4'b1101:
begin
adc_dsync_r <= adc_dsync_r_3;
adc_valid <= adc_valid_3;
adc_data <= adc_data_1101;
end
4'b1100:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data_it_n_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1011:
begin
adc_dsync_r <= adc_dsync_r_3;
adc_valid <= adc_valid_3;
adc_data <= adc_data_1011;
end
4'b1010:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data_ib_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1001:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data_ia_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1000:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0111:
begin
adc_dsync_r <= adc_dsync_r_3;
adc_valid <= adc_valid_3;
adc_data <= adc_data_0111;
end
4'b0110:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_it_n_s;
adc_data[47:32] <= adc_data_ib_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b0101:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_it_n_s;
adc_data[47:32] <= adc_data_ia_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b0100:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= adc_data_it_n_s;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0011:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_ib_s;
adc_data[47:32] <= adc_data_ia_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b0010:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= adc_data_ib_s;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0001:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= adc_data_ia_s;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
default:
begin
adc_dsync_r <= 1'b0;
adc_data_3 <= 48'd0;
adc_valid <= 1'b1;
adc_data[63:48] <= 16'hdead;
adc_data[47:32] <= 16'hdead;
adc_data[31:16] <= 16'hdead;
adc_data[15: 0] <= 16'hdead;
end
endcase
adc_data_cnt <= adc_data_cnt + 2'b1;
end
else
begin
adc_valid <= 1'b0;
adc_data <= adc_data;
adc_data_cnt <= adc_data_cnt;
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk)
begin
if(up_rstn == 0)
begin
up_rdata <= 'd0;
up_ack <= 'd0;
end
else
begin
up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s ;
up_ack <= up_adc_common_ack_s | up_ack_0_s | up_ack_1_s | up_ack_2_s | up_ack_3_s ;
end
end
// adc interfaces
ad7401 ia_if(
.fpga_clk_i(ref_clk),
.adc_clk_i(adc_clk_s),
.reset_i(adc_rst),
.adc_status_o(adc_status_a_s),
.data_o(adc_data_ia_s),
.data_rd_ready_o(data_rd_ready_ia_s),
.adc_mdata_i(adc_ia_dat_i),
.adc_mclkin_o(adc_ia_clk_o));
ad7401 ib_if(
.fpga_clk_i(ref_clk),
.adc_clk_i(adc_clk_s),
.reset_i(adc_rst),
.adc_status_o(adc_status_b_s),
.data_o(adc_data_ib_s),
.data_rd_ready_o(),
.adc_mdata_i(adc_ib_dat_i),
.adc_mclkin_o(adc_ib_clk_o));
ad7401 it_if(
.fpga_clk_i(ref_clk),
.adc_clk_i(adc_clk_s),
.reset_i(adc_rst),
.adc_status_o(adc_status_it_s),
.data_o(adc_data_it_s),
.data_rd_ready_o(),
.adc_mdata_i(adc_it_dat_i),
.adc_mclkin_o(adc_it_clk_o));
ad7401 vbus_if(
.fpga_clk_i(ref_clk),
.adc_clk_i(adc_clk_s),
.reset_i(adc_rst),
.adc_status_o(adc_status_vbus_s),
.data_o(adc_data_vbus_s),
.data_rd_ready_o(),
.adc_mdata_i(adc_vbus_dat_i),
.adc_mclkin_o(adc_vbus_clk_o));
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
.adc_clk(adc_clk_s),
.adc_rst(adc_rst),
.adc_enable(adc_enable_ia),
.adc_pn_sel(),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_pn_type(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(1'b0),
.up_adc_pn_oos(1'b0),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_0_s),
.up_ack(up_ack_0_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
.adc_clk(adc_clk_s),
.adc_rst(adc_rst),
.adc_enable(adc_enable_ib),
.adc_pn_sel(),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_pn_type(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_1_s),
.up_ack(up_ack_1_s));
up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it(
.adc_clk(adc_clk_s),
.adc_rst(adc_rst),
.adc_enable(adc_enable_it),
.adc_pn_sel(),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_pn_type(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_2_s),
.up_ack(up_ack_2_s));
up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus(
.adc_clk(adc_clk_s),
.adc_rst(adc_rst),
.adc_enable(adc_enable_vbus),
.adc_pn_sel(),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_pn_type(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_3_s),
.up_ack(up_ack_3_s));
// common processor control
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(adc_clk_s),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_status_pn_err(),
.adc_status_pn_oos(),
.adc_status_or(),
.adc_status_ovf(adc_dovf_i),
.adc_status_unf(adc_dunf_i),
.adc_clk_ratio(32'd1),
.delay_clk(1'b0),
.delay_rst(),
.delay_sel(),
.delay_rwn(),
.delay_addr(),
.delay_wdata(),
.delay_rdata(5'd0),
.delay_ack_t(1'b0),
.delay_locked(1'b0),
.drp_clk(1'd0),
.drp_rst(),
.drp_sel(),
.drp_wr(),
.drp_addr(),
.drp_wdata(),
.drp_rdata(16'd0),
.drp_ready(1'b0),
.drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd0),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_adc_common_rdata_s),
.up_ack(up_adc_common_ack_s)
);
// up bus interface
up_axi #(
.PCORE_BASEADDR(C_BASEADDR),
.PCORE_HIGHADDR(C_HIGHADDR))
i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata),
.up_ack(up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

27
library/axi_mc_current_monitor/axi_mc_current_monitor_ip.tcl Executable file
View File

@ -0,0 +1,27 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_mc_current_monitor
adi_ip_files axi_mc_current_monitor [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"dec256sinc24b.v" \
"ad7401.v" \
"axi_mc_current_monitor.v" ]
adi_ip_properties axi_mc_current_monitor
ipx::save_core [ipx::current_core]

195
library/axi_mc_current_monitor/dec256sinc24b.v Executable file
View File

@ -0,0 +1,195 @@
// -----------------------------------------------------------------------------
//
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : dec256sinc24b.v
// MODULE NAME : dec256sinc24b
// -----------------------------------------------------------------------------
// KEYWORDS : sigma-delta modulator
// -----------------------------------------------------------------------------
// PURPOSE : Implements a SINC filter for a sigma-delta modulator
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Instantiations :
// Synthesizable (y/n) :
// Target Device :
// Other :
// -----------------------------------------------------------------------------
`timescale 1 ns / 100 ps //Use a timescale that is best for simulation.
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module dec256sinc24b
(
input reset_i,
input mclkout_i,
input mdata_i,
output data_rdy_o, // signals when new data is available
output reg [15:0] data_o // outputs filtered data
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [23:0] ip_data1;
reg [23:0] acc1;
reg [23:0] acc2;
reg [23:0] acc3;
reg [23:0] acc3_d1;
reg [23:0] acc3_d2;
reg [23:0] diff1;
reg [23:0] diff2;
reg [23:0] diff3;
reg [23:0] diff1_d;
reg [23:0] diff2_d;
reg [7:0] word_count;
reg word_clk;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign data_rdy_o = word_clk;
/* Perform the Sinc ACTION*/
always @(mdata_i)
begin
if(mdata_i == 0)
begin
ip_data1 <= 0;
end
else
begin
ip_data1 <= 1;
end
end
/*ACCUMULATOR (INTEGRATOR)
* Perform the accumulation (IIR) at the speed of the modulator.
* mclkout_i = modulators conversion bit rate */
always @(negedge mclkout_i or posedge reset_i)
begin
if( reset_i == 1'b1 )
begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
else
begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
end
/*DECIMATION STAGE (MCLKOUT_I/ WORD_CLK) */
always@(posedge mclkout_i or posedge reset_i )
begin
if(reset_i == 1'b1)
begin
word_count <= 0;
end
else
begin
word_count <= word_count + 1;
end
end
always @(word_count)
begin
word_clk <= word_count[7];
end
/*DIFFERENTIATOR (including decimation stage)
* Perform the differentiation stage (FIR) at a lower speed.
WORD_CLK = output word rate */
always @(posedge word_clk or posedge reset_i)
begin
if(reset_i == 1'b1)
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end
else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
end
/* Clock the Sinc output into an output register
Clocking Sinc Output into an Output Register
WORD_CLK = output word rate */
always @(posedge word_clk)
begin
data_o[15] <= diff3[23];
data_o[14] <= diff3[22];
data_o[13] <= diff3[21];
data_o[12] <= diff3[20];
data_o[11] <= diff3[19];
data_o[10] <= diff3[18];
data_o[9] <= diff3[17];
data_o[8] <= diff3[16];
data_o[7] <= diff3[15];
data_o[6] <= diff3[14];
data_o[5] <= diff3[13];
data_o[4] <= diff3[12];
data_o[3] <= diff3[11];
data_o[2] <= diff3[10];
data_o[1] <= diff3[9];
data_o[0] <= diff3[8];
end
endmodule

327
library/axi_mc_speed/axi_mc_speed.v Executable file
View File

@ -0,0 +1,327 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_mc_speed
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter MOTOR_CONTROL_REVISION = 1
)
//----------- Ports Declarations -----------------------------------------------
(
// physical interface
input [2:0] position_i,
input [2:0] bemf_i,
output [2:0] position_o,
output [31:0] speed_o,
output new_speed_o,
input [1:0] hall_bemf_i,
input ref_clk,
// dma interface
output adc_clk_o,
output adc_dwr_o,
output [31:0] adc_ddata_o,
input adc_dovf_i,
input adc_dunf_i,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
// debug signals
output adc_mon_valid,
output [31:0] adc_mon_data);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg adc_valid = 'd0;
reg [31:0] adc_data = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire adc_start_s;
wire [31:0] speed_data_s;
wire adc_enable_s;
wire adc_status_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire [31:0] pid_s;
wire [ 2:0] position_s;
wire [ 2:0] bemf_s;
wire [ 2:0] bemf_delayed_s;
wire new_speed_s;
wire [ 2:0] bemf_multiplex_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ref_clk;
assign adc_dwr_o = adc_valid;
assign adc_ddata_o = adc_data;
// monitor signals
assign adc_mon_valid = new_speed_s;
assign adc_mon_data = { 20'h0, bemf_multiplex_s, bemf_s, bemf_delayed_s, position_s };
assign bemf_multiplex_s =(MOTOR_CONTROL_REVISION == 2) ? position_i : bemf_i;
assign position_o =(hall_bemf_i == 2'b01) ? bemf_delayed_s : position_s;
assign new_speed_o = new_speed_s;
assign speed_o = speed_data_s;
// adc channels - dma interface
always @(posedge ref_clk)
begin
adc_data <= speed_data_s;
adc_valid <= new_speed_s;
end
// processor read interface
always @(negedge up_rstn or posedge up_clk)
begin
if(up_rstn == 0)
begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else
begin
up_rdata <= up_adc_common_rdata_s;
up_ack <= up_adc_common_ack_s;
end
end
// HALL sensors debouncers
debouncer
#( .DEBOUNCER_LEN(400))
position_0(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(position_i[0]),
.sig_o(position_s[0]));
debouncer
#( .DEBOUNCER_LEN(400))
position_1(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(position_i[1]),
.sig_o(position_s[1]));
debouncer
#( .DEBOUNCER_LEN(400))
position_2(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(position_i[2]),
.sig_o(position_s[2]));
// BEMF debouncer
debouncer
#( .DEBOUNCER_LEN(400))
bemf_0(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(bemf_multiplex_s[0]),
.sig_o(bemf_s[0]));
debouncer
#( .DEBOUNCER_LEN(400))
bemf_1(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(bemf_multiplex_s[1]),
.sig_o(bemf_s[1]));
debouncer
#( .DEBOUNCER_LEN(400))
bemf_2(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(bemf_multiplex_s[2]),
.sig_o(bemf_s[2]));
delay_30_degrees delay_30_degrees_i1(
.clk_i(ref_clk),
.rst_i(adc_rst),
.offset_i(32'h0),
.position_i(bemf_s),
.position_o(bemf_delayed_s));
speed_detector
#( .AVERAGE_WINDOW(1024),
.LOG_2_AW(10),
.SAMPLE_CLK_DECIM(10000))
speed_detector_inst(
.clk_i(ref_clk),
.rst_i(adc_rst),
.position_i(position_o),
.new_speed_o(new_speed_s),
.current_speed_o(),
.speed_o(speed_data_s));
// common processor control
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_status_pn_err(1'b0),
.adc_status_pn_oos(1'b0),
.adc_status_or(),
.adc_status_ovf(adc_dovf_i),
.adc_status_unf(adc_dunf_i),
.adc_clk_ratio(32'd1),
.delay_clk(1'b0),
.delay_rst(),
.delay_sel(),
.delay_rwn(),
.delay_addr(),
.delay_wdata(),
.delay_rdata(5'd0),
.delay_ack_t(1'b0),
.delay_locked(1'b0),
.drp_clk(1'd0),
.drp_rst(),
.drp_sel(),
.drp_wr(),
.drp_addr(),
.drp_wdata(),
.drp_rdata(16'd0),
.drp_ready(1'b0),
.drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd0),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_adc_common_rdata_s),
.up_ack(up_adc_common_ack_s)
);
// up bus interface
up_axi #(
.PCORE_BASEADDR(C_BASEADDR),
.PCORE_HIGHADDR(C_HIGHADDR))
i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata),
.up_ack(up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

24
library/axi_mc_speed/axi_mc_speed_ip.tcl Executable file
View File

@ -0,0 +1,24 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_mc_speed
adi_ip_files axi_mc_speed [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"debouncer.v" \
"speed_detector.v" \
"delay_30_degrees.v" \
"axi_mc_speed.v" ]
adi_ip_properties axi_mc_speed
ipx::save_core [ipx::current_core]

101
library/axi_mc_speed/debouncer.v Executable file
View File

@ -0,0 +1,101 @@
// -----------------------------------------------------------------------------
//
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : debouncer.v
// MODULE NAME : debouncer
// AUTHOR : ACozma
// AUTHOR'S EMAIL : andrei.cozma@analog.com
// -----------------------------------------------------------------------------
// KEYWORDS :
// -----------------------------------------------------------------------------
// PURPOSE : Module used for debouncing input signals
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Instantiations :
// Synthesizable (y/n) : y
// Target Device :
// Other :
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
module debouncer
//----------- Paramters Declarations -------------------------------------------
#(
parameter DEBOUNCER_LEN = 4
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input rst_i,
input sig_i,
output reg sig_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [DEBOUNCER_LEN-1:0] shift_reg;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
always @(posedge clk_i)
begin
if(rst_i == 1)
begin
shift_reg <= 0;
sig_o <= 0;
end
else
begin
shift_reg <= {shift_reg[DEBOUNCER_LEN-2:0], sig_i};
if(shift_reg == {DEBOUNCER_LEN{1'b1}})
begin
sig_o <= 1'b1;
end
else if(shift_reg == {DEBOUNCER_LEN{1'b0}})
begin
sig_o <= 1'b0;
end
end
end
endmodule

228
library/axi_mc_speed/delay_30_degrees.v Executable file
View File

@ -0,0 +1,228 @@
// -----------------------------------------------------------------------------
//
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : delay_30_degrees.v
// MODULE NAME : delay_30_degrees
// AUTHOR : ACostina
// AUTHOR'S EMAIL : adrian.costina@analog.com
// -----------------------------------------------------------------------------
// KEYWORDS : BEMF, Analog Devices, Motor Control
// -----------------------------------------------------------------------------
// PURPOSE : Module used for delaying the BEMF based position signal with 30
// degrees.
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Instantiations :
// Synthesizable (y/n) :
// Target Device :
// Other :
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
module delay_30_degrees
//----------- Paramters Declarations -------------------------------------------
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input rst_i,
input [31:0] offset_i, // offset register
input [2:0] position_i, // input position
output reg [2:0] position_o // delayed with 30 degrees position
);
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
localparam MAX_SPEED_COUNT= 32'h1000000;
//State machine
localparam RESET = 6'b000001;
localparam INIT = 6'b000010;
localparam CHANGE_POSITION = 6'b000100;
localparam DELAY_30_DEGREES = 6'b001000;
localparam APPLY_CHANGE = 6'b010000;
localparam IDLE = 6'b100000;
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [5:0] state; // current state
reg [5:0] next_state; // next state
reg [2:0] position_old; // saves the latest position
reg [31:0] speed_count; // counts the current speed of rotation
reg [31:0] speed_divider; // divides the speed of rotation by 2, correspoding to 30 degrees
reg [31:0] delay_count; // Applied the delay to the input signal
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// State transitions
always @*
begin
next_state = state;
case (state)
RESET:
begin
next_state = INIT;
end
INIT:
begin
if (position_i != position_old)
begin
next_state = CHANGE_POSITION;
end
end
CHANGE_POSITION:
begin
next_state = DELAY_30_DEGREES;
end
DELAY_30_DEGREES:
begin
if( delay_count > speed_divider)
begin
next_state = APPLY_CHANGE;
end
end
APPLY_CHANGE:
begin
next_state = IDLE;
end
IDLE:
begin
if (position_i != position_old)
begin
next_state = CHANGE_POSITION;
end
end
default:
begin
next_state = RESET;
end
endcase
end
always @(posedge clk_i)
begin
case(state)
RESET:
begin
speed_count <= 0;
speed_divider <= 0;
position_o <= 3'b1;
end
INIT:
begin
if (speed_count < MAX_SPEED_COUNT)
begin
speed_count <= speed_count + 1;
end
end
CHANGE_POSITION:
begin
speed_divider <= speed_count >> 1 ;
speed_count <= 0;
delay_count <= 0;
end
DELAY_30_DEGREES:
begin
if (speed_count < MAX_SPEED_COUNT)
begin
speed_count <= speed_count + 1;
end
delay_count <= delay_count + 1;
end
APPLY_CHANGE:
begin
if (position_i == 3'b101)
begin
position_o <= 100;
end
if (position_i == 3'b100)
begin
position_o <= 110;
end
if (position_i == 3'b110)
begin
position_o <= 010;
end
if (position_i == 3'b010)
begin
position_o <= 011;
end
if (position_i == 3'b011)
begin
position_o <= 001;
end
if (position_i == 3'b001)
begin
position_o <= 101;
end
position_old <= position_i;
if (speed_count < MAX_SPEED_COUNT)
begin
speed_count <= speed_count + 1;
end
end
IDLE:
begin
if (speed_count < MAX_SPEED_COUNT)
begin
speed_count <= speed_count + 1;
end
end
endcase
end
always @ (posedge clk_i)
begin
if(rst_i == 1'b1)
begin
state <= RESET;
end
else
begin
state <= next_state;
end
end
endmodule

262
library/axi_mc_speed/speed_detector.v Executable file
View File

@ -0,0 +1,262 @@
// -----------------------------------------------------------------------------
//
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : speed_detector.v
// MODULE NAME : speed_detector
// AUTHOR : ACostina
// AUTHOR'S EMAIL : adrian.costina@analog.com
// -----------------------------------------------------------------------------
// KEYWORDS : Analog Devices, Motor Control, Speed detector
// -----------------------------------------------------------------------------
// PURPOSE : Detects the speed of rotation of a motor
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Instantiations :
// Synthesizable (y/n) :
// Target Device :
// Other :
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
module speed_detector
//----------- Paramters Declarations -------------------------------------------
#(
parameter AVERAGE_WINDOW = 32, // Averages data on the latest samples
parameter LOG_2_AW = 5, // Average window is 2 ^ LOG_2_AW
parameter SAMPLE_CLK_DECIM = 10000
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input rst_i,
input [ 2:0] position_i, // position as determined by the sensors
output reg new_speed_o, // signals a new speed has been computed
output reg [31:0] current_speed_o, // data bus with the current speed
output reg [31:0] speed_o // data bus with the mediated speed
);
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
localparam AW = LOG_2_AW - 1;
localparam MAX_SPEED_CNT= 32'h10000;
//State machine
localparam RESET = 8'b00000001;
localparam INIT = 8'b00000010;
localparam CHANGE_POSITION = 8'b00000100;
localparam ADD_COUNTER = 8'b00001000;
localparam SUBSTRACT_MEM = 8'b00010000;
localparam UPDATE_MEM = 8'b00100000;
localparam IDLE = 8'b10000000;
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [2:0] position_old;
reg [63:0] avg_register;
reg [63:0] avg_register_stable;
reg [31:0] cnt_period;
reg [31:0] decimation; // register used to divide by ten the speed
reg [31:0] cnt_period_old;
reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM
reg [AW:0] write_addr;
reg [AW:0] read_addr;
reg [31:0] sample_clk_div;
reg [7:0] state;
reg [7:0] next_state;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// Count ticks per position
always @(posedge clk_i)
begin
if(rst_i == 1'b1)
begin
cnt_period <= 32'b0;
decimation <= 32'b0;
end
else
begin
if(state != CHANGE_POSITION)
begin
if(decimation == 9)
begin
cnt_period <= cnt_period + 1;
decimation <= 32'b0;
end
else
begin
decimation <= decimation + 1;
end
end
else
begin
decimation <= 32'b0;
cnt_period <= 32'b0;
cnt_period_old <= cnt_period;
end
end
end
always @(posedge clk_i)
begin
if(rst_i == 1'b1)
begin
state <= RESET;
end
else
begin
state <= next_state;
end
end
always @*
begin
next_state = state;
case(state)
RESET:
begin
next_state = INIT;
end
INIT:
begin
if(position_i != position_old)
begin
next_state = CHANGE_POSITION;
end
end
CHANGE_POSITION:
begin
next_state = ADD_COUNTER;
end
ADD_COUNTER:
begin
next_state = SUBSTRACT_MEM;
end
SUBSTRACT_MEM:
begin
next_state = UPDATE_MEM;
end
UPDATE_MEM:
begin
next_state = IDLE;
end
IDLE:
begin
if(position_i != position_old)
begin
next_state = CHANGE_POSITION;
end
end
endcase
end
always @(posedge clk_i)
begin
case(state)
RESET:
begin
avg_register <= MAX_SPEED_CNT;
fifo[write_addr] <= MAX_SPEED_CNT;
end
INIT:
begin
end
CHANGE_POSITION:
begin
position_old <= position_i;
end
ADD_COUNTER:
begin
avg_register <= avg_register + cnt_period_old ;
end
SUBSTRACT_MEM:
begin
avg_register <= avg_register - fifo[write_addr];
end
UPDATE_MEM:
begin
fifo[write_addr] <= cnt_period_old;
write_addr <= write_addr + 1;
avg_register_stable <= avg_register;
end
IDLE:
begin
end
endcase
end
// Stable sampling frequency of the motor speed
always @(posedge clk_i)
begin
if(rst_i == 1'b1)
begin
sample_clk_div <= 0;
speed_o <= 0;
new_speed_o <= 0;
end
else
begin
if(sample_clk_div == SAMPLE_CLK_DECIM )
begin
sample_clk_div <= 0;
speed_o <=(avg_register_stable >> LOG_2_AW);
new_speed_o <= 1;
current_speed_o <= cnt_period_old;
end
else
begin
sample_clk_div <= sample_clk_div + 1;
new_speed_o <= 0;
end
end
end
endmodule

535
library/axi_mc_torque_ctrl/axi_mc_torque_ctrl.v Executable file
View File

@ -0,0 +1,535 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_mc_torque_ctrl
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000
)
(
input ref_clk, // 100 MHz
// physical interface
input fmc_m1_fault_i,
output fmc_m1_en_o,
output pwm_ah_o,
output pwm_al_o,
output pwm_bh_o,
output pwm_bl_o,
output pwm_ch_o,
output pwm_cl_o,
output [7:0] gpo_o,
// interconnection with other modules
output [1:0] sensors_o,
input [2:0] position_i,
input new_speed_i,
input [31:0] speed_i,
input [15:0] it_i,
input i_ready_i,
// dma interface
output adc_clk_o,
output adc_dwr_o,
output [31:0] adc_ddata_o,
input adc_dovf_i,
input adc_dunf_i,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
// debug signals
output adc_mon_valid,
output [31:0] adc_mon_data
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
// internal registers
reg adc_valid = 'd0;
reg [31:0] adc_data = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg [15:0] tmr_dv_reg = 'd0;
reg datavalid_reg = 'd0;
reg [15:0] tmr_ctrl_reg = 'd0;
reg pwm_gen_clk = 'd0;
reg ctrl_gen_clk = 'd0;
reg one_chan_reg = 'd0;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire [31:0] up_control_rdata_s;
wire [31:0] rdata_ref_speed_s;
wire [31:0] rdata_actual_speed_s;
wire up_adc_common_ack_s;
wire up_control_ack_s;
wire ack_ref_speed_s;
wire ack_actual_speed_s;
wire run_s;
wire star_delta_s;
wire oloop_matlab_s; // 0 - open loop, 1 matlab controlls pwm
wire [10:0] pwm_open_s;
wire [31:0] pwm_controller_s;
wire [10:0] pwm_s;
wire [31:0] err_s;
wire [31:0] pid_s;
wire [2:0] position_s;
wire [31:0] ki_s;
wire [31:0] kp_s;
wire [31:0] ki1_s;
wire [31:0] kp1_s;
wire [31:0] kd1_s;
wire [31:0] reference_speed_s;
wire [31:0] speed_rpm_s; // speed in RPM from the controller
wire enable_ref_speed_s;
wire enable_actual_speed_s;
wire [10:0] gpo_s;
wire [31:0] it_max_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ref_clk;
assign adc_dwr_o = adc_valid;
assign adc_ddata_o = adc_data;
// monitor signals
assign adc_mon_valid = i_ready_i;
assign adc_mon_data = {25'h0 ,fmc_m1_en_o, pwm_ah_o, pwm_al_o, pwm_bh_o, pwm_bl_o, pwm_ch_o, pwm_cl_o};
// multiple instances synchronization
assign pid_s = 32'd0;
assign fmc_m1_en_o = run_s;
assign pwm_s = oloop_matlab_s ? pwm_controller_s[10:0] : pwm_open_s ;
assign position_s = position_i;
// assign gpo
assign gpo_o[7:4] = gpo_s[10:7];
assign gpo_o[3:0] = gpo_s[3:0];
// clock generation for controller
always @(posedge ref_clk)
begin
pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk
if(tmr_ctrl_reg == 16'd4) // generate 10 MHz clk
begin
tmr_ctrl_reg <= 16'd0;
ctrl_gen_clk <= ~ctrl_gen_clk;
end
else
begin
tmr_ctrl_reg <= tmr_ctrl_reg + 16'd1;
end
end
// CE generation for controller
always @(posedge ref_clk)
begin
if(tmr_dv_reg == 16'd999)
begin
datavalid_reg <= 1'b1;
tmr_dv_reg <= 16'd0;
end
else
begin
datavalid_reg <= 1'b0;
tmr_dv_reg <= tmr_dv_reg + 16'd1;
end
end
// adc channels - dma interface
always @(posedge ref_clk)
begin
if(datavalid_reg == 1)
begin
case({enable_actual_speed_s , enable_ref_speed_s})
2'b11:
begin
adc_data <= {speed_rpm_s[29:14],reference_speed_s[15:0]};
adc_valid <= 1'b1;
end
2'b01:
begin
adc_data <= { adc_data[15:0], reference_speed_s[15:0]};
one_chan_reg <= ~one_chan_reg;
if(one_chan_reg == 1'b1)
begin
adc_valid <= 1'b1;
end
else
begin
adc_valid <= 1'b0;
end
end
2'b10:
begin
adc_data <= { adc_data[15:0], speed_rpm_s[29:14]};
one_chan_reg <= ~one_chan_reg;
if(one_chan_reg == 1'b1)
begin
adc_valid <= 1'b1;
end
else
begin
adc_valid <= 1'b0;
end
end
2'b00:
begin
adc_data <= 32'hdeadbeef;
adc_valid <= 1'b1;
end
endcase
end
else
begin
adc_data <= adc_data;
adc_valid <= 1'b0;
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if(up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_ref_speed_s | rdata_actual_speed_s ;
up_ack <= up_control_ack_s | up_adc_common_ack_s | ack_ref_speed_s | ack_actual_speed_s;
end
end
// main (device interface)
motor_driver
#( .PWM_BITS(11))
motor_driver_inst(
.clk_i(ref_clk),
.pwm_clk_i(pwm_gen_clk),
.rst_n_i(up_rstn) ,
.run_i(run_s),
.star_delta_i(1'b0),
//.dir_i(1'b1),
.position_i(position_s),
.pwm_duty_i(pwm_s),
.AH_o(pwm_ah_o),
.BH_o(pwm_bh_o),
.CH_o(pwm_ch_o),
.AL_o(pwm_al_o),
.BL_o(pwm_bl_o),
.CL_o(pwm_cl_o));
control_registers control_reg_inst(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_control_rdata_s),
.up_ack(up_control_ack_s),
//control pins
.run_o(run_s),
.break_o(),
.star_delta_o(star_delta_s),
.sensors_o(sensors_o),
.kp_o(kp_s),
.ki_o(ki_s),
.kp1_o(kp1_s),
.ki1_o(ki1_s),
.kd1_o(kd1_s),
.gpo_o(gpo_s),
.reference_speed_o(reference_speed_s),
.oloop_matlab_o(oloop_matlab_s),
.err_i(err_s),
.calibrate_adcs_o(),
.pwm_open_o( pwm_open_s));
bldc_sim_fpga_cw torque_controller(
.ce(1'b1),
.clk(ctrl_gen_clk),
.clk_x0(ctrl_gen_clk),
.it({16'h0,it_i}),
.kd1(kd1_s),
.ki(ki_s),
.ki1(ki1_s),
.kp(kp_s),
.kp1(kp1_s),
.motor_speed(speed_i),
.new_current(i_ready_i),
.new_speed(new_speed_i),
.ref_speed(reference_speed_s),
.reset(!up_rstn),
.reset_acc(!run_s),
.err(err_s),
.it_max(it_max_s),
.pwm(pwm_controller_s),
.speed(speed_rpm_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel_ref_speed(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(enable_ref_speed_s),
.adc_pn_sel(),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_pn_type(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(1'b0),
.up_adc_pn_oos(1'b0),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_ref_speed_s),
.up_ack(ack_ref_speed_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel_actual_speed(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(enable_actual_speed_s),
.adc_pn_sel(),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_pn_type(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_actual_speed_s),
.up_ack(ack_actual_speed_s));
// common processor control
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_status_pn_err(),
.adc_status_pn_oos(),
.adc_status_or(),
.adc_status_ovf(adc_dovf_i),
.adc_status_unf(adc_dunf_i),
.adc_clk_ratio(32'd1),
.delay_clk(1'b0),
.delay_rst(),
.delay_sel(),
.delay_rwn(),
.delay_addr(),
.delay_wdata(),
.delay_rdata(5'd0),
.delay_ack_t(1'b0),
.delay_locked(1'b0),
.drp_clk(1'd0),
.drp_rst(),
.drp_sel(),
.drp_wr(),
.drp_addr(),
.drp_wdata(),
.drp_rdata(16'd0),
.drp_ready(1'b0),
.drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd0),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_adc_common_rdata_s),
.up_ack(up_adc_common_ack_s));
// up bus interface
up_axi #(
.PCORE_BASEADDR(C_BASEADDR),
.PCORE_HIGHADDR(C_HIGHADDR))
i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata),
.up_ack(up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

29
library/axi_mc_torque_ctrl/axi_mc_torque_ctrl_ip.tcl Executable file
View File

@ -0,0 +1,29 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_mc_torque_ctrl
adi_ip_files axi_mc_torque_ctrl [list \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"bldc_sim_fpga_cw.ngc" \
"bldc_sim_fpga_cw.xdc" \
"motor_driver.v" \
"control_registers.v" \
"bldc_sim_fpga_cw_bb.v" \
"axi_mc_torque_ctrl.v" ]
adi_ip_properties axi_mc_torque_ctrl
ipx::save_core [ipx::current_core]

3
library/axi_mc_torque_ctrl/bldc_sim_fpga_cw.ngc Executable file
View File

File diff suppressed because one or more lines are too long

4
library/axi_mc_torque_ctrl/bldc_sim_fpga_cw.xdc Executable file
View File

@ -0,0 +1,4 @@
# Global period constraint
create_clock -name clk -period 100.0 [get_ports clk]

53
library/axi_mc_torque_ctrl/bldc_sim_fpga_cw_bb.v Executable file
View File

@ -0,0 +1,53 @@
// Declare the module black box
module bldc_sim_fpga_cw (
ce ,
clk ,
clk_x0 ,
it ,
kd1 ,
ki ,
ki1 ,
kp ,
kp1 ,
motor_speed ,
new_current ,
new_speed ,
ref_speed ,
reset ,
reset_acc ,
err ,
it_max ,
pwm ,
speed
); // synthesis black_box
// Inputs
input ce;
input clk;
input clk_x0;
input [31:0] it;
input [31:0] kd1;
input [31:0] ki;
input [31:0] ki1;
input [31:0] kp;
input [31:0] kp1;
input [31:0] motor_speed;
input new_current;
input new_speed;
input [31:0] ref_speed;
input reset;
input reset_acc;
// Outputs
output [31:0] err;
output [31:0] it_max;
output [31:0] pwm;
output [31:0] speed;
//synthesis attribute box_type bldc_sim_fpga_cw "black_box"
endmodule

229
library/axi_mc_torque_ctrl/control_registers.v Executable file
View File

@ -0,0 +1,229 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module control_registers
(
//bus interface
input up_rstn,
input up_clk,
input up_sel,
input up_wr,
input [13:0] up_addr,
input [31:0] up_wdata,
output reg [31:0] up_rdata,
output reg up_ack,
//control
input [31:0] err_i,
output [31:0] pwm_open_o,
output [31:0] reference_speed_o,
output [31:0] kp_o,
output [31:0] ki_o,
output [31:0] kp1_o,
output [31:0] ki1_o,
output [31:0] kd1_o,
output run_o,
output break_o,
output star_delta_o,
output [1:0] sensors_o,
output [10:0] gpo_o,
output oloop_matlab_o,
output calibrate_adcs_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
//internal registers
reg [31:0] control_r;
reg [31:0] reference_speed_r;
reg [31:0] kp_r;
reg [31:0] ki_r;
reg [31:0] kp1_r;
reg [31:0] ki1_r;
reg [31:0] kd1_r;
reg [31:0] pwm_open_r;
reg [31:0] pwm_break_r;
reg [31:0] status_r;
reg [31:0] reserved_r1;
reg [31:0] reserved_r2;
reg [10:0] gpo_r;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
//internal signals
wire up_sel_s;
wire up_wr_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
//decode block select
assign up_sel_s = (up_addr[13:4] == 10'h00) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
assign run_o = control_r[0]; // Run the motor
assign break_o = control_r[2]; // Activate the Break circuit
assign star_delta_o = control_r[4]; // Select between star [0] or delta [1] controller
assign sensors_o = control_r[9:8]; // Select between Hall[00] and BEMF[01] sensors
assign calibrate_adcs_o = control_r[16];
assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1]
assign gpo_o = control_r[30:20];
assign pwm_open_o = pwm_open_r; // PWM value, for open loop control
assign reference_speed_o = reference_speed_r;
assign kp_o = kp_r;
assign ki_o = ki_r;
assign kp1_o = kp1_r;
assign kd1_o = kd1_r;
assign ki1_o = ki1_r;
// processor write interface
always @(negedge up_rstn or posedge up_clk)
begin
if (up_rstn == 0)
begin
control_r <= 'h0;
reference_speed_r <= 'd1000;
kp_r <= 'd35000;
ki_r <= 'd30;
kp1_r <= 'd400000;
ki1_r <= 'd250;
kd1_r <= 'd200000;
pwm_open_r <= 'h5ff;
pwm_break_r <= 'd0;
status_r <= 'd0;
end
else
begin
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h3))
begin
reserved_r1 <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h4))
begin
control_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h5))
begin
reference_speed_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h6))
begin
kp_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h7))
begin
ki_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8))
begin
reserved_r2 <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h9))
begin
kp1_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'ha))
begin
ki1_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hb))
begin
kd1_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hc))
begin
pwm_open_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hd))
begin
pwm_break_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'he))
begin
status_r <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk)
begin
if (up_rstn == 0) begin
up_ack <= 'd0;
up_rdata <= 'd0;
end
else
begin
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[3:0])
4'h3: up_rdata <= reserved_r1;
4'h4: up_rdata <= control_r;
4'h5: up_rdata <= reference_speed_r;
4'h6: up_rdata <= kp_r;
4'h7: up_rdata <= ki_r;
4'h8: up_rdata <= reserved_r2;
4'h9: up_rdata <= kp1_r;
4'ha: up_rdata <= ki1_r;
4'hb: up_rdata <= kd1_r;
4'hc: up_rdata <= pwm_open_r;
4'hd: up_rdata <= pwm_break_r;
4'he: up_rdata <= status_r;
4'hf: up_rdata <= err_i;
default: up_rdata <= 0;
endcase
end
else
begin
up_rdata <= 32'd0;
end
end
end
endmodule

272
library/axi_mc_torque_ctrl/motor_driver.v Executable file
View File

@ -0,0 +1,272 @@
// -----------------------------------------------------------------------------
//
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : motor_driver.v
// MODULE NAME :motor_driver
// AUTHOR : acozma
// AUTHOR'S EMAIL : andrei.cozma@analog.com
// -----------------------------------------------------------------------------
// SVN REVISION: $WCREV$
// -----------------------------------------------------------------------------
// KEYWORDS :
// -----------------------------------------------------------------------------
// PURPOSE : Module for driving a BLDC motor
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy : Active low reset signal
// Clock Domains :
// Critical Timing : N/A
// Test Features : N/A
// Asynchronous I/F : N/A
// Instantiations : N/A
// Synthesizable (y/n) : Y
// Target Device :
// Other :
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module motor_driver
//----------- Paramters Declarations -------------------------------------------
#(
parameter PWM_BITS = 11
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input pwm_clk_i,
input rst_n_i,
input run_i,
input star_delta_i, // 0 star configuration, 1 delta configuration
input [2:0] position_i,
input [PWM_BITS-1:0] pwm_duty_i,
output AH_o,
output BH_o,
output CH_o,
output AL_o,
output BL_o,
output CL_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [ 7:0] motor_state;
reg [ 7:0] motor_next_state;
reg [31:0] align_counter;
reg pwm_s;
reg [PWM_BITS-1:0] pwm_cnt;
reg [32:0] stall_counter;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
wire align_complete;
wire [PWM_BITS-1:0] pwm_duty_s;
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
parameter OFF = 8'b00000001;
parameter ALIGN = 8'b00000010;
parameter PHASE1 = 8'b00000100;
parameter PHASE2 = 8'b00001000;
parameter PHASE3 = 8'b00010000;
parameter PHASE4 = 8'b00100000;
parameter PHASE5 = 8'b01000000;
parameter PHASE6 = 8'b10000000;
parameter [PWM_BITS-1:0] ALIGN_PWM_DUTY = 2**(PWM_BITS-1) + 2**(PWM_BITS-4);
parameter [31:0] ALIGN_TIME = 32'h01000000;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign align_complete = align_counter < ALIGN_TIME ? 0 : 1;
assign pwm_duty_s = motor_state == OFF ? 0 :
motor_state == ALIGN ? ALIGN_PWM_DUTY : pwm_duty_i;
//Motor Phases Control
// assign AH_o = star_delta_i ? ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2 || motor_state == PHASE3) ? pwm_s : ~pwm_s ) :
// ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE6) ? ~pwm_s : (motor_state == PHASE3 || motor_state == PHASE4) ? pwm_s : 0) ;
// assign AL_o = star_delta_i ? ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2 || motor_state == PHASE3) ? ~pwm_s : pwm_s ) :
// ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE6) ? pwm_s : (motor_state == PHASE3 || motor_state == PHASE4) ? ~pwm_s : 0) ;
// assign BH_o = star_delta_i ? ( (motor_state == PHASE3 || motor_state == PHASE4 || motor_state == PHASE5 ) ? pwm_s : ~pwm_s ) :
// ( (motor_state == PHASE2 || motor_state == PHASE3) ? ~pwm_s : (motor_state == PHASE5 || motor_state == PHASE6) ? pwm_s : 0 );
// assign BL_o = star_delta_i ? ( (motor_state == PHASE3 || motor_state == PHASE4 || motor_state == PHASE5 ) ? ~pwm_s : pwm_s ) :
// ( (motor_state == PHASE2 || motor_state == PHASE3) ? pwm_s : (motor_state == PHASE5 || motor_state == PHASE6) ? ~pwm_s : 0 );
// assign CH_o = star_delta_i ? ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE5 || motor_state == PHASE6) ? pwm_s : ~pwm_s ) :
// ( (motor_state == PHASE4 || motor_state == PHASE5) ? ~pwm_s : (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2) ? pwm_s : 0 );
// assign CL_o = star_delta_i ? ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE5 || motor_state == PHASE6) ? ~pwm_s : pwm_s ) :
// ( (motor_state == PHASE4 || motor_state == PHASE5) ? pwm_s : (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2) ? ~pwm_s : 0 );
assign AH_o = ( (motor_state == PHASE3 || motor_state == PHASE4 || motor_state == PHASE5 ) ? ~pwm_s : 1 );
assign AL_o = ( (motor_state == PHASE3 || motor_state == PHASE4 || motor_state == PHASE5 ) ? pwm_s : ~pwm_s );
assign BH_o = ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE5 || motor_state == PHASE6) ? ~pwm_s : 1 );
assign BL_o = ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE5 || motor_state == PHASE6) ? pwm_s : ~pwm_s );
assign CH_o = ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2 || motor_state == PHASE3) ? ~pwm_s : 1 );
assign CL_o = ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2 || motor_state == PHASE3) ? pwm_s : ~pwm_s );
//Control the current motor state
always @(posedge clk_i)
begin
if(rst_n_i == 1'b0)
begin
motor_state <= OFF;
align_counter <= 0;
end
else
begin
motor_state <= (run_i == 1'b1 ? motor_next_state : OFF);
align_counter <= motor_state == ALIGN ? align_counter + 1 : 0;
end
end
//Determine the next motor state
always @(motor_state, position_i, align_complete,run_i, stall_counter)
begin
motor_next_state <= motor_state;
case(motor_state)
OFF:
begin
if(run_i == 1'b1)
begin
motor_next_state <= ALIGN;
end
end
ALIGN:
begin
if(align_complete == 1'b1)
begin
motor_next_state <= PHASE2;
end
end
PHASE1:
begin
if(position_i == 3'b010 || stall_counter == 0 )
begin
motor_next_state <= PHASE2;
end
end
PHASE2:
begin
if(position_i == 3'b110 || stall_counter == 0)
begin
motor_next_state <= PHASE3;
end
end
PHASE3:
begin
if(position_i == 3'b100 || stall_counter == 0 )
begin
motor_next_state <= PHASE4;
end
end
PHASE4:
begin
if(position_i == 3'b101 || stall_counter == 0 )
begin
motor_next_state <= PHASE5;
end
end
PHASE5:
begin
if(position_i == 3'b001 || stall_counter == 0 )
begin
motor_next_state <= PHASE6;
end
end
PHASE6:
begin
if(position_i == 3'b011 || stall_counter == 0 )
begin
motor_next_state <= PHASE1;
end
end
default:
begin
motor_next_state <= OFF;
end
endcase
end
always @(posedge clk_i)
begin
if (rst_n_i == 1'b0)
begin
stall_counter <= 32'd5000000;
end
else
begin
if (motor_next_state == motor_state && motor_state != OFF && motor_state != ALIGN)
begin
if(stall_counter > 0)
begin
stall_counter <= stall_counter - 1;
end
end
else
begin
stall_counter <= 32'd5000000;
end
end
end
//Generate the PWM signal
always @(posedge pwm_clk_i)
begin
if((rst_n_i == 1'b0))
begin
pwm_cnt <= 0;
end
else
begin
pwm_cnt <= pwm_cnt < (2**PWM_BITS - 1) ? pwm_cnt + 1 : 0;
end
pwm_s <= pwm_cnt < pwm_duty_s ? 1 : 0;
end
endmodule

380
projects/motor_control/common/motor_control_bd.tcl Executable file
View File

@ -0,0 +1,380 @@
# motor control
# position detection interface
set position_i [ create_bd_port -dir I -from 2 -to 0 position_i ]
# current monitor 1 interface
set adc_ia_dat_i [ create_bd_port -dir I adc_ia_dat_i ]
set adc_ib_dat_i [ create_bd_port -dir I adc_ib_dat_i ]
set adc_it_dat_i [ create_bd_port -dir I adc_it_dat_i ]
set adc_vbus_dat_i [ create_bd_port -dir I adc_vbus_dat_i ]
set adc_ia_clk_o [ create_bd_port -dir O adc_ia_clk_o ]
set adc_ib_clk_o [ create_bd_port -dir O adc_ib_clk_o ]
set adc_it_clk_o [ create_bd_port -dir O adc_it_clk_o ]
set adc_vbus_clk_o [ create_bd_port -dir O adc_vbus_clk_o ]
# cuurrent monitor 2 interface
set adc_ia_dat_d_i [ create_bd_port -dir I adc_ia_dat_d_i ]
set adc_ib_dat_d_i [ create_bd_port -dir I adc_ib_dat_d_i ]
set adc_it_dat_d_i [ create_bd_port -dir I adc_it_dat_d_i ]
set adc_ia_clk_d_o [ create_bd_port -dir O adc_ia_clk_d_o ]
set adc_ib_clk_d_o [ create_bd_port -dir O adc_ib_clk_d_o ]
set adc_it_clk_d_o [ create_bd_port -dir O adc_it_clk_d_o ]
# motor control interface
set fmc_m1_fault_i [ create_bd_port -dir I fmc_m1_fault_i ]
set fmc_m1_en_o [ create_bd_port -dir O fmc_m1_en_o ]
set pwm_al_o [ create_bd_port -dir O pwm_al_o]
set pwm_ah_o [ create_bd_port -dir O pwm_ah_o]
set pwm_cl_o [ create_bd_port -dir O pwm_cl_o]
set pwm_ch_o [ create_bd_port -dir O pwm_ch_o]
set pwm_bl_o [ create_bd_port -dir O pwm_bl_o]
set pwm_bh_o [ create_bd_port -dir O pwm_bh_o]
# gpo interface
set gpo_o [ create_bd_port -dir O -from 7 -to 0 gpo_o ]
# xadc interface
set vp_in [ create_bd_port -dir I vp_in ]
set vn_in [ create_bd_port -dir I vn_in ]
set vauxp0 [ create_bd_port -dir I vauxp0 ]
set vauxn0 [ create_bd_port -dir I vauxn0 ]
set vauxp8 [ create_bd_port -dir I vauxp8 ]
set vauxn8 [ create_bd_port -dir I vauxn8 ]
set muxaddr_out [ create_bd_port -dir O -from 4 -to 0 muxaddr_out ]
# additions to default configuration
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect
set_property -dict [ list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7
# current monitor 1 peripherals
set axi_mc_current_monitor_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_1 ]
set axi_current_monitor_1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_1_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_1_dma
# set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_1_dma
# current monitor 2 peripherals
set axi_mc_current_monitor_2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_2 ]
set axi_current_monitor_2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_2_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_2_dma
# set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_2_dma
# speed detector
set axi_mc_speed_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 axi_mc_speed_1 ]
set axi_speed_detector_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_speed_detector_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_speed_detector_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_speed_detector_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_speed_detector_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_speed_detector_dma
# set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {2}] $axi_speed_detector_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_speed_detector_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_speed_detector_dma
# torque controller
set axi_mc_torque_controller [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_torque_ctrl:1.0 axi_mc_torque_controller ]
set axi_torque_controller_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_torque_controller_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_torque_controller_dma
# set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {2}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_torque_controller_dma
# xadc
set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ]
set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1
set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_wiz_1
set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_wiz_1
set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} ] $xadc_wiz_1
set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {false} ] $xadc_wiz_1
# additional interconnect
set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect ]
set_property -dict [ list CONFIG.NUM_SI {4} CONFIG.NUM_MI {1} ] $axi_mem_interconnect
# connections
# position
connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i] [get_bd_pins axi_mc_speed_1/bemf_i]
# current monitor 1
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/ref_clk] $sys_100m_clk_source
connect_bd_net -net adc_ia_dat_i_1 [get_bd_ports adc_ia_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ia_dat_i]
connect_bd_net -net adc_ib_dat_i_1 [get_bd_ports adc_ib_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ib_dat_i]
connect_bd_net -net adc_it_dat_i_1 [get_bd_ports adc_it_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_it_dat_i]
connect_bd_net -net adc_vbus_dat_i_1 [get_bd_ports adc_vbus_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_dat_i]
connect_bd_net -net axi_mc_current_monitor_1_adc_ia_clk_o [get_bd_ports adc_ia_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ia_clk_o]
connect_bd_net -net axi_mc_current_monitor_1_adc_ib_clk_o [get_bd_ports adc_ib_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ib_clk_o]
connect_bd_net -net axi_mc_current_monitor_1_adc_it_clk_o [get_bd_ports adc_it_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_it_clk_o]
connect_bd_net -net axi_mc_current_monitor_1_adc_vbus_clk_o [get_bd_ports adc_vbus_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_clk_o]
connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins axi_mc_current_monitor_1/adc_clk_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins axi_mc_current_monitor_1/adc_dwr_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_en]
connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins axi_mc_current_monitor_1/adc_ddata_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_din]
connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins axi_mc_current_monitor_1/adc_dsync_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_sync]
connect_bd_net -net axi_mc_current_monitor_1_adc_mon_data [get_bd_pins axi_mc_current_monitor_1/adc_mon_data]
#connect_bd_net -net axi_mc_current_monitor_1_adc_dovf [get_bd_pins axi_mc_current_monitor_1/adc_dovf_i]
#connect_bd_net -net axi_mc_current_monitor_1_adc_dunf [get_bd_pins axi_mc_current_monitor_1/adc_dunf_i]
connect_bd_net [get_bd_pins axi_mc_current_monitor_1/i_ready_o] [get_bd_pins axi_mc_torque_controller/i_ready_i]
# interrupt
connect_bd_net -net axi_current_monitor_1_dma_irq [get_bd_pins axi_current_monitor_1_dma/irq] [get_bd_pins sys_concat_intc/In2]
# current monitor 2
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/ref_clk] $sys_100m_clk_source
connect_bd_net -net adc_ia_dat_d_i [get_bd_ports adc_ia_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_ia_dat_i]
connect_bd_net -net axi_mc_current_monitor_2_adc_ia_clk_o [get_bd_ports adc_ia_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_ia_clk_o]
connect_bd_net -net adc_ib_dat_d_i [get_bd_ports adc_ib_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_ib_dat_i]
connect_bd_net -net axi_mc_current_monitor_2_adc_ib_clk_o [get_bd_ports adc_ib_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_ib_clk_o]
connect_bd_net -net adc_it_dat_d_i [get_bd_ports adc_it_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_it_dat_i]
connect_bd_net -net axi_mc_current_monitor_2_adc_it_clk_o [get_bd_ports adc_it_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_it_clk_o]
connect_bd_net -net axi_mc_current_monitor_2_adc_clk [get_bd_pins axi_mc_current_monitor_2/adc_clk_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_current_monitor_2_adc_dwr [get_bd_pins axi_mc_current_monitor_2/adc_dwr_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_en]
connect_bd_net -net axi_mc_current_monitor_2_adc_ddata [get_bd_pins axi_mc_current_monitor_2/adc_ddata_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_din]
connect_bd_net -net axi_mc_current_monitor_2_adc_dsync [get_bd_pins axi_mc_current_monitor_2/adc_dsync_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_sync]
#connect_bd_net -net axi_mc_current_monitor_2_adc_dovf [get_bd_pins axi_mc_current_monitor_2/adc_dovf_i]
#connect_bd_net -net axi_mc_current_monitor_2_adc_dunf [get_bd_pins axi_mc_current_monitor_2/adc_dunf_i]
#interrupt
connect_bd_net -net axi_current_monitor_2_dma_irq [get_bd_pins axi_current_monitor_2_dma/irq] [get_bd_pins sys_concat_intc/In6]
# speed detector
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/ref_clk] $sys_100m_clk_source
connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o]
connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o] [get_bd_pins axi_mc_torque_controller/position_i]
connect_bd_net -net axi_mc_speed_1_new_speed_o [get_bd_pins axi_mc_speed_1/new_speed_o]
connect_bd_net -net axi_mc_speed_1_new_speed_o [get_bd_pins axi_mc_speed_1/new_speed_o] [get_bd_pins axi_mc_torque_controller/new_speed_i]
connect_bd_net -net axi_mc_speed_1_speed_o [get_bd_pins axi_mc_speed_1/speed_o]
connect_bd_net -net axi_mc_speed_1_speed_o [get_bd_pins axi_mc_speed_1/speed_o] [get_bd_pins axi_mc_torque_controller/speed_i]
connect_bd_net [get_bd_pins /axi_mc_torque_controller/fmc_m1_fault_i] [get_bd_ports /fmc_m1_fault_i]
connect_bd_net -net speed_detector_adc_clk [get_bd_pins axi_mc_speed_1/adc_clk_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_clk]
connect_bd_net -net speed_detector_adc_dwr [get_bd_pins axi_mc_speed_1/adc_dwr_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_en]
connect_bd_net -net speed_detector_adc_ddata [get_bd_pins axi_mc_speed_1/adc_ddata_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_din]
#connect_bd_net -net speed_detector_adc_dovf [get_bd_pins axi_mc_speed_1/adc_dovf_i]
#connect_bd_net -net speed_detector_adc_dunf [get_bd_pins axi_mc_speed_1/adc_dunf_i]
# interrupt
connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_pins sys_concat_intc/In3]
# torque controller
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_torque_controller/ref_clk] $sys_100m_clk_source
connect_bd_net -net axi_mc_current_monitor_1_it_o [get_bd_pins axi_mc_current_monitor_1/it_o] [get_bd_pins axi_mc_torque_controller/it_i]
connect_bd_net -net axi_mc_torque_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins axi_mc_torque_controller/fmc_m1_en_o]
connect_bd_net -net axi_mc_torque_controller_pwm_al_o [get_bd_ports pwm_al_o] [get_bd_pins axi_mc_torque_controller/pwm_al_o]
connect_bd_net -net axi_mc_torque_controller_pwm_ah_o [get_bd_ports pwm_ah_o] [get_bd_pins axi_mc_torque_controller/pwm_ah_o]
connect_bd_net -net axi_mc_torque_controller_pwm_cl_o [get_bd_ports pwm_cl_o] [get_bd_pins axi_mc_torque_controller/pwm_cl_o]
connect_bd_net -net axi_mc_torque_controller_pwm_ch_o [get_bd_ports pwm_ch_o] [get_bd_pins axi_mc_torque_controller/pwm_ch_o]
connect_bd_net -net axi_mc_torque_controller_pwm_bl_o [get_bd_ports pwm_bl_o] [get_bd_pins axi_mc_torque_controller/pwm_bl_o]
connect_bd_net -net axi_mc_torque_controller_pwm_bh_o [get_bd_ports pwm_bh_o] [get_bd_pins axi_mc_torque_controller/pwm_bh_o]
connect_bd_net -net axi_mc_torque_controller_gpo_o [get_bd_ports gpo_o] [get_bd_pins axi_mc_torque_controller/gpo_o]
connect_bd_net -net axi_mc_torque_controller_sensors_o [get_bd_pins axi_mc_torque_controller/sensors_o] [get_bd_pins axi_mc_speed_1/hall_bemf_i]
connect_bd_net -net axi_mc_torque_controller_adc_clk [get_bd_pins axi_mc_torque_controller/adc_clk_o] [get_bd_pins axi_torque_controller_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_torque_controller_adc_dwr [get_bd_pins axi_mc_torque_controller/adc_dwr_o] [get_bd_pins axi_torque_controller_dma/fifo_wr_en]
connect_bd_net -net axi_mc_torque_controller_adc_ddata [get_bd_pins axi_mc_torque_controller/adc_ddata_o] [get_bd_pins axi_torque_controller_dma/fifo_wr_din]
#connect_bd_net -net axi_mc_torque_controller_adc_dsync [get_bd_pins axi_mc_torque_controller/adc_dsync_o] [get_bd_pins axi_torque_controller_dma/fifo_wr_sync]
#connect_bd_net -net axi_mc_torque_controller_adc_dovf [get_bd_pins axi_mc_torque_controller/adc_dovf_i]
#connect_bd_net -net axi_mc_torque_controller_adc_dunf [get_bd_pins axi_mc_torque_controller/adc_dunf_i]
# interrupt
connect_bd_net -net axi_torque_controller_dma_irq [get_bd_pins axi_torque_controller_dma/irq] [get_bd_pins sys_concat_intc/In5]
# xadc
connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net vp_in_1 [get_bd_ports vp_in] [get_bd_pins xadc_wiz_1/vp_in]
connect_bd_net -net vn_in_1 [get_bd_ports vn_in] [get_bd_pins xadc_wiz_1/vn_in]
connect_bd_net -net vauxp0_1 [get_bd_ports vauxp0] [get_bd_pins xadc_wiz_1/vauxp0]
connect_bd_net -net vauxn0_1 [get_bd_ports vauxn0] [get_bd_pins xadc_wiz_1/vauxn0]
connect_bd_net -net vauxp8_1 [get_bd_ports vauxp8] [get_bd_pins xadc_wiz_1/vauxp8]
connect_bd_net -net vauxn8_1 [get_bd_ports vauxn8] [get_bd_pins xadc_wiz_1/vauxn8]
connect_bd_net -net xadc_wiz_1_muxaddr_out [get_bd_ports muxaddr_out] [get_bd_pins xadc_wiz_1/muxaddr_out]
# ila
set ila_current_monitor [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_current_monitor]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE2_WIDTH {1}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE3_WIDTH {64}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE4_WIDTH {32}] $ila_current_monitor
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1} ] $ila_current_monitor
set_property -dict [list CONFIG.C_ADV_TRIGGER {true}] $ila_current_monitor
connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins ila_current_monitor/probe0]
connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins ila_current_monitor/probe1]
connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins ila_current_monitor/probe2]
connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins ila_current_monitor/probe3]
connect_bd_net -net axi_mc_current_monitor_1_adc_mon_data [get_bd_pins ila_current_monitor/probe4]
connect_bd_net -net sys_100m_clk [get_bd_pins ila_current_monitor/clk]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_mc_current_monitor_1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_torque_controller/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_torque_controller_dma/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source
#inteconnects (current monitor 1)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_1/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_mem_interconnect_s01_axi [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/m_dest_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source
#interconnect (current monitor 2)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_2/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_mem_interconnect_s02_axi [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/m_dest_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source
# interconnect (speed detector)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_speed_1/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_mem_interconnect_s00_axi [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins axi_speed_detector_dma/m_dest_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source
# interconnect (torque controller)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_torque_controller/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_torque_controller/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_torque_controller_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_torque_controller_dma/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_torque_controller_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_torque_controller_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_mem_interconnect_s03_axi [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_torque_controller_dma/m_dest_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source
# interconnect (dmas)
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_mem_interconnect_m00_axi [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
# address map
create_bd_addr_seg -range 0x10000 -offset 0x40400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_1_dma/s_axi/axi_lite] SEG_data_c_m_1_dma
create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs axi_speed_detector_dma/s_axi/axi_lite] SEG_data_s_d_dma
create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_torque_controller_dma/s_axi/axi_lite] SEG_data_t_c_dma
create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_2_dma/s_axi/axi_lite] SEG_data_c_m_2_dma
create_bd_addr_seg -range 0x10000 -offset 0x40500000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_1/s_axi/axi_lite] SEG_data_c_m_1
create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d
create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_torque_controller/s_axi/axi_lite] SEG_data_t_c
create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2
create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_speed_detector_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_torque_controller_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm

5
projects/motor_control/zed/system_bd.tcl Executable file
View File

@ -0,0 +1,5 @@
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/motor_control_bd.tcl

112
projects/motor_control/zed/system_constr.xdc Executable file
View File

@ -0,0 +1,112 @@
# Motor Control
#Test
#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[27]] ; ## XADC-GIO0
#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[28]] ; ## XADC-GIO1
#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[29]] ; ## XADC-GIO2
#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[30]] ; ## XADC-GIO3
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3
#End Test
set_property PACKAGE_PIN J16 [get_ports {position_i[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {position_i[0]}]
set_property PACKAGE_PIN J17 [get_ports {position_i[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {position_i[1]}]
set_property PACKAGE_PIN G15 [get_ports {position_i[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {position_i[2]}]
set_property PACKAGE_PIN A16 [get_ports pwm_ah_o]
set_property IOSTANDARD LVCMOS25 [get_ports pwm_ah_o]
set_property PACKAGE_PIN A17 [get_ports pwm_al_o]
set_property IOSTANDARD LVCMOS25 [get_ports pwm_al_o]
set_property PACKAGE_PIN C15 [get_ports pwm_bh_o]
set_property IOSTANDARD LVCMOS25 [get_ports pwm_bh_o]
set_property PACKAGE_PIN B15 [get_ports pwm_bl_o]
set_property IOSTANDARD LVCMOS25 [get_ports pwm_bl_o]
set_property PACKAGE_PIN A21 [get_ports pwm_ch_o]
set_property IOSTANDARD LVCMOS25 [get_ports pwm_ch_o]
set_property PACKAGE_PIN A22 [get_ports pwm_cl_o]
set_property IOSTANDARD LVCMOS25 [get_ports pwm_cl_o]
set_property PACKAGE_PIN L21 [get_ports fmc_m1_en_o]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_m1_en_o]
set_property PACKAGE_PIN L22 [get_ports fmc_m1_fault_i]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_m1_fault_i]
set_property PACKAGE_PIN T16 [get_ports adc_ia_dat_i]
set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_dat_i]
set_property PACKAGE_PIN T17 [get_ports adc_ib_dat_i]
set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_dat_i]
set_property PACKAGE_PIN N17 [get_ports adc_it_dat_i]
set_property IOSTANDARD LVCMOS25 [get_ports adc_it_dat_i]
set_property PACKAGE_PIN N18 [get_ports adc_vbus_dat_i]
set_property IOSTANDARD LVCMOS25 [get_ports adc_vbus_dat_i]
set_property PACKAGE_PIN P17 [get_ports adc_ia_clk_o]
set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_clk_o]
set_property PACKAGE_PIN P18 [get_ports adc_ib_clk_o]
set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_clk_o]
set_property PACKAGE_PIN M21 [get_ports adc_it_clk_o]
set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_o]
set_property PACKAGE_PIN M22 [get_ports adc_vbus_clk_o]
set_property IOSTANDARD LVCMOS25 [get_ports adc_vbus_clk_o]
set_property PACKAGE_PIN A18 [get_ports {gpo_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[0]}]
set_property PACKAGE_PIN A19 [get_ports {gpo_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[1]}]
set_property PACKAGE_PIN R19 [get_ports {gpo_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[2]}]
set_property PACKAGE_PIN T19 [get_ports {gpo_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[3]}]
set_property PACKAGE_PIN D21 [get_ports {gpo_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[4]}]
set_property PACKAGE_PIN J22 [get_ports {gpo_o[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[5]}]
set_property PACKAGE_PIN G16 [get_ports {gpo_o[6]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[6]}]
set_property PACKAGE_PIN M19 [get_ports {gpo_o[7]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[7]}]
set_property PACKAGE_PIN B17 [get_ports adc_ia_dat_d_i]
set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_dat_d_i]
set_property PACKAGE_PIN B21 [get_ports adc_ib_dat_d_i]
set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_dat_d_i]
set_property PACKAGE_PIN B22 [get_ports adc_it_dat_d_i]
set_property IOSTANDARD LVCMOS25 [get_ports adc_it_dat_d_i]
set_property PACKAGE_PIN D20 [get_ports adc_ia_clk_d_o]
set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_clk_d_o]
set_property PACKAGE_PIN C20 [get_ports adc_ib_clk_d_o]
set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_clk_d_o]
set_property PACKAGE_PIN E21 [get_ports adc_it_clk_d_o]
set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_d_o]
set_property PACKAGE_PIN H15 [get_ports {muxaddr_out[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[0]}]
set_property PACKAGE_PIN R15 [get_ports {muxaddr_out[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[1]}]
set_property PACKAGE_PIN K15 [get_ports {muxaddr_out[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[2]}]
set_property PACKAGE_PIN J15 [get_ports {muxaddr_out[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[3]}]
set_property PACKAGE_PIN E16 [get_ports vauxn0]
set_property IOSTANDARD LVCMOS25 [get_ports vauxn0]
set_property PACKAGE_PIN D17 [get_ports vauxn8]
set_property IOSTANDARD LVCMOS25 [get_ports vauxn8]
set_property PACKAGE_PIN F16 [get_ports vauxp0]
set_property IOSTANDARD LVCMOS25 [get_ports vauxp0]
set_property PACKAGE_PIN D16 [get_ports vauxp8]
set_property IOSTANDARD LVCMOS25 [get_ports vauxp8]
set_property PACKAGE_PIN M12 [get_ports vn_in]
set_property IOSTANDARD LVCMOS25 [get_ports vn_in]
set_property PACKAGE_PIN L11 [get_ports vp_in]
set_property IOSTANDARD LVCMOS25 [get_ports vp_in]

13
projects/motor_control/zed/system_project.tcl Executable file
View File

@ -0,0 +1,13 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create motor_control_zed
adi_project_files motor_control_zed [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
adi_project_run motor_control_zed

313
projects/motor_control/zed/system_top.v Executable file
View File

@ -0,0 +1,313 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
adc_ia_clk_d_o,
adc_ia_clk_o,
adc_ia_dat_d_i,
adc_ia_dat_i,
adc_ib_clk_d_o,
adc_ib_clk_o,
adc_ib_dat_d_i,
adc_ib_dat_i,
adc_it_clk_d_o,
adc_it_clk_o,
adc_it_dat_d_i,
adc_it_dat_i,
adc_vbus_clk_o,
adc_vbus_dat_i,
fmc_m1_en_o,
fmc_m1_fault_i,
gpo_o,
position_i,
pwm_ah_o,
pwm_al_o,
pwm_bh_o,
pwm_bl_o,
pwm_ch_o,
pwm_cl_o,
vauxn0,
vauxn8,
vauxp0,
vauxp8,
vn_in,
vp_in,
muxaddr_out,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output adc_ia_clk_d_o;
output adc_ia_clk_o;
input adc_ia_dat_d_i;
input adc_ia_dat_i;
output adc_ib_clk_d_o;
output adc_ib_clk_o;
input adc_ib_dat_d_i;
input adc_ib_dat_i;
output adc_it_clk_d_o;
output adc_it_clk_o;
input adc_it_dat_d_i;
input adc_it_dat_i;
output adc_vbus_clk_o;
input adc_vbus_dat_i;
output fmc_m1_en_o;
input fmc_m1_fault_i;
output [7:0] gpo_o;
input [2:0] position_i;
output pwm_ah_o;
output pwm_al_o;
output pwm_bh_o;
output pwm_bl_o;
output pwm_ch_o;
output pwm_cl_o;
input vauxn0;
input vauxn8;
input vauxp0;
input vauxp8;
input vn_in;
input vp_in;
output [3:0]muxaddr_out;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
genvar n;
generate
for (n = 0; n <= 31; n = n + 1) begin: g_iobuf_gpio_bd
IOBUF i_iobuf_gpio_bd (
.I (gpio_o[n]),
.O (gpio_i[n]),
.T (gpio_t[n]),
.IO (gpio_bd[n]));
end
endgenerate
IOBUF i_iic_mux_scl_0 (.I(iic_mux_scl_o_s[0]), .O(iic_mux_scl_i_s[0]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[0]));
IOBUF i_iic_mux_scl_1 (.I(iic_mux_scl_o_s[1]), .O(iic_mux_scl_i_s[1]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[1]));
IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0]));
IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1]));
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.adc_ia_clk_d_o(adc_ia_clk_d_o),
.adc_ia_clk_o(adc_ia_clk_o),
.adc_ia_dat_d_i(adc_ia_dat_d_i),
.adc_ia_dat_i(adc_ia_dat_i),
.adc_ib_clk_d_o(adc_ib_clk_d_o),
.adc_ib_clk_o(adc_ib_clk_o),
.adc_ib_dat_d_i(adc_ib_dat_d_i),
.adc_ib_dat_i(adc_ib_dat_i),
.adc_it_clk_d_o(adc_it_clk_d_o),
.adc_it_clk_o(adc_it_clk_o),
.adc_it_dat_d_i(adc_it_dat_d_i),
.adc_it_dat_i(adc_it_dat_i),
.adc_vbus_clk_o(adc_vbus_clk_o),
.adc_vbus_dat_i(adc_vbus_dat_i),
.fmc_m1_en_o(fmc_m1_en_o),
.fmc_m1_fault_i(fmc_m1_fault_i),
.gpo_o(gpo_o),
.position_i(position_i),
.pwm_ah_o(pwm_ah_o),
.pwm_al_o(pwm_al_o),
.pwm_bh_o(pwm_bh_o),
.pwm_bl_o(pwm_bl_o),
.pwm_ch_o(pwm_ch_o),
.pwm_cl_o(pwm_cl_o),
.vauxn0(vauxn0),
.vauxn8(vauxn8),
.vauxp0(vauxp0),
.vauxp8(vauxp8),
.vn_in(vn_in),
.vp_in(vp_in),
.muxaddr_out(muxaddr_out),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_I (iic_mux_scl_i_s),
.iic_mux_scl_O (iic_mux_scl_o_s),
.iic_mux_scl_T (iic_mux_scl_t_s),
.iic_mux_sda_I (iic_mux_sda_i_s),
.iic_mux_sda_O (iic_mux_sda_o_s),
.iic_mux_sda_T (iic_mux_sda_t_s),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************