scripts: initial commit
Rejeesh Kutty
parent
581892b22a
commit
210da4116f
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@ -1,308 +1,218 @@
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#----------------------------------------------------------------------------
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# Internal processes
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#----------------------------------------------------------------------------
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###################################################################################################
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###################################################################################################
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# ensure that in case of a port number less than 10, the number format to be 0X
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# usage: get_numstr 2
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proc get_numstr {number} {
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if { $number < 10} {
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return "0${number}"
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} else {
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return $number
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variable sys_zynq
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variable sys_addr_cntrl_space
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variable sys_cpu_interconnect_index
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variable sys_hp0_interconnect_index
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variable sys_hp1_interconnect_index
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variable sys_hp2_interconnect_index
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variable sys_hp3_interconnect_index
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variable sys_mem_interconnect_index
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variable sys_interrupts_n
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variable sys_interrupts_q
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###################################################################################################
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###################################################################################################
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set sys_cpu_interconnect_index 0
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set sys_hp0_interconnect_index 0
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set sys_hp1_interconnect_index 0
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set sys_hp2_interconnect_index 0
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set sys_hp3_interconnect_index 0
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set sys_mem_interconnect_index 0
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set sys_interrupts_n 0
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###################################################################################################
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###################################################################################################
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proc ad_connect_type {p_name} {
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set m_name ""
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if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_pins -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_intf_nets -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_intf_pins -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
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return $m_name
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}
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proc ad_connect {p_name_1 p_name_2} {
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set m_name_1 [ad_connect_type $p_name_1]
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set m_name_2 [ad_connect_type $p_name_2]
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if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
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connect_bd_intf_net $m_name_1 $m_name_2
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return
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}
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if {[get_property CLASS $m_name_1] eq "bd_pin"} {
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connect_bd_net $m_name_1 $m_name_2
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return
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}
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if {[get_property CLASS $m_name_1] eq "bd_net"} {
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set m_source_1 [filter [get_bd_pins -of_objects [get_bd_nets $m_name_1]] -regexp "DIR == O"]
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connect_bd_net -net $m_name_1 $m_name_2 $m_source_1
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return
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}
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}
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#------------------------------------------------------------------------------
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# Integration processes
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#------------------------------------------------------------------------------
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# usage : adi_interconnect_lite axi_ad9467
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#------------------------------------------------------------------------------
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proc adi_interconnect_lite { p_name } {
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###################################################################################################
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###################################################################################################
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global sys_100m_clk_source
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global sys_100m_resetn_source
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proc ad_mem_interconnect {p_sel p_name p_clk} {
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set axi_cpu_interconnect [get_bd_cells axi_cpu_interconnect]
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# increment the number of the master ports of the interconnect
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set p_port [get_property CONFIG.NUM_MI $axi_cpu_interconnect]
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set i_count [expr $p_port + 1]
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set i_str [get_numstr $p_port]
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set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
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set p_seg_fields [split $p_seg "/"]
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lassign $p_seg_fields no_use p_seg_name p_seg_intf p_seg_base
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set_property CONFIG.NUM_MI $i_count [get_bd_cells axi_cpu_interconnect]
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "$axi_cpu_interconnect/M${i_str}_ACLK"] \
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[get_bd_pins "${p_name}/s_axi_aclk"] \
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$sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn \
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[get_bd_pins "${axi_cpu_interconnect}/M${i_str}_ARESETN"] \
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[get_bd_pins "${p_name}/s_axi_aresetn"] \
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$sys_100m_resetn_source
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# make the interface connection
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connect_bd_intf_net -intf_net "${p_name}axi_lite" \
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[get_bd_intf_pins "${axi_cpu_interconnect}/M${i_str}_AXI"] \
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[get_bd_intf_pins "${p_seg_name}/${p_seg_intf}"]
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set m_clk_source [filter [get_bd_pins -of_objects [get_bd_nets $p_clk]] -regexp "DIR == O"]
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if {($p_sel == "HP0") && ($sys_zynq == 1)} {
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if {$sys_hp0_interconnect_index == 0} {
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}
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}
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}
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#------------------------------------------------------------------------------
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# usage: adi_assign_base_address 0x74a00000 axi_ad9467
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#------------------------------------------------------------------------------
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proc adi_assign_base_address {p_addr p_name} {
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###################################################################################################
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###################################################################################################
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proc ad_cpu_interrupt {p_index p_name} {
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global sys_interrupts_n
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global sys_interrupts_q
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set i_str "In$p_index"
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if {$p_index >= $sys_interrupts_n} {
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set sys_interrupts_n [expr $p_index + 1]
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set_property CONFIG.NUM_PORTS $sys_interrupts_n [get_bd_cells sys_concat_intc]
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}
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set sys_interrupts_q($p_index) $p_name
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set p_intr [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \
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-regexp "TYPE == intr"]
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connect_bd_net -net "${p_name}_intr" \
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[get_bd_pins sys_concat_intc/${i_str}] \
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[get_bd_pins ${p_intr}]
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}
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proc ad_cpu_interrupt_update {} {
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global sys_zynq
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global sys_interrupts_n
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global sys_interrupts_q
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if {$sys_zynq == 1} {
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connect_bd_net -net sys_cpu_interrupt \
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[get_bd_pins sys_concat_intc/dout] \
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[get_bd_pins sys_ps7/IRQ_F2P]
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} else {
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connect_bd_net -net sys_cpu_interrupt \
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[get_bd_pins sys_concat_intc/dout] \
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[get_bd_pins axi_intc/intr]
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}
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for {set p_index 0} {$p_index < $sys_interrupts_n} {incr p_index} {
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if {![info exists sys_interrupts_q($p_index)]} {
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set i_str "In$p_index"
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set o_str "unc_intr_$p_index"
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create_bd_port -dir I ${o_str}
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connect_bd_net -net ${o_str} \
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[get_bd_pins sys_concat_intc/${i_str}] \
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[get_bd_ports ${o_str}]
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}
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}
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}
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###################################################################################################
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###################################################################################################
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proc ad_cpu_interconnect {p_address p_name} {
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global sys_zynq
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global sys_addr_cntrl_space
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global sys_cpu_interconnect_index
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set i_str "M$sys_cpu_interconnect_index"
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if {$sys_cpu_interconnect_index < 10} {
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set i_str "M0$sys_cpu_interconnect_index"
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}
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set m_clk_source [filter [get_bd_pins -of_objects [get_bd_nets sys_cpu_clk]] -regexp "DIR == O"]
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set m_reset_source [filter [get_bd_pins -of_objects [get_bd_nets sys_cpu_resetn]] -regexp "DIR == O"]
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if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 1)} {
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connect_bd_net -net sys_cpu_clk \
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[get_bd_pins sys_ps7/M_AXI_GP0_ACLK] \
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[get_bd_pins axi_cpu_interconnect/ACLK] \
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[get_bd_pins axi_cpu_interconnect/S00_ACLK] \
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$m_clk_source
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connect_bd_net -net sys_cpu_resetn \
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[get_bd_pins axi_cpu_interconnect/ARESETN] \
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[get_bd_pins axi_cpu_interconnect/S00_ARESETN] \
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$m_reset_source
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connect_bd_intf_net -intf_net sys_ps7_axi \
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[get_bd_intf_pins axi_cpu_interconnect/S00_AXI] \
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[get_bd_intf_pins sys_ps7/M_AXI_GP0]
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}
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if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 0)} {
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connect_bd_net -net sys_cpu_clk \
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[get_bd_pins sys_ps7/M_AXI_GP0_ACLK] \
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[get_bd_pins axi_cpu_interconnect/ACLK] \
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[get_bd_pins axi_cpu_interconnect/S00_ACLK] \
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$m_clk_source
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connect_bd_net -net sys_cpu_resetn \
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[get_bd_pins axi_cpu_interconnect/ARESETN] \
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[get_bd_pins axi_cpu_interconnect/S00_ARESETN] \
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$m_reset_source
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connect_bd_intf_net -intf_net sys_ps7_axi \
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[get_bd_intf_pins axi_cpu_interconnect/S00_AXI] \
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[get_bd_intf_pins sys_ps7/M_AXI_GP0]
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}
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set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
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set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
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set p_seg [lsearch -inline -regexp $p_seg (?i)/.*s_axi\/|axi_lite.*/]
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set p_seg_range [get_property range $p_seg]
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set p_seg_fields [split $p_seg "/"]
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lassign $p_seg_fields no_use p_seg_name p_seg_intf p_seg_base
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set p_seg_range [get_property range $p_seg]
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set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
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set p_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \
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-regexp "CONFIG.ASSOCIATED_BUSIF == ${p_seg_intf}"]
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set p_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_clock}]]
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connect_bd_net -net sys_cpu_clk \
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[get_bd_pins "axi_cpu_interconnect/${i_str}_ACLK"] \
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[get_bd_pins ${p_clock}] \
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$m_clk_source
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connect_bd_net -net sys_cpu_resetn \
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[get_bd_pins "axi_cpu_interconnect/${i_str}_ARESETN"] \
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[get_bd_pins ${p_name}/${p_reset}] \
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$m_reset_source
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connect_bd_intf_net -intf_net "${p_name}_axi_lite" \
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[get_bd_intf_pins "axi_cpu_interconnect/${i_str}_AXI"] \
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[get_bd_intf_pins ${p_seg_name}/${p_seg_intf}]
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create_bd_addr_seg -range $p_seg_range \
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-offset $p_addr $sys_addr_cntrl_space \
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-offset $p_address $sys_addr_cntrl_space \
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$p_seg "SEG_data_${p_name}"
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}
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#------------------------------------------------------------------------------
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# usage : adi_add_interrupt axi_ad9467_dma/irq
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#------------------------------------------------------------------------------
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proc adi_add_interrupt { intr_port } {
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global sys_zynq
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if { [get_bd_ports unc_int2] != {} } {
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delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2]
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connect_bd_net [get_bd_pins sys_concat_intc/In2] [get_bd_pins $intr_port]
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} elseif { [get_bd_ports unc_int3] != {} } {
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delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3]
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connect_bd_net [get_bd_pins sys_concat_intc/In3] [get_bd_pins $intr_port]
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} else {
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set p_intr [get_property CONFIG.NUM_PORTS [get_bd_cells sys_concat_intc]]
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set i_intr [expr $p_intr + 1]
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set_property CONFIG.NUM_PORTS $i_intr [get_bd_cells sys_concat_intc]
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connect_bd_net -net "sys_concat_intc_din_${i_intr}" \
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[get_bd_pins "sys_concat_intc/In${i_intr}"] \
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[get_bd_pins $intr_port]
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}
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# incrase the auxiliary concat last input port
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if { $sys_zynq == 0 } {
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set p_aux_intr [get_property CONFIG.IN9_WIDTH [get_bd_cells sys_concat_aux_intc]]
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set i_aux_intr [expr $p_aux_intr + 1]
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set_property CONFIG.IN9_WIDTH $i_aux_intr [get_bd_cells sys_concat_aux_intc]
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}
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}
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#------------------------------------------------------------------------------
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# usage : adi_spi_core 0x41600000 2 ad9467_spi
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#------------------------------------------------------------------------------
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proc adi_spi_core { spi_addr spi_ss spi_name } {
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global sys_zynq
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global sys_100m_clk_source
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# define SPI ports
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create_bd_port -dir I "${spi_name}_sclk_i"
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create_bd_port -dir O "${spi_name}_sclk_o"
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create_bd_port -dir I "${spi_name}_mosi_i"
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create_bd_port -dir O "${spi_name}_mosi_o"
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create_bd_port -dir I "${spi_name}_miso_i"
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create_bd_port -dir I "${spi_name}_csn_i"
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create_bd_port -dir O -from [expr $spi_ss - 1] -to 0 "${spi_name}_csn_o"
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# check processor type, connect system clock and reset to the peripheral
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if { $sys_zynq == 1 } {
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set sys_ps7 [get_bd_cells sys_ps7]
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# add SPI interface to ps7, first check which SPI is free
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if { [get_property CONFIG.PCW_SPI0_PERIPHERAL_ENABLE [get_bd_cells sys_ps7]] == 0 } {
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set if_spi "SPI0"
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} else {
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI0_IO {EMIO}] $sys_ps7
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set if_spi "SPI1"
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}
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# connect chipselect lines to the ports
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if { $spi_ss > 1 } {
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create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 "${spi_name}_csn_concat"
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set_property CONFIG.NUM_PORTS $spi_ss [get_bd_cells "${spi_name}_csn_concat"]
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connect_bd_net -net "${spi_name}_csn_o" \
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[get_bd_ports "${spi_name}_csn_o"] \
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[get_bd_pins "${spi_name}_csn_concat/dout"]
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set i 0
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set j [expr $spi_ss - 1]
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while { $i < $spi_ss } {
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if { $j == 0 } {
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set ss_number SS
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} else {
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set ss_number SS${j}
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}
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connect_bd_net [get_bd_pins "${spi_name}_csn_concat/In${i}"] \
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[get_bd_pins "sys_ps7/${if_spi}_${ss_number}_O"]
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incr i
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incr j -1
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}
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} else {
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connect_bd_net -net "${spi_name}_csn_o" \
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[get_bd_ports "${spi_name}_csn_o"] \
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[get_bd_pins "sys_ps7/${if_spi}_SS_O"]
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}
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# connect remaining nets to the ports
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connect_bd_net -net spi_csn_i \
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[get_bd_ports "${spi_name}_csn_i"] \
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[get_bd_pins "sys_ps7/${if_spi}_SS_I"]
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connect_bd_net -net spi_sclk_i \
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[get_bd_ports "${spi_name}_sclk_i"] \
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[get_bd_pins "sys_ps7/${if_spi}_SCLK_I"]
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connect_bd_net -net spi_sclk_o \
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[get_bd_ports "${spi_name}_sclk_o"] \
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[get_bd_pins "sys_ps7/${if_spi}_SCLK_O"]
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connect_bd_net -net spi_mosi_i \
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[get_bd_ports "${spi_name}_mosi_i"] \
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[get_bd_pins "sys_ps7/${if_spi}_MOSI_I"]
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connect_bd_net -net spi_mosi_o \
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[get_bd_ports "${spi_name}_mosi_o"] \
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[get_bd_pins "sys_ps7/${if_spi}_MOSI_O"]
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connect_bd_net -net spi_miso_i \
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[get_bd_ports "${spi_name}_miso_i"] \
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[get_bd_pins "sys_ps7/${if_spi}_MISO_I"]
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} else {
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# instanciate AXI_SPI core
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set spi_name [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 $spi_name]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $spi_name
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set_property -dict [list CONFIG.C_SCK_RATIO {16}] $spi_name
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set_property -dict [list CONFIG.Multiples16 {2}] $spi_name
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set_property CONFIG.C_NUM_SS_BITS $spi_ss $spi_name
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connect_bd_net -net sys_100m_clk \
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[get_bd_pins "${spi_name}/ext_spi_clk"] \
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$sys_100m_clk_source
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# spi external ports
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connect_bd_net -net spi_csn_o \
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[get_bd_ports "${spi_name}_csn_o"] \
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[get_bd_pins "${spi_name}/ss_o"]
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connect_bd_net -net spi_csn_i \
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[get_bd_ports "${spi_name}_csn_i"] \
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[get_bd_pins "${spi_name}/ss_i"]
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connect_bd_net -net spi_sclk_o \
|
||||
[get_bd_ports "${spi_name}_sclk_o"] \
|
||||
[get_bd_pins "${spi_name}/sck_o"]
|
||||
connect_bd_net -net spi_sclk_i \
|
||||
[get_bd_ports "${spi_name}_sclk_i"] \
|
||||
[get_bd_pins "${spi_name}/sck_i"]
|
||||
connect_bd_net -net spi_mosi_o \
|
||||
[get_bd_ports "${spi_name}_mosi_o"] \
|
||||
[get_bd_pins "${spi_name}/io0_o"]
|
||||
connect_bd_net -net spi_mosi_i \
|
||||
[get_bd_ports "${spi_name}_mosi_i"] \
|
||||
[get_bd_pins "${spi_name}/io0_i"]
|
||||
connect_bd_net -net spi_miso_i \
|
||||
[get_bd_ports "${spi_name}_miso_i"] \
|
||||
[get_bd_pins "${spi_name}/io1_i"]
|
||||
}
|
||||
}
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# adi_dma_interconnect axi_ad9467_dma/m_dest_axi sys_200m_clk axi_mem_interconnect
|
||||
#------------------------------------------------------------------------------
|
||||
proc adi_dma_interconnect { dma_if dma_clk ic_name } {
|
||||
|
||||
global sys_100m_resetn_source
|
||||
|
||||
set dma_atrb [split $dma_if "/"]
|
||||
lassign $dma_atrb dma_name dma_if_port
|
||||
|
||||
# increment the number of the slave ports of the interconnect
|
||||
set p_port [get_property CONFIG.NUM_SI [get_bd_cells $ic_name]]
|
||||
if { $p_port == 1} {
|
||||
if { [get_bd_intf_nets -of_object [get_bd_intf_pins "${ic_name}/S00_AXI"]] eq {} } {
|
||||
set i_count 1
|
||||
set i_str [get_numstr 0]
|
||||
} else {
|
||||
set i_count [expr $p_port + 1]
|
||||
set i_str [get_numstr $p_port]
|
||||
}
|
||||
} else {
|
||||
set i_count [expr $p_port + 1]
|
||||
set i_str [get_numstr $p_port]
|
||||
}
|
||||
|
||||
set_property CONFIG.NUM_SI $i_count [get_bd_cells $ic_name]
|
||||
|
||||
# connect clk and reset for the interconnect
|
||||
connect_bd_net [get_bd_pins "${ic_name}/S${i_str}_ACLK"] \
|
||||
${dma_clk}
|
||||
connect_bd_net [get_bd_pins "${ic_name}/S${i_str}_ARESETN"] \
|
||||
$sys_100m_resetn_source
|
||||
|
||||
# connect clk and reset for the peripheral port
|
||||
connect_bd_net [get_bd_pins "${dma_name}/${dma_if_port}_aclk"] \
|
||||
${dma_clk}
|
||||
connect_bd_net [get_bd_pins "${dma_name}/${dma_if_port}_aresetn"] \
|
||||
$sys_100m_resetn_source
|
||||
|
||||
# make the port connection
|
||||
connect_bd_intf_net -intf_net "${dma_name}_${i_str}" \
|
||||
[get_bd_intf_pins "${ic_name}/S${i_str}_AXI"] \
|
||||
[get_bd_intf_pins "${dma_name}/${dma_if_port}"]
|
||||
|
||||
# define address space for the peripheral
|
||||
assign_bd_address
|
||||
}
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# usage : adi_hp_assign 1
|
||||
#------------------------------------------------------------------------------
|
||||
proc adi_hp_assign { hp_port hp_clk } {
|
||||
|
||||
global sys_100m_resetn_source
|
||||
|
||||
# check is hp port is enabled
|
||||
if { [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port}" [get_bd_cells sys_ps7]] == 1 } {
|
||||
#return the interconnect of the hp port
|
||||
set hp_net [get_bd_intf_nets -of_objects [get_bd_intf_pins "sys_ps7/S_AXI_HP${hp_port}"]]
|
||||
set hp_net_cells [get_bd_cells -of_obkects $hp_net]
|
||||
set idx [lsearch $hp_net_cells "/sys_ps7"]
|
||||
set ic_hp [lreplace $hp_net_cells $idx $idx]
|
||||
} else {
|
||||
set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] [get_bd_cells sys_ps7]
|
||||
|
||||
set ic_hp "axi_hp${hp_port}_interconnect"
|
||||
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 $ic_hp
|
||||
set_property -dict [list CONFIG.NUM_MI {1}] [get_bd_cells $ic_hp]
|
||||
|
||||
connect_bd_intf_net -intf_net "${ic_hp}_m00_axi" \
|
||||
[get_bd_intf_pins "${ic_hp}/M00_AXI"] \
|
||||
[get_bd_intf_pins "sys_ps7/S_AXI_HP${hp_port}"]
|
||||
|
||||
# connect interconnect clock and reset
|
||||
connect_bd_net [get_bd_pins "${ic_hp}/ACLK"] \
|
||||
[get_bd_pins "${ic_hp}/M00_ACLK"] \
|
||||
[get_bd_pins "sys_ps7/S_AXI_HP${hp_port}_ACLK"] \
|
||||
$hp_clk
|
||||
connect_bd_net [get_bd_pins "${ic_hp}/ARESETN"] \
|
||||
[get_bd_pins "${ic_hp}/M00_ARESETN"] \
|
||||
$sys_100m_resetn_source
|
||||
}
|
||||
|
||||
return $ic_hp
|
||||
}
|
||||
|
||||
###################################################################################################
|
||||
###################################################################################################
|
||||
|
|
|
|||
Loading…
Reference in New Issue