adi_board.tcl: Add comments to all proc
Istvan Csomortani
István Csomortáni
parent
4d966500a8
commit
21031261b0
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@ -1,22 +1,6 @@
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###################################################################################################
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###################################################################################################
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variable sys_cpu_interconnect_index
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variable sys_hp0_interconnect_index
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variable sys_hp1_interconnect_index
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variable sys_hp2_interconnect_index
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variable sys_hp3_interconnect_index
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variable sys_mem_interconnect_index
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variable sys_mem_clk_index
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variable xcvr_index
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variable xcvr_tx_index
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variable xcvr_rx_index
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variable xcvr_instance
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###################################################################################################
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###################################################################################################
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## Global variables for interconnect interface indexing
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#
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set sys_cpu_interconnect_index 0
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set sys_hp0_interconnect_index -1
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set sys_hp1_interconnect_index -1
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@ -30,9 +14,13 @@ set xcvr_tx_index 0
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set xcvr_rx_index 0
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set xcvr_instance NONE
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###################################################################################################
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###################################################################################################
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## Add an instance of an IP to the block design.
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#
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# \param[i_ip] - name of the IP
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# \param[i_name] - name of the instance
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# \param[i_params] - a list of the parameters, the list must contain {name, value}
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# pairs
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#
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proc ad_ip_instance {i_ip i_name {i_params {}}} {
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set cell [create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && \
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@ -47,14 +35,24 @@ proc ad_ip_instance {i_ip i_name {i_params {}}} {
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}
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}
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## Define a parameter value of an IP instance.
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#
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# \param[i_name] - name of the instance
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# \param[i_param] - name of the parameter
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# \param[i_value] - value of the parameter
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#
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proc ad_ip_parameter {i_name i_param i_value} {
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set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
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}
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###################################################################################################
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###################################################################################################
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## Define the type of an IPI interface object, in general these objects an be:
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# interface pins, ports or nets; or cells pins, ports or nets.
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#
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# \param[p_name] - name of the object
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#
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# \return - the type of the object
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#
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proc ad_connect_type {p_name} {
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set m_name ""
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@ -69,8 +67,20 @@ proc ad_connect_type {p_name} {
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return $m_name
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}
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## Connect two IPI interface object together.
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#
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# \param[p_name_1] - first object name
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# \param[p_name_2] - second object name
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#
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# Valid object types are: GND/VCC, net/port/pin names or interface names
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#
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# \return - N/A
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#
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proc ad_connect {p_name_1 p_name_2} {
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## connect an IPI object to GND or VCC
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## instantiate xlconstant with the required width module if there isn't any
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## already
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if {($p_name_2 eq "GND") || ($p_name_2 eq "VCC")} {
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set p_size 1
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set p_msb [get_property left [get_bd_pins $p_name_1]]
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@ -128,6 +138,15 @@ proc ad_connect {p_name_1 p_name_2} {
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}
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}
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## Disconnect two IPI interface object together.
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#
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# \param[p_name_1] - first object name
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# \param[p_name_2] - second object name
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#
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# Valid object types are: GND/VCC, net/port/pin names or interface names
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#
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# \return - N/A
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#
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proc ad_disconnect {p_name_1 p_name_2} {
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set m_name_1 [ad_connect_type $p_name_1]
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@ -153,12 +172,17 @@ proc ad_disconnect {p_name_1 p_name_2} {
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}
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}
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###################################################################################################
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###################################################################################################
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## Define all the connections between the transceiver IP, the transceiver
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# configuration IP and the JESD204 Link IP.
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#
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# lane_map maps the logical lane $n onto the physical lane $lane_map[$n]. If no
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# lane map is provided logical lane $n is mapped onto physical lane $n.
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# \param[u_xcvr] - name of the transceiver IP (util_adxcvr)
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# \param[a_xcvr] - name of the transceiver configuration IP (axi_adxcvr)
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# \param[a_jesd] - name of the JESD204 link IP
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# \param[lane_map] - lane_map maps the logical lane $n onto the physical lane
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# $lane_map[$n], otherwise logical lane $n is mapped onto physical lane $n.
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# \param[device_clk] - define a custom device clock, should be a net name
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# connected to the clock source. If not used, the rx|tx_clk_out_0 is used as
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# device clock
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#
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proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {device_clk {}}} {
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@ -171,16 +195,6 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {device_clk {}}} {
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set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
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set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
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# set jesd204_vlnv [get_property VLNV $a_jesd]
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#
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# if {[string first "analog.com" $jesd204_vlnv] == 0} {
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# set jesd204_type 0
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# } elseif {[string first "xilinx.com" $jesd204_vlnv] == 0} {
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# set jesd204_type 1
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# } else {
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# return -code 1 "Unsupported JESD204 core type."
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# }
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set jesd204_bd_type [get_property TYPE [get_bd_cells $a_jesd]]
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if {$jesd204_bd_type == "hier"} {
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@ -291,9 +305,6 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {device_clk {}}} {
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ad_connect ${a_jesd}/sysref $m_sysref
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ad_connect ${a_jesd}/sync $m_sync
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ad_connect ${device_clk} ${a_jesd}/device_clk
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# if {$tx_or_rx_n == 0} {
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# ad_connect ${a_xcvr}/up_status ${a_jesd}/phy_ready
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# }
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} else {
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ad_connect ${a_jesd}/${txrx}_sysref $m_sysref
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ad_connect ${a_jesd}/${txrx}_sync $m_sync
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@ -311,6 +322,12 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {device_clk {}}} {
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}
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}
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## Connect all the PLL clock and reset ports of the transceiver IP to a clock
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# or reset source.
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#
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# \param[m_src] - name of the clock or reset source
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# \param[m_dst] - name or list of names of the clock or reset sink
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#
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proc ad_xcvrpll {m_src m_dst} {
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foreach p_dst [get_bd_pins -quiet $m_dst] {
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@ -318,9 +335,12 @@ proc ad_xcvrpll {m_src m_dst} {
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}
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}
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###################################################################################################
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###################################################################################################
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a
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# HP0 high speed interface in case of PSx.
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#
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# \param[p_clk] - name of the clock or reset source
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# \param[p_name] - name or list of names of the clock or reset sink
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#
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proc ad_mem_hp0_interconnect {p_clk p_name} {
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global sys_zynq
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@ -330,6 +350,12 @@ proc ad_mem_hp0_interconnect {p_clk p_name} {
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if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
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}
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a
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# HP1 high speed interface in case of PSx.
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#
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# \param[p_clk] - name of the clock or reset source
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# \param[p_name] - name or list of names of the clock or reset sink
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#
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proc ad_mem_hp1_interconnect {p_clk p_name} {
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global sys_zynq
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@ -339,6 +365,12 @@ proc ad_mem_hp1_interconnect {p_clk p_name} {
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if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
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}
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a
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# HP2 high speed interface in case of PSx.
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#
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# \param[p_clk] - name of the clock or reset source
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# \param[p_name] - name or list of names of the clock or reset sink
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#
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proc ad_mem_hp2_interconnect {p_clk p_name} {
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global sys_zynq
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@ -348,6 +380,12 @@ proc ad_mem_hp2_interconnect {p_clk p_name} {
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if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
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}
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a
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# HP3 high speed interface in case of PSx.
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#
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# \param[p_clk] - name of the clock or reset source
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# \param[p_name] - name or list of names of the clock or reset sink
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#
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proc ad_mem_hp3_interconnect {p_clk p_name} {
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global sys_zynq
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@ -357,9 +395,15 @@ proc ad_mem_hp3_interconnect {p_clk p_name} {
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if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
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}
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###################################################################################################
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###################################################################################################
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## Create an memory mapped interface connection to a MIG or PS7/8 IP, proc is
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# called in the ad_mem_hp[0|1|2|3]_interconnect processes, should never be
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# directly called in block designs.
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#
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# \param[p_sel] - name of the high speed interface, valid values are HP0, HP1
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# HP2, HP3 or MEM in case of Microblaze
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# \param[p_clk] - name of the clock or reset source
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# \param[p_name] - name or list of names of the clock or reset sink
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#
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proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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global sys_zynq
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@ -524,9 +568,12 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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}
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###################################################################################################
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###################################################################################################
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## Create an AXI4 Lite memory mapped interface connection for register maps,
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# instantiates an interconnect and reconfigure it at every process call.
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#
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# \param[p_address] - address offset of the IP register map
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# \param[p_name] - name of the IP
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#
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proc ad_cpu_interconnect {p_address p_name} {
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global sys_zynq
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@ -694,9 +741,12 @@ proc ad_cpu_interconnect {p_address p_name} {
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}
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}
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###################################################################################################
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###################################################################################################
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## Connects an IP interrupt port to the system's interrupt controller interface.
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#
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# \param[p_ps_index] - interrupt index used in PSx based architecture
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# \param[p_mb_index] - interrupt index used in Microblaze based architecture
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# \param[p_name] - name of the interrupt port
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#
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proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
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global sys_zynq
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@ -736,6 +786,3 @@ proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
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}
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}
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###################################################################################################
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###################################################################################################
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