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common: Define three global clock nets 

For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.

These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:

  - sys_cpu_clk     - 100MHz
  - sys_dma_clk     - 200MHz or 250Mhz
  - sys_iodelay_clk - 200MHz or 500Mhz
main
Istvan Csomortani 2019-05-27 10:52:27 +01:00 committed by István Csomortáni
parent c4c87c7c7a
commit 20c714eccf
11 changed files with 69 additions and 3 deletions
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6
projects/common/ac701/ac701_system_bd.tcl
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@ -151,6 +151,12 @@ ad_connect sys_cpu_resetn axi_ddr_cntrl/aresetn
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_200m_clk]
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_cpu_clk sys_mb/Clk
ad_connect sys_cpu_clk sys_dlmb/LMB_Clk

6
projects/common/kc705/kc705_system_bd.tcl
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@ -165,6 +165,12 @@ ad_connect sys_cpu_resetn axi_ddr_cntrl/aresetn
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_200m_clk]
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_cpu_clk sys_mb/Clk
ad_connect sys_cpu_clk sys_dlmb/LMB_Clk

6
projects/common/kcu105/kcu105_system_bd.tcl
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@ -136,6 +136,12 @@ ad_connect sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn
ad_connect sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn
ad_connect sys_200m_clk axi_ddr_cntrl/addn_ui_clkout2
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_200m_clk]
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
# microblaze
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset

6
projects/common/microzed/microzed_system_bd.tcl
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@ -61,6 +61,12 @@ ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_200m_clk]
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
# interface connections
ad_connect ddr sys_ps7/DDR

6
projects/common/vc707/vc707_system_bd.tcl
View File

@ -171,6 +171,12 @@ ad_connect sys_cpu_resetn axi_ddr_cntrl/aresetn
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_200m_clk]
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_cpu_clk sys_mb/Clk
ad_connect sys_cpu_clk sys_dlmb/LMB_Clk

8
projects/common/vcu118/vcu118_system_bd.tcl
View File

@ -76,6 +76,7 @@ ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE default_250mhz_clk
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE ddr4_sdram_c1
ad_ip_parameter axi_ddr_cntrl CONFIG.RESET_BOARD_INTERFACE reset
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ 250
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 500
ad_ip_instance proc_sys_reset axi_ddr_cntrl_rstgen
@ -136,6 +137,13 @@ ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn
ad_connect sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn
ad_connect sys_250m_clk axi_ddr_cntrl/addn_ui_clkout2
ad_connect sys_500m_clk axi_ddr_cntrl/addn_ui_clkout3
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_250m_clk]
set sys_iodelay_clk [get_bd_nets sys_500m_clk]
# microblaze debug & interrupt

6
projects/common/zc702/zc702_system_bd.tcl
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@ -110,6 +110,12 @@ ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_200m_clk]
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
# interface connections
ad_connect ddr sys_ps7/DDR

6
projects/common/zc706/zc706_system_bd.tcl
View File

@ -111,6 +111,12 @@ ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_200m_clk]
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
# interface connections
ad_connect ddr sys_ps7/DDR

14
projects/common/zcu102/zcu102_system_bd.tcl
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@ -30,8 +30,11 @@ ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ 100
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 200
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 250
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 500
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
@ -55,12 +58,19 @@ ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
# system reset/clock definitions
ad_connect sys_cpu_clk sys_ps8/pl_clk0
ad_connect sys_200m_clk sys_ps8/pl_clk1
ad_connect sys_250m_clk sys_ps8/pl_clk1
ad_connect sys_500m_clk sys_ps8/pl_clk2
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_250m_clk]
set sys_iodelay_clk [get_bd_nets sys_500m_clk]
# gpio
ad_connect gpio_i sys_ps8/emio_gpio_i

6
projects/common/zed/zed_system_bd.tcl
View File

@ -143,6 +143,12 @@ ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
# generic system clocks pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_200m_clk]
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
# interface connections
ad_connect ddr sys_ps7/DDR

2
projects/scripts/adi_board.tcl
View File

@ -548,7 +548,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
}
} else {
set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
if {[lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] "/$p_clk"] == -1 } {
if {[lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] $p_clk] == -1 } {
incr sys_mem_clk_index
set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index