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adxcvr- initial commit

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Rejeesh Kutty 2016-07-08 13:56:08 -04:00
parent 92c580a84d
commit 20ac95b1ec
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library/axi_adxcvr/axi_adxcvr.v Normal file
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library/axi_adxcvr/axi_adxcvr_es.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adxcvr_es (
// up interface
input up_rstn,
input up_clk,
output up_es_enb,
output [11:0] up_es_addr,
output up_es_wr,
output [15:0] up_es_wdata,
input [15:0] up_es_rdata,
input up_es_ready,
input up_ch_lpm_dfe_n,
input up_es_req,
output up_es_ack,
input [ 4:0] up_es_pscale,
input [ 1:0] up_es_vrange,
input [ 7:0] up_es_vstep,
input [ 7:0] up_es_vmax,
input [ 7:0] up_es_vmin,
input [11:0] up_es_hmax,
input [11:0] up_es_hmin,
input [11:0] up_es_hstep,
input [31:0] up_es_saddr,
output up_es_status,
// axi interface
output up_axi_awvalid,
output [31:0] up_axi_awaddr,
output [ 2:0] up_axi_awprot,
input up_axi_awready,
output up_axi_wvalid,
output [31:0] up_axi_wdata,
output [ 3:0] up_axi_wstrb,
input up_axi_wready,
input up_axi_bvalid,
input [ 1:0] up_axi_bresp,
output up_axi_bready,
output up_axi_arvalid,
output [31:0] up_axi_araddr,
output [ 2:0] up_axi_arprot,
input up_axi_arready,
input up_axi_rvalid,
input [31:0] up_axi_rdata,
input [ 1:0] up_axi_rresp,
output up_axi_rready);
// parameters
parameter integer GTH_OR_GTX_N = 0;
parameter integer TX_OR_RX_N = 0;
// addresses
localparam [11:0] ES_DRP_CTRL_ADDR = (GTH_OR_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d
localparam [11:0] ES_DRP_HOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c
localparam [11:0] ES_DRP_VOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b
localparam [11:0] ES_DRP_STATUS_ADDR = (GTH_OR_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153
localparam [11:0] ES_DRP_SCNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152
localparam [11:0] ES_DRP_ECNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151
// fsm-states
localparam [ 4:0] ES_FSM_IDLE = 6'h00;
localparam [ 4:0] ES_FSM_HOFFSET_READ = 6'h01;
localparam [ 4:0] ES_FSM_HOFFSET_RRDY = 6'h02;
localparam [ 4:0] ES_FSM_HOFFSET_WRITE = 6'h03;
localparam [ 4:0] ES_FSM_HOFFSET_WRDY = 6'h04;
localparam [ 4:0] ES_FSM_VOFFSET_READ = 6'h05;
localparam [ 4:0] ES_FSM_VOFFSET_RRDY = 6'h06;
localparam [ 4:0] ES_FSM_VOFFSET_WRITE = 6'h07;
localparam [ 4:0] ES_FSM_VOFFSET_WRDY = 6'h08;
localparam [ 4:0] ES_FSM_CTRL_READ = 6'h09;
localparam [ 4:0] ES_FSM_CTRL_RRDY = 6'h0a;
localparam [ 4:0] ES_FSM_START_WRITE = 6'h0b;
localparam [ 4:0] ES_FSM_START_WRDY = 6'h0c;
localparam [ 4:0] ES_FSM_STATUS_READ = 6'h0d;
localparam [ 4:0] ES_FSM_STATUS_RRDY = 6'h0e;
localparam [ 4:0] ES_FSM_STOP_WRITE = 6'h0f;
localparam [ 4:0] ES_FSM_STOP_WRDY = 6'h10;
localparam [ 4:0] ES_FSM_SCNT_READ = 6'h11;
localparam [ 4:0] ES_FSM_SCNT_RRDY = 6'h12;
localparam [ 4:0] ES_FSM_ECNT_READ = 6'h13;
localparam [ 4:0] ES_FSM_ECNT_RRDY = 6'h14;
localparam [ 4:0] ES_FSM_AXI_WRITE = 6'h15;
localparam [ 4:0] ES_FSM_AXI_READY = 6'h16;
localparam [ 4:0] ES_FSM_UPDATE = 6'h17;
// internal registers
reg up_awvalid = 'd0;
reg [31:0] up_awaddr = 'd0;
reg up_wvalid = 'd0;
reg [31:0] up_wdata = 'd0;
reg up_status = 'd0;
reg up_ut = 'd0;
reg [31:0] up_daddr = 'd0;
reg [11:0] up_hindex = 'd0;
reg [ 7:0] up_vindex = 'd0;
reg [15:0] up_hdata = 'd0;
reg [15:0] up_vdata = 'd0;
reg [15:0] up_cdata = 'd0;
reg [15:0] up_sdata = 'd0;
reg [15:0] up_edata = 'd0;
reg up_req_d = 'd0;
reg up_ack = 'd0;
reg [ 4:0] up_fsm = 'd0;
reg up_enb = 'd0;
reg [11:0] up_addr = 'd0;
reg up_wr = 'd0;
reg [15:0] up_data = 'd0;
// internal signals
wire up_heos_s;
wire up_eos_s;
wire up_ut_s;
wire [ 7:0] up_vindex_m_s;
wire [ 7:0] up_vindex_n_s;
wire [ 7:0] up_vindex_s;
wire up_start_s;
// axi interface
generate
if (TX_OR_RX_N == 1) begin
assign up_axi_awvalid = 1'b0;
assign up_axi_awaddr = 32'd0;
assign up_axi_awprot = 3'd0;
assign up_axi_wvalid = 1'b0;
assign up_axi_wdata = 32'd0;
assign up_axi_wstrb = 4'hf;
assign up_axi_bready = 1'b1;
assign up_axi_arvalid = 1'b0;
assign up_axi_araddr = 32'd0;
assign up_axi_arprot = 3'd0;
assign up_axi_rready = 1'b1;
end else begin
assign up_axi_awvalid = up_awvalid;
assign up_axi_awaddr = up_awaddr;
assign up_axi_awprot = 3'd0;
assign up_axi_wvalid = up_wvalid;
assign up_axi_wdata = up_wdata;
assign up_axi_wstrb = 4'hf;
assign up_axi_bready = 1'b1;
assign up_axi_arvalid = 1'b0;
assign up_axi_araddr = 32'd0;
assign up_axi_arprot = 3'd0;
assign up_axi_rready = 1'b1;
end
endgenerate
// reconfig interface
generate
if (TX_OR_RX_N == 1) begin
assign up_es_ack = 1'b1;
assign up_es_enb = 1'b0;
assign up_es_addr = 12'd0;
assign up_es_wr = 1'd0;
assign up_es_wdata = 16'd0;
assign up_es_status = 1'd0;
end else begin
assign up_es_ack = up_ack;
assign up_es_enb = up_enb;
assign up_es_addr = up_addr;
assign up_es_wr = up_wr;
assign up_es_wdata = up_data;
assign up_es_status = up_status;
end
endgenerate
// axi write
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_awvalid <= 'b0;
up_awaddr <= 'd0;
up_wvalid <= 'b0;
up_wdata <= 'd0;
up_status <= 'd0;
end else begin
if ((up_awvalid == 1'b1) && (up_axi_awready == 1'b1)) begin
up_awvalid <= 1'b0;
up_awaddr <= 32'd0;
end else if (up_fsm == ES_FSM_AXI_WRITE) begin
up_awvalid <= 1'b1;
up_awaddr <= up_daddr;
end
if ((up_wvalid == 1'b1) && (up_axi_wready == 1'b1)) begin
up_wvalid <= 1'b0;
up_wdata <= 32'd0;
end else if (up_fsm == ES_FSM_AXI_WRITE) begin
up_wvalid <= 1'b1;
up_wdata <= {up_sdata, up_edata};
end
if (up_axi_bvalid == 1'b1) begin
up_status <= | up_axi_bresp;
end
end
end
// prescale, horizontal and vertical offsets
assign up_heos_s = (up_hindex == up_es_hmax) ? up_ut : 1'b0;
assign up_eos_s = (up_vindex == up_es_vmax) ? up_heos_s : 1'b0;
assign up_ut_s = up_ut & ~up_ch_lpm_dfe_n;
assign up_vindex_m_s = ~up_vindex + 1'b1;
assign up_vindex_n_s = {1'b1, up_vindex_m_s[6:0]};
assign up_vindex_s = (up_vindex[7] == 1'b1) ? up_vindex_n_s : up_vindex;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_ut <= 'd0;
up_daddr <= 'd0;
up_hindex <= 'd0;
up_vindex <= 'd0;
end else begin
if (up_fsm == ES_FSM_IDLE) begin
up_ut <= up_ch_lpm_dfe_n;
up_daddr <= up_es_saddr;
up_hindex <= up_es_hmin;
up_vindex <= up_es_vmin;
end else if (up_fsm == ES_FSM_UPDATE) begin
up_ut <= ~up_ut | up_ch_lpm_dfe_n;
up_daddr <= up_daddr + 3'd4;
if (up_heos_s == 1'b1) begin
up_hindex <= up_es_hmin;
end else if (up_ut == 1'b1) begin
up_hindex <= up_hindex + up_es_hstep;
end
if (up_heos_s == 1'b1) begin
up_vindex <= up_vindex + up_es_vstep;
end
end
end
end
// read-modify-write
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_hdata <= 'd0;
up_vdata <= 'd0;
up_cdata <= 'd0;
up_sdata <= 'd0;
up_edata <= 'd0;
end else begin
if ((up_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_ready == 1'b1)) begin
up_hdata <= up_es_rdata;
end
if ((up_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_ready == 1'b1)) begin
up_vdata <= up_es_rdata;
end
if ((up_fsm == ES_FSM_CTRL_RRDY) && (up_es_ready == 1'b1)) begin
up_cdata <= up_es_rdata;
end
if ((up_fsm == ES_FSM_SCNT_RRDY) && (up_es_ready == 1'b1)) begin
up_sdata <= up_es_rdata;
end
if ((up_fsm == ES_FSM_ECNT_RRDY) && (up_es_ready == 1'b1)) begin
up_edata <= up_es_rdata;
end
end
end
// request, start and ack
assign up_start_s = up_es_req & ~up_req_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_req_d <= 1'b0;
up_ack <= 1'b0;
end else begin
up_req_d <= up_es_req;
if (up_fsm == ES_FSM_UPDATE) begin
up_ack <= up_eos_s | ~up_es_req;
end else begin
up_ack <= 1'b0;
end
end
end
// es-fsm
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_fsm <= ES_FSM_IDLE;
end else begin
case (up_fsm)
ES_FSM_IDLE: begin
if (up_start_s == 1'b1) begin
up_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_fsm <= ES_FSM_IDLE;
end
end
ES_FSM_HOFFSET_READ: begin
up_fsm <= ES_FSM_HOFFSET_RRDY;
end
ES_FSM_HOFFSET_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_HOFFSET_WRITE;
end else begin
up_fsm <= ES_FSM_HOFFSET_RRDY;
end
end
ES_FSM_HOFFSET_WRITE: begin
up_fsm <= ES_FSM_HOFFSET_WRDY;
end
ES_FSM_HOFFSET_WRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_VOFFSET_READ;
end else begin
up_fsm <= ES_FSM_HOFFSET_WRDY;
end
end
ES_FSM_VOFFSET_READ: begin
up_fsm <= ES_FSM_VOFFSET_RRDY;
end
ES_FSM_VOFFSET_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_VOFFSET_WRITE;
end else begin
up_fsm <= ES_FSM_VOFFSET_RRDY;
end
end
ES_FSM_VOFFSET_WRITE: begin
up_fsm <= ES_FSM_VOFFSET_WRDY;
end
ES_FSM_VOFFSET_WRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_CTRL_READ;
end else begin
up_fsm <= ES_FSM_VOFFSET_WRDY;
end
end
ES_FSM_CTRL_READ: begin
up_fsm <= ES_FSM_CTRL_RRDY;
end
ES_FSM_CTRL_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_START_WRITE;
end else begin
up_fsm <= ES_FSM_CTRL_RRDY;
end
end
ES_FSM_START_WRITE: begin
up_fsm <= ES_FSM_START_WRDY;
end
ES_FSM_START_WRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_STATUS_READ;
end else begin
up_fsm <= ES_FSM_START_WRDY;
end
end
ES_FSM_STATUS_READ: begin
up_fsm <= ES_FSM_STATUS_RRDY;
end
ES_FSM_STATUS_RRDY: begin
if (up_es_ready == 1'b0) begin
up_fsm <= ES_FSM_STATUS_RRDY;
end else if (up_es_rdata[3:0] == 4'b0101) begin
up_fsm <= ES_FSM_STOP_WRITE;
end else begin
up_fsm <= ES_FSM_STATUS_READ;
end
end
ES_FSM_STOP_WRITE: begin
up_fsm <= ES_FSM_STOP_WRDY;
end
ES_FSM_STOP_WRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_SCNT_READ;
end else begin
up_fsm <= ES_FSM_STOP_WRDY;
end
end
ES_FSM_SCNT_READ: begin
up_fsm <= ES_FSM_SCNT_RRDY;
end
ES_FSM_SCNT_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_ECNT_READ;
end else begin
up_fsm <= ES_FSM_SCNT_RRDY;
end
end
ES_FSM_ECNT_READ: begin
up_fsm <= ES_FSM_ECNT_RRDY;
end
ES_FSM_ECNT_RRDY: begin
if (up_es_ready == 1'b1) begin
up_fsm <= ES_FSM_AXI_WRITE;
end else begin
up_fsm <= ES_FSM_ECNT_RRDY;
end
end
ES_FSM_AXI_WRITE: begin
up_fsm <= ES_FSM_AXI_READY;
end
ES_FSM_AXI_READY: begin
if (up_axi_bvalid == 1'b1) begin
up_fsm <= ES_FSM_UPDATE;
end else begin
up_fsm <= ES_FSM_AXI_READY;
end
end
ES_FSM_UPDATE: begin
if ((up_eos_s == 1'b1) || (up_es_req == 1'b0)) begin
up_fsm <= ES_FSM_IDLE;
end else if (up_ut == 1'b1) begin
up_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_fsm <= ES_FSM_VOFFSET_READ;
end
end
default: begin
up_fsm <= ES_FSM_IDLE;
end
endcase
end
end
// channel access
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_enb <= 'd0;
up_addr <= 'd0;
up_wr <= 'd0;
up_data <= 'd0;
end else begin
case (up_fsm)
ES_FSM_HOFFSET_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_HOFFSET_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_HOFFSET_WRITE: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_HOFFSET_ADDR;
up_wr <= 1'b1;
if (GTH_OR_GTX_N == 1) begin
up_data <= {up_hindex, up_hdata[3:0]};
end else begin
up_data <= {up_hdata[15:12], up_hindex};
end
end
ES_FSM_VOFFSET_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_VOFFSET_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_VOFFSET_WRITE: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_VOFFSET_ADDR;
up_wr <= 1'b1;
if (GTH_OR_GTX_N == 1) begin
up_data <= {up_vdata[15:11], up_vindex_s[7], up_ut_s, up_vindex_s[6:0], up_es_vrange};
end else begin
up_data <= {up_es_pscale, up_vdata[10:9], up_ut_s, up_vindex_s};
end
end
ES_FSM_CTRL_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_CTRL_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_START_WRITE: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_CTRL_ADDR;
up_wr <= 1'b1;
if (GTH_OR_GTX_N == 1) begin
up_data <= {6'd1, 2'b11, up_cdata[7:5], up_es_pscale};
end else begin
up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd1};
end
end
ES_FSM_STATUS_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_STATUS_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_STOP_WRITE: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_CTRL_ADDR;
up_wr <= 1'b1;
if (GTH_OR_GTX_N == 1) begin
up_data <= {6'd0, 2'b11, up_cdata[7:5], up_es_pscale};
end else begin
up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd0};
end
end
ES_FSM_SCNT_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_SCNT_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
ES_FSM_ECNT_READ: begin
up_enb <= 1'b1;
up_addr <= ES_DRP_ECNT_ADDR;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
default: begin
up_enb <= 1'b0;
up_addr <= 9'h000;
up_wr <= 1'b0;
up_data <= 16'h0000;
end
endcase
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_adxcvr/axi_adxcvr_ip.tcl Normal file
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## AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY!
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_adxcvr
adi_ip_files axi_adxcvr [list \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_adxcvr_es.v" \
"axi_adxcvr_up.v" \
"axi_adxcvr_mdrp.v" \
"axi_adxcvr_mstatus.v" \
"axi_adxcvr.v" ]
adi_ip_properties_lite axi_adxcvr
ipx::remove_all_bus_interface [ipx::current_core]
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
ipx::infer_bus_interface {\
s_axi_awvalid \
s_axi_awaddr \
s_axi_awprot \
s_axi_awready \
s_axi_wvalid \
s_axi_wdata \
s_axi_wstrb \
s_axi_wready \
s_axi_bvalid \
s_axi_bresp \
s_axi_bready \
s_axi_arvalid \
s_axi_araddr \
s_axi_arprot \
s_axi_arready \
s_axi_rvalid \
s_axi_rdata \
s_axi_rresp \
s_axi_rready} \
xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface {\
m_axi_awvalid \
m_axi_awaddr \
m_axi_awprot \
m_axi_awready \
m_axi_wvalid \
m_axi_wdata \
m_axi_wstrb \
m_axi_wready \
m_axi_bvalid \
m_axi_bresp \
m_axi_bready \
m_axi_arvalid \
m_axi_araddr \
m_axi_arprot \
m_axi_arready \
m_axi_rvalid \
m_axi_rdata \
m_axi_rresp \
m_axi_rready} \
xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
-of_objects [ipx::current_core]]
set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces axi_clk \
-of_objects [ipx::current_core]]]
ipx::add_memory_map {s_axi} [ipx::current_core]
set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
set_property range {4096} [ipx::get_address_blocks axi_lite \
-of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
for {set n 0} {$n < 16} {incr n} {
if {($n%4) == 0} {
adi_if_infer_bus ADI:user:if_xcvr_cm master up_cm_${n} [list \
"sel up_cm_sel_${n} "\
"enb up_cm_enb_${n} "\
"addr up_cm_addr_${n} "\
"wr up_cm_wr_${n} "\
"wdata up_cm_wdata_${n} "\
"rdata up_cm_rdata_${n} "\
"ready up_cm_ready_${n} "]
}
adi_if_infer_bus ADI:user:if_xcvr_cm master up_es_${n} [list \
"sel up_es_sel_${n} "\
"enb up_es_enb_${n} "\
"addr up_es_addr_${n} "\
"wr up_es_wr_${n} "\
"wdata up_es_wdata_${n} "\
"rdata up_es_rdata_${n} "\
"ready up_es_ready_${n} "]
adi_if_infer_bus ADI:user:if_xcvr_ch master up_ch_${n} [list \
"pll_rst up_ch_pll_rst_${n} "\
"pll_locked up_ch_pll_locked_${n} "\
"rst up_ch_rst_${n} "\
"user_ready up_ch_user_ready_${n} "\
"rst_done up_ch_rst_done_${n} "\
"lpm_dfe_n up_ch_lpm_dfe_n_${n} "\
"rate up_ch_rate_${n} "\
"sys_clk_sel up_ch_sys_clk_sel_${n} "\
"out_clk_sel up_ch_out_clk_sel_${n} "\
"sel up_ch_sel_${n} "\
"enb up_ch_enb_${n} "\
"addr up_ch_addr_${n} "\
"wr up_ch_wr_${n} "\
"wdata up_ch_wdata_${n} "\
"rdata up_ch_rdata_${n} "\
"ready up_ch_ready_${n} "]
}
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
[ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces up_ch_0 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
[ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))} \
[ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces up_ch_1 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))} \
[ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces up_ch_2 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))} \
[ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces up_ch_3 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
[ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces up_ch_4 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
[ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))} \
[ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces up_ch_5 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))} \
[ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces up_ch_6 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))} \
[ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces up_ch_7 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
[ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces up_ch_8 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
[ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))} \
[ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces up_ch_9 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))} \
[ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces up_ch_10 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))} \
[ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces up_ch_11 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
[ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces up_ch_12 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
[ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))} \
[ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces up_ch_13 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))} \
[ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces up_ch_14 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))} \
[ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_adxcvr_mdrp (
input up_rstn,
input up_clk,
input [ 7:0] up_sel,
input up_enb,
input [15:0] up_rdata_in,
input up_ready_in,
input [15:0] up_rdata,
input up_ready,
output [15:0] up_rdata_out,
output up_ready_out);
// parameters
parameter integer XCVR_ID = 0;
// internal registers
reg up_ready_d = 'd0;
reg [15:0] up_rdata_int = 'd0;
reg up_ready_int = 'd0;
reg [15:0] up_rdata_m_in = 'd0;
reg up_ready_m_in = 'd0;
reg [15:0] up_rdata_m = 'd0;
reg up_ready_m = 'd0;
// internal signals
wire up_ready_s;
wire [15:0] up_rdata_m_s;
wire up_ready_m_s;
// disable if not selected
assign up_rdata_out = up_rdata_int;
assign up_ready_out = up_ready_int;
assign up_ready_s = up_ready_m & up_ready_m_in;
assign up_rdata_m_s = up_rdata_m | up_rdata_m_in;
assign up_ready_m_s = up_ready_s & ~up_ready_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_ready_d <= 1'd0;
up_rdata_int <= 16'd0;
up_ready_int <= 1'b0;
end else begin
up_ready_d <= up_ready_s;
case (up_sel)
8'hff: begin
up_rdata_int <= up_rdata_m_s;
up_ready_int <= up_ready_m_s;
end
XCVR_ID: begin
up_rdata_int <= up_rdata;
up_ready_int <= up_ready;
end
default: begin
up_rdata_int <= up_rdata_in;
up_ready_int <= up_ready_int;
end
endcase
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rdata_m_in <= 16'd0;
up_ready_m_in <= 1'b0;
up_rdata_m <= 16'd0;
up_ready_m <= 1'b0;
end else begin
if (up_ready_in == 1'b1) begin
up_rdata_m_in <= up_rdata_in;
up_ready_m_in <= 1'b1;
end else if (up_enb == 1'b1) begin
up_rdata_m_in <= 16'd0;
up_ready_m_in <= 1'b0;
end
if (up_ready == 1'b1) begin
up_rdata_m <= up_rdata;
up_ready_m <= 1'b1;
end else if (up_enb == 1'b1) begin
up_rdata_m <= 16'd0;
up_ready_m <= 1'b0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_adxcvr_mstatus (
input up_rstn,
input up_clk,
input up_pll_locked_in,
input up_rst_done_in,
input up_pll_locked,
input up_rst_done,
output up_pll_locked_out,
output up_rst_done_out);
// internal registers
reg up_pll_locked_int = 'd0;
reg up_rst_done_int = 'd0;
// daisy-chain the signals
assign up_pll_locked_out = up_pll_locked_int;
assign up_rst_done_out = up_rst_done_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_pll_locked_int <= 1'd0;
up_rst_done_int <= 1'd0;
end else begin
up_pll_locked_int <= up_pll_locked_in & up_pll_locked;
up_rst_done_int <= up_rst_done_in & up_rst_done;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_adxcvr/axi_adxcvr_up.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adxcvr_up (
// common
output [ 7:0] up_cm_sel,
output up_cm_enb,
output [11:0] up_cm_addr,
output up_cm_wr,
output [15:0] up_cm_wdata,
input [15:0] up_cm_rdata,
input up_cm_ready,
// channel
output up_ch_pll_rst,
input up_ch_pll_locked,
output up_ch_rst,
output up_ch_user_ready,
input up_ch_rst_done,
output up_ch_lpm_dfe_n,
output [ 2:0] up_ch_rate,
output [ 1:0] up_ch_sys_clk_sel,
output [ 2:0] up_ch_out_clk_sel,
output [ 7:0] up_ch_sel,
output up_ch_enb,
output [11:0] up_ch_addr,
output up_ch_wr,
output [15:0] up_ch_wdata,
input [15:0] up_ch_rdata,
input up_ch_ready,
// eye-scan
output [ 7:0] up_es_sel,
output up_es_req,
input up_es_ack,
output [ 4:0] up_es_pscale,
output [ 1:0] up_es_vrange,
output [ 7:0] up_es_vstep,
output [ 7:0] up_es_vmax,
output [ 7:0] up_es_vmin,
output [11:0] up_es_hmax,
output [11:0] up_es_hmin,
output [11:0] up_es_hstep,
output [31:0] up_es_saddr,
input up_es_status,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 9:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [ 9:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
localparam [31:0] VERSION = 32'h00100161;
parameter integer ID = 0;
parameter integer TX_OR_RX_N = 0;
parameter integer QPLL_ENABLE = 1;
// internal registers
reg up_wreq_d = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg [ 3:0] up_pll_rst_cnt = 'd0;
reg [ 3:0] up_rst_cnt = 'd0;
reg [ 6:0] up_user_ready_cnt = 'd0;
reg up_status = 'd0;
reg up_lpm_dfe_n = 'd0;
reg [ 2:0] up_rate = 'd0;
reg [ 1:0] up_sys_clk_sel = 'd0;
reg [ 2:0] up_out_clk_sel = 'd0;
reg [ 7:0] up_icm_sel = 'd0;
reg up_icm_enb = 'd0;
reg up_icm_wr = 'd0;
reg [11:0] up_icm_addr = 'd0;
reg [15:0] up_icm_wdata = 'd0;
reg [15:0] up_icm_rdata = 'd0;
reg up_icm_busy = 'd0;
reg [ 7:0] up_ich_sel = 'd0;
reg up_ich_enb = 'd0;
reg up_ich_wr = 'd0;
reg [11:0] up_ich_addr = 'd0;
reg [15:0] up_ich_wdata = 'd0;
reg [15:0] up_ich_rdata = 'd0;
reg up_ich_busy = 'd0;
reg [ 7:0] up_ies_sel = 'd0;
reg up_ies_req = 'd0;
reg [ 4:0] up_ies_prescale = 'd0;
reg [ 1:0] up_ies_voffset_range = 'd0;
reg [ 7:0] up_ies_voffset_step = 'd0;
reg [ 7:0] up_ies_voffset_max = 'd0;
reg [ 7:0] up_ies_voffset_min = 'd0;
reg [11:0] up_ies_hoffset_max = 'd0;
reg [11:0] up_ies_hoffset_min = 'd0;
reg [11:0] up_ies_hoffset_step = 'd0;
reg [31:0] up_ies_start_addr = 'd0;
reg up_ies_status = 'd0;
reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0;
// defaults
assign up_wack = up_wreq_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wreq_d <= 'd0;
up_scratch <= 'd0;
end else begin
up_wreq_d <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin
up_scratch <= up_wdata;
end
end
end
// reset-controller
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_resetn <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin
up_resetn <= up_wdata[0];
end
end
end
assign up_ch_pll_rst = up_pll_rst_cnt[3];
assign up_ch_rst = up_rst_cnt[3];
assign up_ch_user_ready = up_user_ready_cnt[6];
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_pll_rst_cnt <= 4'h8;
up_rst_cnt <= 4'h8;
up_user_ready_cnt <= 7'h00;
up_status <= 1'b0;
end else begin
if (up_resetn == 1'b0) begin
up_pll_rst_cnt <= 4'h8;
end else if (up_pll_rst_cnt[3] == 1'b1) begin
up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1;
end
if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) ||
(up_ch_pll_locked == 1'b0)) begin
up_rst_cnt <= 4'h8;
end else if (up_rst_cnt[3] == 1'b1) begin
up_rst_cnt <= up_rst_cnt + 1'b1;
end
if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin
up_user_ready_cnt <= 7'h00;
end else if (up_user_ready_cnt[6] == 1'b0) begin
up_user_ready_cnt <= up_user_ready_cnt + 1'b1;
end
if (up_resetn == 1'b0) begin
up_status <= 1'b0;
end else if (up_ch_rst_done == 1'b1) begin
up_status <= 1'b1;
end
end
end
// control signals
assign up_ch_lpm_dfe_n = up_lpm_dfe_n;
assign up_ch_rate = up_rate;
assign up_ch_sys_clk_sel = up_sys_clk_sel;
assign up_ch_out_clk_sel = up_out_clk_sel;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_lpm_dfe_n <= 'd0;
up_rate <= 'd0;
up_sys_clk_sel <= 'd0;
up_out_clk_sel <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin
up_lpm_dfe_n <= up_wdata[12];
up_rate <= up_wdata[10:8];
up_sys_clk_sel <= up_wdata[5:4];
up_out_clk_sel <= up_wdata[2:0];
end
end
end
// common access
assign up_cm_sel = up_icm_sel;
assign up_cm_enb = up_icm_enb;
assign up_cm_wr = up_icm_wr;
assign up_cm_addr = up_icm_addr;
assign up_cm_wdata = up_icm_wdata;
generate
if (QPLL_ENABLE == 0) begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_icm_sel <= 'd0;
up_icm_enb <= 'd0;
up_icm_wr <= 'd0;
up_icm_addr <= 'd0;
up_icm_wdata <= 'd0;
up_icm_rdata <= 'd0;
up_icm_busy <= 'd0;
end else begin
up_icm_sel <= 'd0;
up_icm_enb <= 'd0;
up_icm_wr <= 'd0;
up_icm_addr <= 'd0;
up_icm_wdata <= 'd0;
up_icm_rdata <= 'd0;
up_icm_busy <= 'd0;
end
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_icm_sel <= 'd0;
up_icm_enb <= 'd0;
up_icm_wr <= 'd0;
up_icm_addr <= 'd0;
up_icm_wdata <= 'd0;
up_icm_rdata <= 'd0;
up_icm_busy <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h010)) begin
up_icm_sel <= up_wdata[7:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
up_icm_enb <= 1'b1;
end else begin
up_icm_enb <= 1'b0;
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
up_icm_wr <= up_wdata[28];
up_icm_addr <= up_wdata[27:16];
up_icm_wdata <= up_wdata[15:0];
end
if (up_cm_ready == 1'b1) begin
up_icm_rdata <= up_cm_rdata;
up_icm_busy <= 1'b0;
end else if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin
up_icm_rdata <= 16'd0;
up_icm_busy <= 1'b1;
end
end
end
end
endgenerate
// channel access
assign up_ch_sel = up_ich_sel;
assign up_ch_enb = up_ich_enb;
assign up_ch_wr = up_ich_wr;
assign up_ch_addr = up_ich_addr;
assign up_ch_wdata = up_ich_wdata;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ich_sel <= 'd0;
up_ich_enb <= 'd0;
up_ich_wr <= 'd0;
up_ich_addr <= 'd0;
up_ich_wdata <= 'd0;
up_ich_rdata <= 'd0;
up_ich_busy <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h018)) begin
up_ich_sel <= up_wdata[7:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
up_ich_enb <= 1'b1;
end else begin
up_ich_enb <= 1'b0;
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
up_ich_wr <= up_wdata[28];
up_ich_addr <= up_wdata[27:16];
up_ich_wdata <= up_wdata[15:0];
end
if (up_ch_ready == 1'b1) begin
up_ich_rdata <= up_ch_rdata;
up_ich_busy <= 1'b0;
end else if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin
up_ich_rdata <= 16'd0;
up_ich_busy <= 1'b1;
end
end
end
// eye-scan
assign up_es_sel = up_ies_sel;
assign up_es_req = up_ies_req;
assign up_es_pscale = up_ies_prescale;
assign up_es_vrange = up_ies_voffset_range;
assign up_es_vstep = up_ies_voffset_step;
assign up_es_vmax = up_ies_voffset_max;
assign up_es_vmin = up_ies_voffset_min;
assign up_es_hmax = up_ies_hoffset_max;
assign up_es_hmin = up_ies_hoffset_min;
assign up_es_hstep = up_ies_hoffset_step;
assign up_es_saddr = up_ies_start_addr;
generate
if (TX_OR_RX_N == 1) begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ies_sel <= 'd0;
up_ies_req <= 'd0;
up_ies_prescale <= 'd0;
up_ies_voffset_range <= 'd0;
up_ies_voffset_step <= 'd0;
up_ies_voffset_max <= 'd0;
up_ies_voffset_min <= 'd0;
up_ies_hoffset_max <= 'd0;
up_ies_hoffset_min <= 'd0;
up_ies_hoffset_step <= 'd0;
up_ies_start_addr <= 'd0;
up_ies_status <= 'd0;
end else begin
up_ies_sel <= 'd0;
up_ies_req <= 'd0;
up_ies_prescale <= 'd0;
up_ies_voffset_range <= 'd0;
up_ies_voffset_step <= 'd0;
up_ies_voffset_max <= 'd0;
up_ies_voffset_min <= 'd0;
up_ies_hoffset_max <= 'd0;
up_ies_hoffset_min <= 'd0;
up_ies_hoffset_step <= 'd0;
up_ies_start_addr <= 'd0;
up_ies_status <= 'd0;
end
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ies_sel <= 'd0;
up_ies_req <= 'd0;
up_ies_prescale <= 'd0;
up_ies_voffset_range <= 'd0;
up_ies_voffset_step <= 'd0;
up_ies_voffset_max <= 'd0;
up_ies_voffset_min <= 'd0;
up_ies_hoffset_max <= 'd0;
up_ies_hoffset_min <= 'd0;
up_ies_hoffset_step <= 'd0;
up_ies_start_addr <= 'd0;
up_ies_status <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h020)) begin
up_ies_sel <= up_wdata[7:0];
end
if (up_es_ack == 1'b1) begin
up_ies_req <= 1'b0;
end else if ((up_wreq == 1'b1) && (up_waddr == 10'h028)) begin
up_ies_req <= up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h029)) begin
up_ies_prescale <= up_wdata[4:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02a)) begin
up_ies_voffset_range <= up_wdata[25:24];
up_ies_voffset_step <= up_wdata[23:16];
up_ies_voffset_max <= up_wdata[15:8];
up_ies_voffset_min <= up_wdata[7:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02b)) begin
up_ies_hoffset_max <= up_wdata[27:16];
up_ies_hoffset_min <= up_wdata[11:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02c)) begin
up_ies_hoffset_step <= up_wdata[11:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h02d)) begin
up_ies_start_addr <= up_wdata;
end
if (up_es_status == 1'b1) begin
up_ies_status <= 1'b1;
end else if ((up_wreq == 1'b1) && (up_waddr == 10'h02e)) begin
up_ies_status <= up_ies_status & ~up_wdata[0];
end
end
end
end
endgenerate
// read interface
assign up_rack = up_rreq_d;
assign up_rdata = up_rdata_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rreq_d <= 'd0;
up_rdata_d <= 'd0;
end else begin
up_rreq_d <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr)
10'h000: up_rdata_d <= VERSION;
10'h001: up_rdata_d <= ID;
10'h002: up_rdata_d <= up_scratch;
10'h004: up_rdata_d <= {31'd0, up_resetn};
10'h005: up_rdata_d <= {31'd0, up_status};
10'h008: up_rdata_d <= {19'd0, up_lpm_dfe_n, 1'd0, up_rate, 2'd0, up_sys_clk_sel, 1'd0, up_out_clk_sel};
10'h010: up_rdata_d <= {24'd0, up_icm_sel};
10'h011: up_rdata_d <= {3'd0, up_icm_wr, up_icm_addr, up_icm_wdata};
10'h012: up_rdata_d <= {15'd0, up_icm_busy, up_icm_rdata};
10'h018: up_rdata_d <= {24'd0, up_ich_sel};
10'h019: up_rdata_d <= {3'd0, up_ich_wr, up_ich_addr, up_ich_wdata};
10'h01a: up_rdata_d <= {15'd0, up_ich_busy, up_ich_rdata};
10'h020: up_rdata_d <= {24'd0, up_ies_sel};
10'h028: up_rdata_d <= {31'd0, up_ies_req};
10'h029: up_rdata_d <= {27'd0, up_ies_prescale};
10'h02a: up_rdata_d <= {6'd0, up_ies_voffset_range, up_ies_voffset_step, up_ies_voffset_max, up_ies_voffset_min};
10'h02b: up_rdata_d <= {4'd0, up_ies_hoffset_max, 4'd0, up_ies_hoffset_min};
10'h02c: up_rdata_d <= {20'd0, up_ies_hoffset_step};
10'h02d: up_rdata_d <= up_ies_start_addr;
10'h02e: up_rdata_d <= {31'd0, up_es_status};
default: up_rdata_d <= 32'd0;
endcase
end else begin
up_rdata_d <= 32'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************