library: Adding axi_clock_monitor ip core
AndrDragomir
AndrDragomir
parent
459704d183
commit
204dff3b73
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@ -39,6 +39,7 @@ clean:
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$(MAKE) -C axi_adrv9001 clean
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$(MAKE) -C axi_adrv9001 clean
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$(MAKE) -C axi_adrv9009 clean
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$(MAKE) -C axi_adrv9009 clean
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$(MAKE) -C axi_clkgen clean
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$(MAKE) -C axi_clkgen clean
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$(MAKE) -C axi_clock_monitor clean
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$(MAKE) -C axi_dac_interpolate clean
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$(MAKE) -C axi_dac_interpolate clean
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$(MAKE) -C axi_dmac clean
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$(MAKE) -C axi_dmac clean
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$(MAKE) -C axi_fan_control clean
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$(MAKE) -C axi_fan_control clean
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@ -165,6 +166,7 @@ lib:
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$(MAKE) -C axi_adrv9001
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$(MAKE) -C axi_adrv9001
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$(MAKE) -C axi_adrv9009
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$(MAKE) -C axi_adrv9009
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$(MAKE) -C axi_clkgen
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$(MAKE) -C axi_clkgen
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$(MAKE) -C axi_clock_monitor
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$(MAKE) -C axi_dac_interpolate
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$(MAKE) -C axi_dac_interpolate
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$(MAKE) -C axi_dmac
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$(MAKE) -C axi_dmac
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$(MAKE) -C axi_fan_control
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$(MAKE) -C axi_fan_control
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@ -0,0 +1,20 @@
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_clock_monitor
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += axi_clock_monitor.v
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XILINX_DEPS += ../common/up_clock_mon.v
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XILINX_DEPS += axi_clock_monitor_constr.xdc
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XILINX_DEPS += axi_clock_monitor_ip.tcl
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INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
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INTEL_DEPS += ../intel/common/up_rst_constr.sdc
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INTEL_DEPS += axi_clock_monitor_hw.tcl
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include ../scripts/library.mk
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@ -0,0 +1 @@
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https://wiki.analog.com/resources/fpga/docs/axi_clock_monitor
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@ -0,0 +1,271 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_clock_monitor #(
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parameter ID = 0,
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parameter NUM_OF_CLOCKS = 1) (
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// clocks
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input clock_0,
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input clock_1,
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input clock_2,
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input clock_3,
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input clock_4,
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input clock_5,
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input clock_6,
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input clock_7,
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input clock_8,
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input clock_9,
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input clock_10,
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input clock_11,
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input clock_12,
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input clock_13,
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input clock_14,
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input clock_15,
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output reset,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// local parameters
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localparam PCORE_VERSION = 1
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// internal registers
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reg pass = 'd0;
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reg up_wack_int = 'd0;
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reg up_rack_int = 'd0;
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reg up_scratch = 'd0;
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reg up_reset_core = 'd0;
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reg [31:0] up_rdata_int = 'd0;
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire up_wreq_s;
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wire up_rreq_s;
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wire up_waddr_s;
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wire up_raddr_s;
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wire clock [0:15];
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wire [20:0] clk_mon_count [0:15];
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wire up_wreq_i_s;
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wire [(PROC_ADDR_WD-1):0] up_waddr_i_s;
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wire [31:0] up_wdata_i_s;
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wire up_wack_o_s;
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wire up_rreq_i_s;
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wire [(PROC_ADDR_WD-1):0] up_raddr_i_s;
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wire [31:0] up_rdata_o_s;
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wire up_rack_o_s;
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// loop variables
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genvar n;
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generate
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assign clock[0 ] = clock_0;
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assign clock[1 ] = clock_1;
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assign clock[2 ] = clock_2;
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assign clock[3 ] = clock_3;
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assign clock[4 ] = clock_4;
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assign clock[5 ] = clock_5;
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assign clock[6 ] = clock_6;
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assign clock[7 ] = clock_7;
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assign clock[8 ] = clock_8;
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assign clock[9 ] = clock_9;
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assign clock[10] = clock_10;
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assign clock[11] = clock_11;
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assign clock[12] = clock_12;
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assign clock[13] = clock_13;
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assign clock[14] = clock_14;
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assign clock[15] = clock_15;
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endgenerate
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign reset = up_reset_core;
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// decode block select
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assign up_wreq_s = (up_waddr_i_s[13:8] == ID) ? up_wreq_i_s : 1'b0;
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assign up_rreq_s = (up_raddr_i_s[13:8] == ID) ? up_rreq_i_s : 1'b0;
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// processor write interface
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assign up_wack_o_s = up_wack_int;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack_int <= 'd0;
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up_reset_core <= 'd0;
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end else begin
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up_wack_int <= up_wreq_s;
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if (up_wreq_s == 1'b1) begin
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case (up_waddr_i_s[7:0])
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8'h004: up_reset_core <= up_wdata_i_s[0];
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default: pass <= 1'h0;
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endcase
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end
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end
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end
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// processor read interface
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assign up_rack_o_s = up_rack_int;
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assign up_rdata_o_s = up_rdata_int;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack_int <= 'd0;
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up_rdata_int <= 'd0;
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end else begin
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up_rack_int <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr_i_s)
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/* Standard registers */
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12'h000: up_rdata_int <= PCORE_VERSION;
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12'h001: up_rdata_int <= ID;
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/* Core configuration */
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12'h003: up_rdata_int <= NUM_OF_CLOCKS;
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12'h004: up_rdata_int <= up_reset_core;
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/* Clock ratios registers*/
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12'h010: up_rdata_int <= {11'h00, clk_mon_count[ 0]}; /* Make it 16.16 */
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12'h011: up_rdata_int <= {11'h00, clk_mon_count[ 1]}; /* Make it 16.16 */
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12'h012: up_rdata_int <= {11'h00, clk_mon_count[ 2]}; /* Make it 16.16 */
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12'h013: up_rdata_int <= {11'h00, clk_mon_count[ 3]}; /* Make it 16.16 */
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12'h014: up_rdata_int <= {11'h00, clk_mon_count[ 4]}; /* Make it 16.16 */
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12'h015: up_rdata_int <= {11'h00, clk_mon_count[ 5]}; /* Make it 16.16 */
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12'h016: up_rdata_int <= {11'h00, clk_mon_count[ 6]}; /* Make it 16.16 */
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12'h017: up_rdata_int <= {11'h00, clk_mon_count[ 7]}; /* Make it 16.16 */
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12'h018: up_rdata_int <= {11'h00, clk_mon_count[ 8]}; /* Make it 16.16 */
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12'h019: up_rdata_int <= {11'h00, clk_mon_count[ 9]}; /* Make it 16.16 */
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12'h01a: up_rdata_int <= {11'h00, clk_mon_count[10]}; /* Make it 16.16 */
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12'h01b: up_rdata_int <= {11'h00, clk_mon_count[11]}; /* Make it 16.16 */
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12'h01c: up_rdata_int <= {11'h00, clk_mon_count[12]}; /* Make it 16.16 */
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12'h01d: up_rdata_int <= {11'h00, clk_mon_count[13]}; /* Make it 16.16 */
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12'h01e: up_rdata_int <= {11'h00, clk_mon_count[14]}; /* Make it 16.16 */
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12'h01f: up_rdata_int <= {11'h00, clk_mon_count[15]}; /* Make it 16.16 */
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default: up_rdata_int <= 'h00;
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endcase
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end
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end
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end
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// clock monitors
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generate
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for (n = 0; n < NUM_OF_CLOCKS; n = n + 1) begin: clk_mon
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up_clock_mon #(
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.TOTAL_WIDTH(21)
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) i_clock_mon (
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.up_rstn(~up_reset_core),
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.up_clk(up_clk),
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.up_d_count(clk_mon_count[n]),
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.d_rst(1'b0),
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.d_clk(clock[n])
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);
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end
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for (n = NUM_OF_CLOCKS; n < 16; n = n + 1) begin: clk_mon_z
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assign clk_mon_count[n] = 20'd0;
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end
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endgenerate
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// axi interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_i_s),
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.up_waddr (up_waddr_i_s),
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.up_wdata (up_wdata_i_s),
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.up_wack (up_wack_o_s),
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.up_rreq (up_rreq_i_s),
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.up_raddr (up_raddr_i_s),
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.up_rdata (up_rdata_o_s),
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.up_rack (up_rack_o_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,41 @@
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package require qsys
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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ad_ip_create axi_clock_monitor {axi_clock_monitor} p_axi_clock_monitor
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# files
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set_module_property NAME axi_clock_monitor
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ad_ip_files axi_clock_monitor [list \
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$ad_hdl_dir/library/common/up_axi.v \
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$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
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$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
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axi_clock_monitor.v \
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]
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# parameters
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add_parameter NUM_OF_CLOCKS INTEGER 0
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set_parameter_property NUM_OF_CLOCKS DEFAULT_VALUE 8
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set_parameter_property NUM_OF_CLOCKS DISPLAY_NAME NUM_OF_CLOCKS
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set_parameter_property NUM_OF_CLOCKS UNITS None
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set_parameter_property NUM_OF_CLOCKS HDL_PARAMETER true
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# interfaces
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
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ad_interface reset output 1 if_reset
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proc p_axi_clock_monitor {} {
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set num_of_clock [get_parameter_value NUM_OF_CLOCKS]
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|
for {set n 0} {$n < $num_of_clock} {incr n} {
|
||||||
|
ad_interface clock clock_${n} input 1
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,52 @@
|
||||||
|
# ip
|
||||||
|
|
||||||
|
source ../scripts/adi_env.tcl
|
||||||
|
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||||
|
|
||||||
|
adi_ip_create axi_clock_monitor
|
||||||
|
adi_ip_files axi_clock_monitor [list \
|
||||||
|
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||||
|
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||||
|
"axi_clock_monitor.v" \
|
||||||
|
"axi_clock_monitor_constr.xdc" ]
|
||||||
|
|
||||||
|
adi_ip_properties axi_clock_monitor
|
||||||
|
|
||||||
|
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_clock_monitor} [ipx::current_core]
|
||||||
|
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 1} \
|
||||||
|
[ipx::get_ports *_1* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 2} \
|
||||||
|
[ipx::get_ports *_2* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 3} \
|
||||||
|
[ipx::get_ports *_3* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 4} \
|
||||||
|
[ipx::get_ports *_4* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 5} \
|
||||||
|
[ipx::get_ports *_5* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 6} \
|
||||||
|
[ipx::get_ports *_6* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 7} \
|
||||||
|
[ipx::get_ports *_7* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 8 } \
|
||||||
|
[ipx::get_ports *_8* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 9 } \
|
||||||
|
[ipx::get_ports *_9* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 10} \
|
||||||
|
[ipx::get_ports *_10* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 11} \
|
||||||
|
[ipx::get_ports *_11* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 12} \
|
||||||
|
[ipx::get_ports *_12* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 13} \
|
||||||
|
[ipx::get_ports *_13* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 14} \
|
||||||
|
[ipx::get_ports *_14* -of_objects [ipx::current_core]]
|
||||||
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 15} \
|
||||||
|
[ipx::get_ports *_15* -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||||
|
|
||||||
|
ipx::save_core [ipx::current_core]
|
||||||
|
|
||||||
|
|
||||||
Loading…
Reference in New Issue