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ad77681: Add axi_clkgen ip for spi engine 

spi_clk changed from 40MHz to 80MHz
main
Sergiu Arpadi 2020-10-16 17:03:05 +01:00 committed by sarpadi
parent d6b23d5149
commit 1f6bba0aa1
1 changed files with 15 additions and 11 deletions
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18
projects/ad77681evb/common/ad77681evb_bd.tcl
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@ -3,6 +3,12 @@ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 a
create_bd_port -dir I adc_data_ready
ad_ip_instance axi_clkgen spi_clkgen
ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 10
ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
ad_connect sys_cpu_clk spi_clkgen/clk
# create a SPI Engine architecture for ADC
create_bd_cell -type hier spi_adc
@ -77,13 +83,9 @@ ad_ip_parameter axi_ad77681_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad77681_dma CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_parameter axi_ad77681_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1
ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST2_PORT 1
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 40.0
ad_connect sys_40m_clk sys_ps7/FCLK_CLK2
ad_connect sys_cpu_clk spi_adc/clk
ad_connect sys_40m_clk spi_adc/spi_clk
ad_connect spi_adc/spi_clk spi_clkgen/clk_0
ad_connect sys_cpu_resetn spi_adc/resetn
ad_connect sys_cpu_resetn axi_ad77681_dma/m_dest_axi_aresetn
@ -94,8 +96,9 @@ ad_connect axi_ad77681_dma/s_axis spi_adc/M_AXIS_SAMPLE
ad_cpu_interconnect 0x44a00000 spi_adc/axi_regmap
ad_cpu_interconnect 0x44a30000 axi_ad77681_dma
ad_cpu_interconnect 0x44a70000 spi_clkgen
ad_connect sys_40m_clk axi_ad77681_dma/s_axis_aclk
ad_connect spi_adc/spi_clk axi_ad77681_dma/s_axis_aclk
# interrupts
@ -106,3 +109,4 @@ ad_cpu_interrupt "ps-11" "mb-11" spi_adc/irq
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
ad_mem_hp2_interconnect sys_cpu_clk axi_ad77681_dma/m_dest_axi