From 1f6bba0aa19da0b3f23119761642222c026fb883 Mon Sep 17 00:00:00 2001 From: Sergiu Arpadi Date: Fri, 16 Oct 2020 17:03:05 +0100 Subject: [PATCH] ad77681: Add axi_clkgen ip for spi engine spi_clk changed from 40MHz to 80MHz --- projects/ad77681evb/common/ad77681evb_bd.tcl | 26 +++++++++++--------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/projects/ad77681evb/common/ad77681evb_bd.tcl b/projects/ad77681evb/common/ad77681evb_bd.tcl index 18c171f7f..364a10665 100644 --- a/projects/ad77681evb/common/ad77681evb_bd.tcl +++ b/projects/ad77681evb/common/ad77681evb_bd.tcl @@ -3,6 +3,12 @@ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 a create_bd_port -dir I adc_data_ready +ad_ip_instance axi_clkgen spi_clkgen +ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 10 +ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8 +ad_connect sys_cpu_clk spi_clkgen/clk + # create a SPI Engine architecture for ADC create_bd_cell -type hier spi_adc @@ -34,13 +40,13 @@ current_bd_instance /spi_adc ad_ip_instance spi_engine_interconnect interconnect ad_ip_parameter interconnect CONFIG.DATA_WIDTH 32 - + ad_connect axi_regmap/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl ad_connect axi_regmap/spi_engine_ctrl interconnect/s1_ctrl ad_connect interconnect/m_ctrl execution/ctrl ad_connect offload/offload_sdi M_AXIS_SAMPLE - + ad_connect execution/spi m_spi ad_connect spi_clk offload/spi_clk @@ -49,11 +55,11 @@ current_bd_instance /spi_adc ad_connect clk axi_regmap/s_axi_aclk ad_connect spi_clk axi_regmap/spi_clk ad_connect spi_clk interconnect/clk - + ad_connect axi_regmap/spi_resetn offload/spi_resetn ad_connect axi_regmap/spi_resetn execution/resetn ad_connect axi_regmap/spi_resetn interconnect/resetn - + ad_connect drdy offload/trigger ad_connect resetn axi_regmap/s_axi_aresetn @@ -77,13 +83,9 @@ ad_ip_parameter axi_ad77681_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad77681_dma CONFIG.DMA_DATA_WIDTH_SRC 32 ad_ip_parameter axi_ad77681_dma CONFIG.DMA_DATA_WIDTH_DEST 64 -ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1 -ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST2_PORT 1 -ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 40.0 -ad_connect sys_40m_clk sys_ps7/FCLK_CLK2 - ad_connect sys_cpu_clk spi_adc/clk -ad_connect sys_40m_clk spi_adc/spi_clk +ad_connect spi_adc/spi_clk spi_clkgen/clk_0 + ad_connect sys_cpu_resetn spi_adc/resetn ad_connect sys_cpu_resetn axi_ad77681_dma/m_dest_axi_aresetn @@ -94,8 +96,9 @@ ad_connect axi_ad77681_dma/s_axis spi_adc/M_AXIS_SAMPLE ad_cpu_interconnect 0x44a00000 spi_adc/axi_regmap ad_cpu_interconnect 0x44a30000 axi_ad77681_dma +ad_cpu_interconnect 0x44a70000 spi_clkgen -ad_connect sys_40m_clk axi_ad77681_dma/s_axis_aclk +ad_connect spi_adc/spi_clk axi_ad77681_dma/s_axis_aclk # interrupts @@ -106,3 +109,4 @@ ad_cpu_interrupt "ps-11" "mb-11" spi_adc/irq ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0 ad_mem_hp2_interconnect sys_cpu_clk axi_ad77681_dma/m_dest_axi +