util_dacfifo: Update read out method

Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
main
Istvan Csomortani 2015-10-08 16:50:36 +03:00
parent 5e082be963
commit 1ebd38c514
1 changed files with 6 additions and 2 deletions

View File

@ -112,7 +112,7 @@ module util_dacfifo (
always @(posedge dma_clk) begin always @(posedge dma_clk) begin
if(dma_rst == 1'b1) begin if(dma_rst == 1'b1) begin
dma_waddr <= 'b0; dma_waddr <= 'b0;
dma_lastaddr <= {ADDR_WIDTH{1'b1}}; dma_lastaddr <= 'b0;
end else begin end else begin
if (dma_valid && dma_xfer_req) begin if (dma_valid && dma_xfer_req) begin
dma_waddr <= dma_waddr + 1; dma_waddr <= dma_waddr + 1;
@ -137,7 +137,11 @@ module util_dacfifo (
// generate dac read address // generate dac read address
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
if(dac_valid == 1'b1) begin if(dac_valid == 1'b1) begin
dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0; if (dma_lastaddr_2d == 'h0) begin
dac_raddr <= dac_raddr + 1;
end else begin
dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
end
end end
dac_data <= dac_data_s; dac_data <= dac_data_s;
end end