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kcu105- axi-interconnect register slices

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Rejeesh Kutty 2016-12-02 11:54:04 -05:00
parent a728739807
commit 1e7ab4d708
1 changed files with 2 additions and 0 deletions
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projects/common/kcu105/kcu105_system_bd.tcl
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@ -255,6 +255,8 @@ ad_cpu_interconnect 0x44A70000 axi_spi
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddr_interconnect create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddr_interconnect
set_property CONFIG.NUM_MI {1} [get_bd_cells axi_ddr_interconnect] set_property CONFIG.NUM_MI {1} [get_bd_cells axi_ddr_interconnect]
set_property CONFIG.NUM_SI {1} [get_bd_cells axi_ddr_interconnect] set_property CONFIG.NUM_SI {1} [get_bd_cells axi_ddr_interconnect]
set_property CONFIG.S00_HAS_REGSLICE {4} [get_bd_cells axi_ddr_interconnect]
set_property CONFIG.S00_HAS_DATA_FIFO {1} [get_bd_cells axi_ddr_interconnect]
ad_connect axi_ddr_interconnect/M00_AXI axi_ddr_cntrl/C0_DDR4_S_AXI ad_connect axi_ddr_interconnect/M00_AXI axi_ddr_cntrl/C0_DDR4_S_AXI
ad_connect sys_mem_clk axi_ddr_interconnect/ACLK ad_connect sys_mem_clk axi_ddr_interconnect/ACLK