From 1e7ab4d708a79b4baa878756f4482aa27719f69b Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 2 Dec 2016 11:54:04 -0500 Subject: [PATCH] kcu105- axi-interconnect register slices --- projects/common/kcu105/kcu105_system_bd.tcl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 873e206a3..715b597e0 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -255,6 +255,8 @@ ad_cpu_interconnect 0x44A70000 axi_spi create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddr_interconnect set_property CONFIG.NUM_MI {1} [get_bd_cells axi_ddr_interconnect] set_property CONFIG.NUM_SI {1} [get_bd_cells axi_ddr_interconnect] +set_property CONFIG.S00_HAS_REGSLICE {4} [get_bd_cells axi_ddr_interconnect] +set_property CONFIG.S00_HAS_DATA_FIFO {1} [get_bd_cells axi_ddr_interconnect] ad_connect axi_ddr_interconnect/M00_AXI axi_ddr_cntrl/C0_DDR4_S_AXI ad_connect sys_mem_clk axi_ddr_interconnect/ACLK