zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

adi_util_hbm.tcl: Change wrong var name rx_tx_n->tx_rx_n 

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
main
Iulia Moldovan 2024-01-09 11:25:44 +02:00 committed by imoldovan
parent 608044d124
commit 1e4dc519fc
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
library/util_hbm/scripts/adi_util_hbm.tcl
View File

@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@ -33,12 +33,12 @@ proc ad_create_hbm {ip_name {density "4GB"}} {
}
}
proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} {
proc ad_create_util_hbm {name tx_rx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} {
if {$mem_type == 2} {
# HBM
# split converter side bus into multiple AXI masters
set number_of_masters [expr int(ceil((${rx_tx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))]
set number_of_masters [expr int(ceil((${tx_rx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))]
} else {
# DDR we have always one master
set number_of_masters 1
@ -49,7 +49,7 @@ proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_wid
SRC_DATA_WIDTH $src_width \
DST_DATA_WIDTH $dst_width \
AXI_DATA_WIDTH $axi_data_width \
TX_RX_N $rx_tx_n \
TX_RX_N $tx_rx_n \
NUM_M $number_of_masters \
MEM_TYPE $mem_type \
]