From 1e4dc519fcbd2fef895560e7611c10bb48c1ffc8 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Tue, 9 Jan 2024 11:25:44 +0200 Subject: [PATCH] adi_util_hbm.tcl: Change wrong var name rx_tx_n->tx_rx_n Signed-off-by: Iulia Moldovan --- library/util_hbm/scripts/adi_util_hbm.tcl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/library/util_hbm/scripts/adi_util_hbm.tcl b/library/util_hbm/scripts/adi_util_hbm.tcl index 45ddb3a0c..1479bb0c0 100644 --- a/library/util_hbm/scripts/adi_util_hbm.tcl +++ b/library/util_hbm/scripts/adi_util_hbm.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -33,12 +33,12 @@ proc ad_create_hbm {ip_name {density "4GB"}} { } } -proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} { +proc ad_create_util_hbm {name tx_rx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} { if {$mem_type == 2} { # HBM # split converter side bus into multiple AXI masters - set number_of_masters [expr int(ceil((${rx_tx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))] + set number_of_masters [expr int(ceil((${tx_rx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))] } else { # DDR we have always one master set number_of_masters 1 @@ -49,7 +49,7 @@ proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_wid SRC_DATA_WIDTH $src_width \ DST_DATA_WIDTH $dst_width \ AXI_DATA_WIDTH $axi_data_width \ - TX_RX_N $rx_tx_n \ + TX_RX_N $tx_rx_n \ NUM_M $number_of_masters \ MEM_TYPE $mem_type \ ]