zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

alt_serdes- a10 ddio fixes

main
Rejeesh Kutty 2016-11-01 12:40:48 -04:00
parent 671a547c2b
commit 1e0fed82f7
4 changed files with 19 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
library/altera/alt_serdes/alt_serdes_hw.tcl
View File

@ -64,24 +64,34 @@ proc p_alt_serdes {} {
set m_ld_duty_cycle 25.0 set m_ld_duty_cycle 25.0
} }
## arria 10, serdes clock, data-in and data-out ## arria 10, cmos data-in and data-out
if {($m_serdes_factor == 2) && ($m_device_family == "Arria 10")} { if {($m_serdes_factor == 2) && ($m_device_family == "Arria 10")} {
add_hdl_instance alt_serdes_out altera_gpio add_instance alt_serdes_out altera_gpio
set_instance_parameter_value alt_serdes_out {PIN_TYPE_GUI} {Output} set_instance_parameter_value alt_serdes_out {PIN_TYPE_GUI} {Output}
set_instance_parameter_value alt_serdes_out {SIZE} {1} set_instance_parameter_value alt_serdes_out {SIZE} {1}
set_instance_parameter_value alt_serdes_out {gui_diff_buff} {0} set_instance_parameter_value alt_serdes_out {gui_diff_buff} {0}
set_instance_parameter_value alt_serdes_out {gui_io_reg_mode} {DDIO} set_instance_parameter_value alt_serdes_out {gui_io_reg_mode} {DDIO}
add_interface clk conduit end
set_interface_property clk EXPORT_OF alt_serdes_out.ck
add_interface din conduit end
set_interface_property din EXPORT_OF alt_serdes_out.din
add_interface pad_out conduit end
set_interface_property pad_out EXPORT_OF alt_serdes_out.pad_out
return return
} }
## cyclone v, cmos data-in and data-out
if {($m_serdes_factor == 2) && ($m_device_family == "Cyclone V")} { if {($m_serdes_factor == 2) && ($m_device_family == "Cyclone V")} {
return return
} }
## arria 10, serdes clock, data-in and data-out
if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} { if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} {
add_instance alt_serdes_pll altera_iopll add_instance alt_serdes_pll altera_iopll

6
library/altera/common/ad_cmos_out.v
View File

@ -80,9 +80,9 @@ module __ad_cmos_out__ #(
generate generate
if (DEVICE_TYPE == ARRIA10) begin if (DEVICE_TYPE == ARRIA10) begin
__ad_cmos_out_1__ i_tx_data_oddr ( __ad_cmos_out_1__ i_tx_data_oddr (
.ck (tx_clk), .clk_export (tx_clk),
.din ({tx_data_p, tx_data_n}), .din_export ({tx_data_p, tx_data_n}),
.pad_out (tx_data_out)); .pad_out_export (tx_data_out));
end end
endgenerate endgenerate

6
library/axi_ad9361/axi_ad9361_hw.tcl
View File

@ -226,9 +226,9 @@ proc axi_ad9361_elab {} {
proc axi_ad9361_fileset {entityName} { proc axi_ad9361_fileset {entityName} {
ad_ip_modfile ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core ad_ip_modfile ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core_a10
ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core_a10
ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core_a10
ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
} }

1
projects/fmcomms2/common/fmcomms2_qsys.tcl
View File

@ -5,6 +5,7 @@
add_instance axi_ad9361 axi_ad9361 1.0 add_instance axi_ad9361 axi_ad9361 1.0
set_instance_parameter_value axi_ad9361 {ID} {0} set_instance_parameter_value axi_ad9361 {ID} {0}
set_instance_parameter_value axi_ad9361 {DEVICE_TYPE} {0}
add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
add_connection sys_clk.clk axi_ad9361.s_axi_clock add_connection sys_clk.clk axi_ad9361.s_axi_clock