intel_serde: Rename alt_serdes to intel_serdes
Istvan Csomortani
István Csomortáni
parent
b0fbe1bb57
commit
1e074726db
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@ -65,7 +65,7 @@ clean:
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$(MAKE) -C intel/avl_dacfifo clean
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$(MAKE) -C intel/axi_adxcvr clean
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$(MAKE) -C intel/common/alt_mem_asym clean
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$(MAKE) -C intel/common/alt_serdes clean
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$(MAKE) -C intel/common/intel_serdes clean
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$(MAKE) -C intel/jesd204_phy clean
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$(MAKE) -C intel/util_clkdiv clean
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc clean
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@ -175,7 +175,7 @@ lib:
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$(MAKE) -C intel/avl_dacfifo
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$(MAKE) -C intel/axi_adxcvr
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$(MAKE) -C intel/common/alt_mem_asym
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$(MAKE) -C intel/common/alt_serdes
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$(MAKE) -C intel/common/intel_serdes
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$(MAKE) -C intel/jesd204_phy
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$(MAKE) -C intel/util_clkdiv
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc
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@ -96,13 +96,13 @@ ad_alt_intf signal dac_dunf input 1 unf
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# SERDES instances and configurations
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add_hdl_instance ad_serdes_clk_core_tx alt_serdes
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add_hdl_instance ad_serdes_clk_core_tx intel_serdes
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set_instance_parameter_value ad_serdes_clk_core_tx {MODE} {CLK}
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set_instance_parameter_value ad_serdes_clk_core_tx {DDR_OR_SDR_N} {1}
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set_instance_parameter_value ad_serdes_clk_core_tx {SERDES_FACTOR} {8}
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set_instance_parameter_value ad_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0}
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add_hdl_instance ad_serdes_out_core alt_serdes
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add_hdl_instance ad_serdes_out_core intel_serdes
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set_instance_parameter_value ad_serdes_out_core {MODE} {OUT}
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set_instance_parameter_value ad_serdes_out_core {DDR_OR_SDR_N} {1}
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set_instance_parameter_value ad_serdes_out_core {SERDES_FACTOR} {8}
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@ -175,22 +175,22 @@ proc axi_ad9361_elab {} {
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if {$m_fpga_technology eq "Arria 10"} {
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add_hdl_instance axi_ad9361_serdes_clk alt_serdes
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set_instance_parameter_value axi_ad9361_serdes_clk {FPGA_TECHNOLOGY} $m_fpga_technology
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add_hdl_instance axi_ad9361_serdes_clk intel_serdes
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set_instance_parameter_value axi_ad9361_serdes_clk {DEVICE_FAMILY} $m_fpga_technology
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set_instance_parameter_value axi_ad9361_serdes_clk {MODE} {CLK}
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set_instance_parameter_value axi_ad9361_serdes_clk {DDR_OR_SDR_N} {1}
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set_instance_parameter_value axi_ad9361_serdes_clk {SERDES_FACTOR} {4}
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set_instance_parameter_value axi_ad9361_serdes_clk {CLKIN_FREQUENCY} {250.0}
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add_hdl_instance axi_ad9361_serdes_in alt_serdes
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set_instance_parameter_value axi_ad9361_serdes_in {FPGA_TECHNOLOGY} $m_fpga_technology
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add_hdl_instance axi_ad9361_serdes_in intel_serdes
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set_instance_parameter_value axi_ad9361_serdes_in {DEVICE_FAMILY} $m_fpga_technology
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set_instance_parameter_value axi_ad9361_serdes_in {MODE} {IN}
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set_instance_parameter_value axi_ad9361_serdes_in {DDR_OR_SDR_N} {1}
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set_instance_parameter_value axi_ad9361_serdes_in {SERDES_FACTOR} {4}
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set_instance_parameter_value axi_ad9361_serdes_in {CLKIN_FREQUENCY} {250.0}
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add_hdl_instance axi_ad9361_serdes_out alt_serdes
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set_instance_parameter_value axi_ad9361_serdes_out {FPGA_TECHNOLOGY} $m_fpga_technology
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add_hdl_instance axi_ad9361_serdes_out intel_serdes
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set_instance_parameter_value axi_ad9361_serdes_out {DEVICE_FAMILY} $m_fpga_technology
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set_instance_parameter_value axi_ad9361_serdes_out {MODE} {OUT}
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set_instance_parameter_value axi_ad9361_serdes_out {DDR_OR_SDR_N} {1}
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set_instance_parameter_value axi_ad9361_serdes_out {SERDES_FACTOR} {4}
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@ -96,13 +96,13 @@ ad_alt_intf signal adc_dovf input 1 ovf
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# SERDES instances and configurations
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add_hdl_instance ad_serdes_clk_core_rx alt_serdes
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add_hdl_instance ad_serdes_clk_core_rx intel_serdes
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set_instance_parameter_value ad_serdes_clk_core_rx {MODE} {CLK}
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set_instance_parameter_value ad_serdes_clk_core_rx {DDR_OR_SDR_N} {1}
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set_instance_parameter_value ad_serdes_clk_core_rx {SERDES_FACTOR} {4}
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set_instance_parameter_value ad_serdes_clk_core_rx {CLKIN_FREQUENCY} {500.0}
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add_hdl_instance ad_serdes_in_core alt_serdes
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add_hdl_instance ad_serdes_in_core intel_serdes
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set_instance_parameter_value ad_serdes_in_core {MODE} {IN}
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set_instance_parameter_value ad_serdes_in_core {DDR_OR_SDR_N} {1}
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set_instance_parameter_value ad_serdes_in_core {SERDES_FACTOR} {4}
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@ -1,132 +0,0 @@
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package require qsys
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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ad_ip_create alt_serdes {Altera SERDES}
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set_module_property COMPOSITION_CALLBACK p_alt_serdes
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter MODE STRING "CLK" false
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ad_ip_parameter DDR_OR_SDR_N INTEGER 1 false
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ad_ip_parameter SERDES_FACTOR INTEGER 8 false
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ad_ip_parameter CLKIN_FREQUENCY FLOAT 500.0 false
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set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"}
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set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1}
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set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8}
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set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
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proc p_alt_serdes {} {
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set m_mode [get_parameter_value "MODE"]
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set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"]
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set m_serdes_factor [get_parameter_value "SERDES_FACTOR"]
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set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"]
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set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
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set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
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set m_ls_phase 22.5
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set m_ld_phase 315.0
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set m_ld_duty_cycle 12.5
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if {$m_serdes_factor == 4} {
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set m_ls_phase 45
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set m_ld_phase 270.0
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set m_ld_duty_cycle 25.0
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}
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## arria 10 only
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if {$m_mode == "CLK"} {
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add_instance alt_serdes_pll altera_iopll
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set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
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set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
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set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
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set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3}
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set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
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set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
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set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
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set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
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add_interface rst reset sink
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set_interface_property rst EXPORT_OF alt_serdes_pll.reset
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF alt_serdes_pll.locked
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add_interface hs_phase conduit end
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set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
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add_interface hs_clk conduit end
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set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
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add_interface ls_clk clock source
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set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
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return
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}
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if {$m_mode == "IN"} {
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add_instance alt_serdes_in altera_lvds
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set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO}
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set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
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set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate
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set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor
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set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency
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set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
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add_interface data_in conduit end
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set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in
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add_interface clk conduit end
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set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden
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add_interface div_clk conduit end
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set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock
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add_interface hs_phase conduit end
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set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF alt_serdes_in.ext_pll_locked
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add_interface data_s conduit end
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set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out
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add_interface delay_locked conduit end
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set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked
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return
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}
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if {$m_mode == "OUT"} {
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add_instance alt_serdes_out altera_lvds
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set_instance_parameter_value alt_serdes_out {MODE} {TX}
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set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
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set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate
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set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor
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set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
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set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
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set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency
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set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
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add_interface data_out conduit end
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set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out
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add_interface clk conduit end
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set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden
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add_interface div_clk conduit end
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set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock
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add_interface data_s conduit end
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set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in
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return
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}
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}
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@ -3,8 +3,8 @@
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := alt_serdes
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LIBRARY_NAME := intel_serdes
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INTEL_DEPS += alt_serdes_hw.tcl
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INTEL_DEPS += intel_serdes_hw.tcl
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include ../../../scripts/library.mk
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@ -0,0 +1,132 @@
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package require qsys
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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ad_ip_create intel_serdes {Intel SERDES}
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set_module_property COMPOSITION_CALLBACK p_intel_serdes
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter MODE STRING "CLK" false
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ad_ip_parameter DDR_OR_SDR_N INTEGER 1 false
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ad_ip_parameter SERDES_FACTOR INTEGER 8 false
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ad_ip_parameter CLKIN_FREQUENCY FLOAT 500.0 false
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set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"}
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set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1}
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set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8}
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set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
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proc p_intel_serdes {} {
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set m_mode [get_parameter_value "MODE"]
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set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"]
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set m_serdes_factor [get_parameter_value "SERDES_FACTOR"]
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set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"]
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set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
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set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
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set m_ls_phase 22.5
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set m_ld_phase 315.0
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set m_ld_duty_cycle 12.5
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if {$m_serdes_factor == 4} {
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set m_ls_phase 45
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set m_ld_phase 270.0
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set m_ld_duty_cycle 25.0
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}
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## arria 10 only
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if {$m_mode == "CLK"} {
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add_instance intel_serdes_pll altera_iopll
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set_instance_parameter_value intel_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
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set_instance_parameter_value intel_serdes_pll {gui_use_locked} {1}
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set_instance_parameter_value intel_serdes_pll {gui_operation_mode} {lvds}
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set_instance_parameter_value intel_serdes_pll {gui_number_of_clocks} {3}
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set_instance_parameter_value intel_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
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set_instance_parameter_value intel_serdes_pll {gui_en_phout_ports} {true}
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set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
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set_instance_parameter_value intel_serdes_pll {gui_ps_units0} {degrees}
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set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg0} {180.0}
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set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
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set_instance_parameter_value intel_serdes_pll {gui_ps_units1} {degrees}
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set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
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set_instance_parameter_value intel_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
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set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
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set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
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set_instance_parameter_value intel_serdes_pll {gui_ps_units2} {degrees}
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add_interface rst reset sink
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set_interface_property rst EXPORT_OF intel_serdes_pll.reset
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF intel_serdes_pll.refclk
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF intel_serdes_pll.locked
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add_interface hs_phase conduit end
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set_interface_property hs_phase EXPORT_OF intel_serdes_pll.phout
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add_interface hs_clk conduit end
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set_interface_property hs_clk EXPORT_OF intel_serdes_pll.lvds_clk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF intel_serdes_pll.loaden
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add_interface ls_clk clock source
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set_interface_property ls_clk EXPORT_OF intel_serdes_pll.outclk2
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return
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}
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if {$m_mode == "IN"} {
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add_instance intel_serdes_in altera_lvds
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set_instance_parameter_value intel_serdes_in {MODE} {RX_DPA-FIFO}
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set_instance_parameter_value intel_serdes_in {NUM_CHANNELS} {1}
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set_instance_parameter_value intel_serdes_in {DATA_RATE} $m_hs_data_rate
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set_instance_parameter_value intel_serdes_in {J_FACTOR} $m_serdes_factor
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set_instance_parameter_value intel_serdes_in {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value intel_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency
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set_instance_parameter_value intel_serdes_in {PLL_USE_RESET} {false}
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add_interface data_in conduit end
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set_interface_property data_in EXPORT_OF intel_serdes_in.rx_in
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add_interface clk conduit end
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set_interface_property clk EXPORT_OF intel_serdes_in.ext_fclk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF intel_serdes_in.ext_loaden
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add_interface div_clk conduit end
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set_interface_property div_clk EXPORT_OF intel_serdes_in.ext_coreclock
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add_interface hs_phase conduit end
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set_interface_property hs_phase EXPORT_OF intel_serdes_in.ext_vcoph
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF intel_serdes_in.ext_pll_locked
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add_interface data_s conduit end
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set_interface_property data_s EXPORT_OF intel_serdes_in.rx_out
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add_interface delay_locked conduit end
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set_interface_property delay_locked EXPORT_OF intel_serdes_in.rx_dpa_locked
|
||||
return
|
||||
}
|
||||
|
||||
if {$m_mode == "OUT"} {
|
||||
add_instance intel_serdes_out altera_lvds
|
||||
set_instance_parameter_value intel_serdes_out {MODE} {TX}
|
||||
set_instance_parameter_value intel_serdes_out {NUM_CHANNELS} {1}
|
||||
set_instance_parameter_value intel_serdes_out {DATA_RATE} $m_hs_data_rate
|
||||
set_instance_parameter_value intel_serdes_out {J_FACTOR} $m_serdes_factor
|
||||
set_instance_parameter_value intel_serdes_out {TX_EXPORT_CORECLOCK} {false}
|
||||
set_instance_parameter_value intel_serdes_out {TX_USE_OUTCLOCK} {false}
|
||||
set_instance_parameter_value intel_serdes_out {USE_EXTERNAL_PLL} {true}
|
||||
set_instance_parameter_value intel_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency
|
||||
set_instance_parameter_value intel_serdes_out {PLL_USE_RESET} {false}
|
||||
add_interface data_out conduit end
|
||||
set_interface_property data_out EXPORT_OF intel_serdes_out.tx_out
|
||||
add_interface clk conduit end
|
||||
set_interface_property clk EXPORT_OF intel_serdes_out.ext_fclk
|
||||
add_interface loaden conduit end
|
||||
set_interface_property loaden EXPORT_OF intel_serdes_out.ext_loaden
|
||||
add_interface div_clk conduit end
|
||||
set_interface_property div_clk EXPORT_OF intel_serdes_out.ext_coreclock
|
||||
add_interface data_s conduit end
|
||||
set_interface_property data_s EXPORT_OF intel_serdes_out.tx_in
|
||||
return
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue