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fmcomms2/zc702: Fix Warning[Synth 8-2611] 

In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
main
Istvan Csomortani 2017-04-19 13:54:03 +03:00
parent db0cd63ed3
commit 1d4b92190a
1 changed files with 0 additions and 4 deletions
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4
projects/fmcomms2/zc702/system_top.v
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@ -117,10 +117,6 @@ module system_top (
wire [63:0] gpio_o; wire [63:0] gpio_o;
wire [63:0] gpio_t; wire [63:0] gpio_t;
wire spi_udc_csn_tx;
wire spi_udc_csn_rx;
wire spi_udc_sclk;
wire spi_udc_data;
wire tdd_sync_t; wire tdd_sync_t;
wire tdd_sync_o; wire tdd_sync_o;
wire tdd_sync_i; wire tdd_sync_i;