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fmcomms7: ZC706, Update project to new GT framework

main
Adrian Costina 2016-10-14 17:32:23 +03:00
parent a026d44435
commit 1d1fe26624
5 changed files with 125 additions and 177 deletions
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159
projects/fmcomms7/common/fmcomms7_bd.tcl
View File

@ -1,18 +1,4 @@
# fmcomms7
create_bd_port -dir I rx_ref_clk
create_bd_port -dir O rx_sync
create_bd_port -dir I rx_sysref
create_bd_port -dir I -from 3 -to 0 rx_data_p
create_bd_port -dir I -from 3 -to 0 rx_data_n
create_bd_port -dir I tx_ref_clk
create_bd_port -dir I tx_sync
create_bd_port -dir I tx_sysref
create_bd_port -dir O -from 7 -to 0 tx_data_p
create_bd_port -dir O -from 7 -to 0 tx_data_n
create_bd_port -dir O -from 11 -to 0 spi2_csn_o
create_bd_port -dir I -from 11 -to 0 spi2_csn_i
create_bd_port -dir I spi2_clk_i
@ -23,13 +9,18 @@ create_bd_port -dir I spi2_sdi_i
# dac peripherals
set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core
set axi_ad9144_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9144_xcvr]
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9144_xcvr
set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9144_xcvr
set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9144_xcvr
set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9144_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd
set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core
set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9144_dma
@ -48,12 +39,17 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack
# adc peripherals
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr
set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr
set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
@ -73,26 +69,9 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
# dac/adc common gt
set axi_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcomms7_gt]
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.TX_DATA_SEL_0 {5}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.TX_DATA_SEL_2 {6}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.TX_DATA_SEL_3 {7}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.TX_DATA_SEL_4 {2}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.TX_DATA_SEL_5 {0}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.TX_DATA_SEL_6 {1}] $axi_fmcomms7_gt
set_property -dict [list CONFIG.TX_DATA_SEL_7 {4}] $axi_fmcomms7_gt
set util_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcomms7_gt]
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_fmcomms7_gt
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcomms7_gt
set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcomms7_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_gt
set_property -dict [list CONFIG.TX_ENABLE {1}] $util_fmcomms7_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_gt
set util_fmcomms7_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcomms7_xcvr]
set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_xcvr
set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_xcvr
set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi
@ -110,65 +89,22 @@ ad_connect spi2_sdo_o axi_fmcomms7_spi/io0_o
ad_connect spi2_sdi_i axi_fmcomms7_spi/io1_i
ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk
# connections (gt)
ad_connect util_fmcomms7_gt/qpll_ref_clk rx_ref_clk
ad_connect util_fmcomms7_gt/cpll_ref_clk tx_ref_clk
ad_connect axi_fmcomms7_gt/gt_qpll_0 util_fmcomms7_gt/gt_qpll_0
ad_connect axi_fmcomms7_gt/gt_pll_0 util_fmcomms7_gt/gt_pll_0
ad_connect axi_fmcomms7_gt/gt_pll_1 util_fmcomms7_gt/gt_pll_1
ad_connect axi_fmcomms7_gt/gt_pll_2 util_fmcomms7_gt/gt_pll_2
ad_connect axi_fmcomms7_gt/gt_pll_3 util_fmcomms7_gt/gt_pll_3
ad_connect axi_fmcomms7_gt/gt_pll_4 util_fmcomms7_gt/gt_pll_4
ad_connect axi_fmcomms7_gt/gt_pll_5 util_fmcomms7_gt/gt_pll_5
ad_connect axi_fmcomms7_gt/gt_pll_6 util_fmcomms7_gt/gt_pll_6
ad_connect axi_fmcomms7_gt/gt_pll_7 util_fmcomms7_gt/gt_pll_7
ad_connect axi_fmcomms7_gt/gt_rx_0 util_fmcomms7_gt/gt_rx_0
ad_connect axi_fmcomms7_gt/gt_rx_1 util_fmcomms7_gt/gt_rx_1
ad_connect axi_fmcomms7_gt/gt_rx_2 util_fmcomms7_gt/gt_rx_2
ad_connect axi_fmcomms7_gt/gt_rx_3 util_fmcomms7_gt/gt_rx_3
ad_connect axi_fmcomms7_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
ad_connect axi_fmcomms7_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
ad_connect axi_fmcomms7_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
ad_connect axi_fmcomms7_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
ad_connect axi_fmcomms7_gt/gt_tx_0 util_fmcomms7_gt/gt_tx_0
ad_connect axi_fmcomms7_gt/gt_tx_1 util_fmcomms7_gt/gt_tx_1
ad_connect axi_fmcomms7_gt/gt_tx_2 util_fmcomms7_gt/gt_tx_2
ad_connect axi_fmcomms7_gt/gt_tx_3 util_fmcomms7_gt/gt_tx_3
ad_connect axi_fmcomms7_gt/gt_tx_4 util_fmcomms7_gt/gt_tx_4
ad_connect axi_fmcomms7_gt/gt_tx_5 util_fmcomms7_gt/gt_tx_5
ad_connect axi_fmcomms7_gt/gt_tx_6 util_fmcomms7_gt/gt_tx_6
ad_connect axi_fmcomms7_gt/gt_tx_7 util_fmcomms7_gt/gt_tx_7
ad_connect axi_fmcomms7_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx
ad_connect axi_fmcomms7_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx
ad_connect axi_fmcomms7_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx
ad_connect axi_fmcomms7_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx
ad_connect axi_fmcomms7_gt/gt_tx_ip_4 axi_ad9144_jesd/gt4_tx
ad_connect axi_fmcomms7_gt/gt_tx_ip_5 axi_ad9144_jesd/gt5_tx
ad_connect axi_fmcomms7_gt/gt_tx_ip_6 axi_ad9144_jesd/gt6_tx
ad_connect axi_fmcomms7_gt/gt_tx_ip_7 axi_ad9144_jesd/gt7_tx
# connections (dac)
ad_connect util_fmcomms7_gt/tx_sysref tx_sysref
ad_connect util_fmcomms7_gt/tx_p tx_data_p
ad_connect util_fmcomms7_gt/tx_n tx_data_n
ad_connect util_fmcomms7_gt/tx_sync tx_sync
ad_connect util_fmcomms7_gt/tx_out_clk util_fmcomms7_gt/tx_clk
ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk
ad_connect util_fmcomms7_gt/tx_ip_rst axi_ad9144_jesd/tx_reset
ad_connect util_fmcomms7_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done
ad_connect util_fmcomms7_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref
ad_connect util_fmcomms7_gt/tx_ip_sync axi_ad9144_jesd/tx_sync
ad_connect util_fmcomms7_gt/tx_ip_data axi_ad9144_jesd/tx_tdata
ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_core/tx_clk
ad_connect util_fmcomms7_gt/tx_data axi_ad9144_core/tx_data
ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_upack/dac_clk
ad_xcvrcon util_fmcomms7_xcvr axi_ad9144_xcvr axi_ad9144_jesd
ad_reconct util_fmcomms7_xcvr/tx_0 axi_ad9144_jesd/gt5_tx
ad_reconct util_fmcomms7_xcvr/tx_1 axi_ad9144_jesd/gt3_tx
ad_reconct util_fmcomms7_xcvr/tx_2 axi_ad9144_jesd/gt6_tx
ad_reconct util_fmcomms7_xcvr/tx_3 axi_ad9144_jesd/gt7_tx
ad_reconct util_fmcomms7_xcvr/tx_4 axi_ad9144_jesd/gt2_tx
ad_reconct util_fmcomms7_xcvr/tx_5 axi_ad9144_jesd/gt0_tx
ad_reconct util_fmcomms7_xcvr/tx_6 axi_ad9144_jesd/gt1_tx
ad_reconct util_fmcomms7_xcvr/tx_7 axi_ad9144_jesd/gt4_tx
ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
ad_connect axi_ad9144_jesd/tx_tdata axi_ad9144_core/tx_data
ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk
ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0
ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
@ -181,7 +117,7 @@ ad_connect axi_ad9144_core/dac_valid_2 axi_ad9144_upack/dac_valid_2
ad_connect axi_ad9144_core/dac_enable_3 axi_ad9144_upack/dac_enable_3
ad_connect axi_ad9144_core/dac_ddata_3 axi_ad9144_upack/dac_data_3
ad_connect axi_ad9144_core/dac_valid_3 axi_ad9144_upack/dac_valid_3
ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_fifo/dac_clk
ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk
ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk
@ -196,30 +132,21 @@ ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
# connections (adc)
ad_connect util_fmcomms7_gt/rx_sysref rx_sysref
ad_connect util_fmcomms7_gt/rx_p rx_data_p
ad_connect util_fmcomms7_gt/rx_n rx_data_n
ad_connect util_fmcomms7_gt/rx_sync rx_sync
ad_connect util_fmcomms7_gt/rx_out_clk util_fmcomms7_gt/rx_clk
ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
ad_connect util_fmcomms7_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
ad_connect util_fmcomms7_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
ad_connect util_fmcomms7_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
ad_connect util_fmcomms7_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
ad_connect util_fmcomms7_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
ad_connect util_fmcomms7_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_core/rx_clk
ad_connect util_fmcomms7_gt/rx_data axi_ad9680_core/rx_data
ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_cpack/adc_clk
ad_connect util_fmcomms7_gt/rx_rst axi_ad9680_cpack/adc_rst
ad_xcvrcon util_fmcomms7_xcvr axi_ad9680_xcvr axi_ad9680_jesd
ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_fifo/adc_clk
ad_connect util_fmcomms7_gt/rx_rst axi_ad9680_fifo/adc_rst
ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
@ -233,10 +160,11 @@ ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_fmcomms7_gt
ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
ad_cpu_interconnect 0x44A00000 axi_ad9144_core
ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
ad_cpu_interconnect 0x44A10000 axi_ad9680_core
ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
@ -245,7 +173,7 @@ ad_cpu_interconnect 0x44A80000 axi_fmcomms7_spi
# gt uses hp3, and 100MHz clock for both DRP and AXI4
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_fmcomms7_gt/m_axi
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
# interconnect (mem/dac)
@ -260,3 +188,4 @@ ad_cpu_interrupt ps-9 mb-9 axi_ad9144_dma/irq
ad_cpu_interrupt ps-10 mb-10 axi_ad9680_dma/irq
ad_cpu_interrupt ps-12 mb-12 axi_fmcomms7_spi/ip2intc_irpt
ad_connect axi_ad9144_fifo/dac_fifo_bypass GND

12
projects/fmcomms7/zc706/Makefile
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@ -24,14 +24,14 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_VIVADO := vivado -mode batch -source
@ -64,14 +64,14 @@ clean-all:clean
make -C ../../../library/axi_ad9144 clean
make -C ../../../library/axi_ad9680 clean
make -C ../../../library/xilinx/axi_adcfifo clean
make -C ../../../library/xilinx/axi_adxcvr clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_dacfifo clean
make -C ../../../library/util_jesd_gt clean
make -C ../../../library/util_upack clean
@ -84,14 +84,14 @@ lib:
make -C ../../../library/axi_ad9144
make -C ../../../library/axi_ad9680
make -C ../../../library/xilinx/axi_adcfifo
make -C ../../../library/xilinx/axi_adxcvr
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_jesd_gt
make -C ../../../library/axi_spdif_tx
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_cpack
make -C ../../../library/util_dacfifo
make -C ../../../library/util_jesd_gt
make -C ../../../library/util_upack
####################################################################################

1
projects/fmcomms7/zc706/system_bd.tcl
View File

@ -22,4 +22,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
SEG_axi_ddr_cntrl_memaddr
source ../common/fmcomms7_bd.tcl

4
projects/fmcomms7/zc706/system_constr.xdc
View File

@ -102,6 +102,6 @@ set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports hmc922_b
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcomms7_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcomms7_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]

40
projects/fmcomms7/zc706/system_top.v
View File

@ -477,11 +477,17 @@ module system_top (
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_11 (1'b0),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
@ -511,11 +517,25 @@ module system_top (
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.tx_data_n (tx_data_n),
.tx_data_p (tx_data_p),
.tx_ref_clk (tx_ref_clk),
.tx_sync (tx_sync),
.tx_sysref (tx_sysref));
.tx_data_0_n (tx_data_n[0]),
.tx_data_0_p (tx_data_p[0]),
.tx_data_1_n (tx_data_n[1]),
.tx_data_1_p (tx_data_p[1]),
.tx_data_2_n (tx_data_n[2]),
.tx_data_2_p (tx_data_p[2]),
.tx_data_3_n (tx_data_n[3]),
.tx_data_3_p (tx_data_p[3]),
.tx_data_4_n (tx_data_n[4]),
.tx_data_4_p (tx_data_p[4]),
.tx_data_5_n (tx_data_n[5]),
.tx_data_5_p (tx_data_p[5]),
.tx_data_6_n (tx_data_n[6]),
.tx_data_6_p (tx_data_p[6]),
.tx_data_7_n (tx_data_n[7]),
.tx_data_7_p (tx_data_p[7]),
.tx_ref_clk_0 (tx_ref_clk),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (tx_sysref));
endmodule