fmcomms7: ZC706, Update project to new GT framework
Adrian Costina
parent
a026d44435
commit
1d1fe26624
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@ -1,18 +1,4 @@
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# fmcomms7
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir O rx_sync
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create_bd_port -dir I rx_sysref
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create_bd_port -dir I -from 3 -to 0 rx_data_p
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create_bd_port -dir I -from 3 -to 0 rx_data_n
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create_bd_port -dir I tx_ref_clk
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create_bd_port -dir I tx_sync
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create_bd_port -dir I tx_sysref
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create_bd_port -dir O -from 7 -to 0 tx_data_p
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create_bd_port -dir O -from 7 -to 0 tx_data_n
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create_bd_port -dir O -from 11 -to 0 spi2_csn_o
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create_bd_port -dir I -from 11 -to 0 spi2_csn_i
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create_bd_port -dir I spi2_clk_i
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@ -23,13 +9,18 @@ create_bd_port -dir I spi2_sdi_i
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# dac peripherals
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set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
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set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core
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set axi_ad9144_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9144_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9144_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9144_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9144_xcvr
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set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9144_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd
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set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
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set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core
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set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9144_dma
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@ -48,12 +39,17 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack
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# adc peripherals
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set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
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set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr
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set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
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set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
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set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
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@ -73,26 +69,9 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack
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# dac/adc common gt
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set axi_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcomms7_gt]
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_0 {5}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_2 {6}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_3 {7}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_4 {2}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_5 {0}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_6 {1}] $axi_fmcomms7_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_7 {4}] $axi_fmcomms7_gt
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set util_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcomms7_gt]
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_fmcomms7_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcomms7_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcomms7_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_gt
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set_property -dict [list CONFIG.TX_ENABLE {1}] $util_fmcomms7_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_gt
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set util_fmcomms7_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcomms7_xcvr]
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_xcvr
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_xcvr
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set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi
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@ -110,65 +89,22 @@ ad_connect spi2_sdo_o axi_fmcomms7_spi/io0_o
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ad_connect spi2_sdi_i axi_fmcomms7_spi/io1_i
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ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk
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# connections (gt)
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ad_connect util_fmcomms7_gt/qpll_ref_clk rx_ref_clk
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ad_connect util_fmcomms7_gt/cpll_ref_clk tx_ref_clk
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ad_connect axi_fmcomms7_gt/gt_qpll_0 util_fmcomms7_gt/gt_qpll_0
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ad_connect axi_fmcomms7_gt/gt_pll_0 util_fmcomms7_gt/gt_pll_0
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ad_connect axi_fmcomms7_gt/gt_pll_1 util_fmcomms7_gt/gt_pll_1
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ad_connect axi_fmcomms7_gt/gt_pll_2 util_fmcomms7_gt/gt_pll_2
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ad_connect axi_fmcomms7_gt/gt_pll_3 util_fmcomms7_gt/gt_pll_3
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ad_connect axi_fmcomms7_gt/gt_pll_4 util_fmcomms7_gt/gt_pll_4
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ad_connect axi_fmcomms7_gt/gt_pll_5 util_fmcomms7_gt/gt_pll_5
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ad_connect axi_fmcomms7_gt/gt_pll_6 util_fmcomms7_gt/gt_pll_6
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ad_connect axi_fmcomms7_gt/gt_pll_7 util_fmcomms7_gt/gt_pll_7
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ad_connect axi_fmcomms7_gt/gt_rx_0 util_fmcomms7_gt/gt_rx_0
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ad_connect axi_fmcomms7_gt/gt_rx_1 util_fmcomms7_gt/gt_rx_1
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ad_connect axi_fmcomms7_gt/gt_rx_2 util_fmcomms7_gt/gt_rx_2
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ad_connect axi_fmcomms7_gt/gt_rx_3 util_fmcomms7_gt/gt_rx_3
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ad_connect axi_fmcomms7_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx
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ad_connect axi_fmcomms7_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx
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ad_connect axi_fmcomms7_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx
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ad_connect axi_fmcomms7_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx
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ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_fmcomms7_gt/gt_tx_0 util_fmcomms7_gt/gt_tx_0
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ad_connect axi_fmcomms7_gt/gt_tx_1 util_fmcomms7_gt/gt_tx_1
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ad_connect axi_fmcomms7_gt/gt_tx_2 util_fmcomms7_gt/gt_tx_2
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ad_connect axi_fmcomms7_gt/gt_tx_3 util_fmcomms7_gt/gt_tx_3
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ad_connect axi_fmcomms7_gt/gt_tx_4 util_fmcomms7_gt/gt_tx_4
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ad_connect axi_fmcomms7_gt/gt_tx_5 util_fmcomms7_gt/gt_tx_5
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ad_connect axi_fmcomms7_gt/gt_tx_6 util_fmcomms7_gt/gt_tx_6
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ad_connect axi_fmcomms7_gt/gt_tx_7 util_fmcomms7_gt/gt_tx_7
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ad_connect axi_fmcomms7_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx
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ad_connect axi_fmcomms7_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx
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ad_connect axi_fmcomms7_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx
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ad_connect axi_fmcomms7_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx
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ad_connect axi_fmcomms7_gt/gt_tx_ip_4 axi_ad9144_jesd/gt4_tx
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ad_connect axi_fmcomms7_gt/gt_tx_ip_5 axi_ad9144_jesd/gt5_tx
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ad_connect axi_fmcomms7_gt/gt_tx_ip_6 axi_ad9144_jesd/gt6_tx
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ad_connect axi_fmcomms7_gt/gt_tx_ip_7 axi_ad9144_jesd/gt7_tx
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# connections (dac)
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ad_connect util_fmcomms7_gt/tx_sysref tx_sysref
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ad_connect util_fmcomms7_gt/tx_p tx_data_p
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ad_connect util_fmcomms7_gt/tx_n tx_data_n
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ad_connect util_fmcomms7_gt/tx_sync tx_sync
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ad_connect util_fmcomms7_gt/tx_out_clk util_fmcomms7_gt/tx_clk
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ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk
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ad_connect util_fmcomms7_gt/tx_ip_rst axi_ad9144_jesd/tx_reset
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ad_connect util_fmcomms7_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done
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ad_connect util_fmcomms7_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref
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ad_connect util_fmcomms7_gt/tx_ip_sync axi_ad9144_jesd/tx_sync
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ad_connect util_fmcomms7_gt/tx_ip_data axi_ad9144_jesd/tx_tdata
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ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_core/tx_clk
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ad_connect util_fmcomms7_gt/tx_data axi_ad9144_core/tx_data
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ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_upack/dac_clk
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ad_xcvrcon util_fmcomms7_xcvr axi_ad9144_xcvr axi_ad9144_jesd
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ad_reconct util_fmcomms7_xcvr/tx_0 axi_ad9144_jesd/gt5_tx
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ad_reconct util_fmcomms7_xcvr/tx_1 axi_ad9144_jesd/gt3_tx
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ad_reconct util_fmcomms7_xcvr/tx_2 axi_ad9144_jesd/gt6_tx
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ad_reconct util_fmcomms7_xcvr/tx_3 axi_ad9144_jesd/gt7_tx
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ad_reconct util_fmcomms7_xcvr/tx_4 axi_ad9144_jesd/gt2_tx
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ad_reconct util_fmcomms7_xcvr/tx_5 axi_ad9144_jesd/gt0_tx
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ad_reconct util_fmcomms7_xcvr/tx_6 axi_ad9144_jesd/gt1_tx
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ad_reconct util_fmcomms7_xcvr/tx_7 axi_ad9144_jesd/gt4_tx
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ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk
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ad_connect axi_ad9144_jesd/tx_tdata axi_ad9144_core/tx_data
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ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk
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ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0
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ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0
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ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0
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@ -181,7 +117,7 @@ ad_connect axi_ad9144_core/dac_valid_2 axi_ad9144_upack/dac_valid_2
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ad_connect axi_ad9144_core/dac_enable_3 axi_ad9144_upack/dac_enable_3
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ad_connect axi_ad9144_core/dac_ddata_3 axi_ad9144_upack/dac_data_3
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ad_connect axi_ad9144_core/dac_valid_3 axi_ad9144_upack/dac_valid_3
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ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_fifo/dac_clk
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ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk
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ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
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ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
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ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk
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@ -196,30 +132,21 @@ ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
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# connections (adc)
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ad_connect util_fmcomms7_gt/rx_sysref rx_sysref
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ad_connect util_fmcomms7_gt/rx_p rx_data_p
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ad_connect util_fmcomms7_gt/rx_n rx_data_n
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ad_connect util_fmcomms7_gt/rx_sync rx_sync
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ad_connect util_fmcomms7_gt/rx_out_clk util_fmcomms7_gt/rx_clk
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ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk
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ad_connect util_fmcomms7_gt/rx_ip_rst axi_ad9680_jesd/rx_reset
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ad_connect util_fmcomms7_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done
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ad_connect util_fmcomms7_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref
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ad_connect util_fmcomms7_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
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ad_connect util_fmcomms7_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
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ad_connect util_fmcomms7_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
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ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_core/rx_clk
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ad_connect util_fmcomms7_gt/rx_data axi_ad9680_core/rx_data
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ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_cpack/adc_clk
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ad_connect util_fmcomms7_gt/rx_rst axi_ad9680_cpack/adc_rst
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ad_xcvrcon util_fmcomms7_xcvr axi_ad9680_xcvr axi_ad9680_jesd
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ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk
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ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof
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ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data
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ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
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ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
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ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
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ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
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ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
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ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
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ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
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ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_fifo/adc_clk
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ad_connect util_fmcomms7_gt/rx_rst axi_ad9680_fifo/adc_rst
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ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
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ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
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ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
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ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
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ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
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@ -233,10 +160,11 @@ ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_fmcomms7_gt
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ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
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ad_cpu_interconnect 0x44A00000 axi_ad9144_core
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ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
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ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad9680_core
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ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
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@ -245,7 +173,7 @@ ad_cpu_interconnect 0x44A80000 axi_fmcomms7_spi
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_fmcomms7_gt/m_axi
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ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
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# interconnect (mem/dac)
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@ -260,3 +188,4 @@ ad_cpu_interrupt ps-9 mb-9 axi_ad9144_dma/irq
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ad_cpu_interrupt ps-10 mb-10 axi_ad9680_dma/irq
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ad_cpu_interrupt ps-12 mb-12 axi_fmcomms7_spi/ip2intc_irpt
|
||||
|
||||
ad_connect axi_ad9144_fifo/dac_fifo_bypass GND
|
||||
|
|
|
|||
|
|
@ -24,14 +24,14 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
|||
M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr
|
||||
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
|
||||
M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
|
||||
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
|
||||
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
|
||||
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
|
||||
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
|
||||
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
|
||||
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
|
||||
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
|
||||
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
|
||||
M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
|
||||
M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
|
||||
M_DEPS += ../../../library/util_upack/util_upack.xpr
|
||||
|
||||
M_VIVADO := vivado -mode batch -source
|
||||
|
|
@ -64,14 +64,14 @@ clean-all:clean
|
|||
make -C ../../../library/axi_ad9144 clean
|
||||
make -C ../../../library/axi_ad9680 clean
|
||||
make -C ../../../library/xilinx/axi_adcfifo clean
|
||||
make -C ../../../library/xilinx/axi_adxcvr clean
|
||||
make -C ../../../library/axi_clkgen clean
|
||||
make -C ../../../library/axi_dmac clean
|
||||
make -C ../../../library/axi_hdmi_tx clean
|
||||
make -C ../../../library/axi_jesd_gt clean
|
||||
make -C ../../../library/axi_spdif_tx clean
|
||||
make -C ../../../library/xilinx/util_adxcvr clean
|
||||
make -C ../../../library/util_cpack clean
|
||||
make -C ../../../library/util_dacfifo clean
|
||||
make -C ../../../library/util_jesd_gt clean
|
||||
make -C ../../../library/util_upack clean
|
||||
|
||||
|
||||
|
|
@ -84,14 +84,14 @@ lib:
|
|||
make -C ../../../library/axi_ad9144
|
||||
make -C ../../../library/axi_ad9680
|
||||
make -C ../../../library/xilinx/axi_adcfifo
|
||||
make -C ../../../library/xilinx/axi_adxcvr
|
||||
make -C ../../../library/axi_clkgen
|
||||
make -C ../../../library/axi_dmac
|
||||
make -C ../../../library/axi_hdmi_tx
|
||||
make -C ../../../library/axi_jesd_gt
|
||||
make -C ../../../library/axi_spdif_tx
|
||||
make -C ../../../library/xilinx/util_adxcvr
|
||||
make -C ../../../library/util_cpack
|
||||
make -C ../../../library/util_dacfifo
|
||||
make -C ../../../library/util_jesd_gt
|
||||
make -C ../../../library/util_upack
|
||||
|
||||
####################################################################################
|
||||
|
|
|
|||
|
|
@ -22,4 +22,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
|
|||
SEG_axi_ddr_cntrl_memaddr
|
||||
|
||||
source ../common/fmcomms7_bd.tcl
|
||||
|
||||
|
|
|
|||
|
|
@ -1,22 +1,22 @@
|
|||
# fmcomms7
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
|
||||
set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[5])
|
||||
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[5])
|
||||
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3])
|
||||
|
|
@ -51,24 +51,24 @@ set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_dir]
|
|||
|
||||
# spi (others, sdi and/or sdo)
|
||||
|
||||
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_1] ; ## H22 FMC_HPC_LA19_P
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_2] ; ## H23 FMC_HPC_LA19_N
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_1] ; ## H25 FMC_HPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_2] ; ## H26 FMC_HPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_3] ; ## G19 FMC_HPC_LA16_N
|
||||
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_1] ; ## D20 FMC_HPC_LA17_CC_P
|
||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_2] ; ## D21 FMC_HPC_LA17_CC_N
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_1] ; ## G21 FMC_HPC_LA20_P
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_2] ; ## G22 FMC_HPC_LA20_N
|
||||
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports spi2_clk] ; ## C26 FMC_HPC_LA27_P
|
||||
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports spi2_sdo] ; ## C27 FMC_HPC_LA27_N
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_1] ; ## D17 FMC_HPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_2] ; ## D18 FMC_HPC_LA13_N
|
||||
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_1] ; ## H22 FMC_HPC_LA19_P
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_2] ; ## H23 FMC_HPC_LA19_N
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_1] ; ## H25 FMC_HPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_2] ; ## H26 FMC_HPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_3] ; ## G19 FMC_HPC_LA16_N
|
||||
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_1] ; ## D20 FMC_HPC_LA17_CC_P
|
||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_2] ; ## D21 FMC_HPC_LA17_CC_N
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_1] ; ## G21 FMC_HPC_LA20_P
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_2] ; ## G22 FMC_HPC_LA20_N
|
||||
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports spi2_clk] ; ## C26 FMC_HPC_LA27_P
|
||||
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports spi2_sdo] ; ## C27 FMC_HPC_LA27_N
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_1] ; ## D17 FMC_HPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_2] ; ## D18 FMC_HPC_LA13_N
|
||||
|
||||
# external trigger
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
|
||||
|
||||
# clock gpio
|
||||
|
||||
|
|
@ -77,7 +77,7 @@ set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports clk_gpio
|
|||
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS25} [get_ports clk_gpio[2]] ; ## H28 FMC_HPC_LA24_P
|
||||
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports clk_gpio[3]] ; ## H29 FMC_HPC_LA24_N
|
||||
|
||||
# status
|
||||
# status
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N
|
||||
|
|
@ -85,23 +85,23 @@ set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports dac_irq]
|
|||
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports adf4355_1_ld] ; ## D26 FMC_HPC_LA26_P
|
||||
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports adf4355_2_ld] ; ## D27 FMC_HPC_LA26_N
|
||||
|
||||
# control
|
||||
# control
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports xo_en] ; ## G18 FMC_HPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clk_sync] ; ## G12 FMC_HPC_LA08_P
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports adf4355_2_pd] ; ## C22 FMC_HPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_txen0] ; ## G15 FMC_HPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen1] ; ## G16 FMC_HPC_LA12_N
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports hmc271_1_reset] ; ## G24 FMC_HPC_LA22_P
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports hmc271_2_reset] ; ## G25 FMC_HPC_LA22_N
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports hmc349_sel] ; ## C23 FMC_HPC_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports hmc922_a] ; ## D23 FMC_HPC_LA23_P
|
||||
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports hmc922_b] ; ## D24 FMC_HPC_LA23_N
|
||||
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports xo_en] ; ## G18 FMC_HPC_LA16_P
|
||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clk_sync] ; ## G12 FMC_HPC_LA08_P
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports adf4355_2_pd] ; ## C22 FMC_HPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_txen0] ; ## G15 FMC_HPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen1] ; ## G16 FMC_HPC_LA12_N
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports hmc271_1_reset] ; ## G24 FMC_HPC_LA22_P
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports hmc271_2_reset] ; ## G25 FMC_HPC_LA22_N
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports hmc349_sel] ; ## C23 FMC_HPC_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports hmc922_a] ; ## D23 FMC_HPC_LA23_P
|
||||
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports hmc922_b] ; ## D24 FMC_HPC_LA23_N
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
|
||||
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
|
||||
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcomms7_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcomms7_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
|
||||
|
||||
|
|
|
|||
|
|
@ -477,11 +477,17 @@ module system_top (
|
|||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_11 (1'b0),
|
||||
.rx_data_n (rx_data_n),
|
||||
.rx_data_p (rx_data_p),
|
||||
.rx_ref_clk (rx_ref_clk),
|
||||
.rx_sync (rx_sync),
|
||||
.rx_sysref (rx_sysref),
|
||||
.rx_data_0_n (rx_data_n[0]),
|
||||
.rx_data_0_p (rx_data_p[0]),
|
||||
.rx_data_1_n (rx_data_n[1]),
|
||||
.rx_data_1_p (rx_data_p[1]),
|
||||
.rx_data_2_n (rx_data_n[2]),
|
||||
.rx_data_2_p (rx_data_p[2]),
|
||||
.rx_data_3_n (rx_data_n[3]),
|
||||
.rx_data_3_p (rx_data_p[3]),
|
||||
.rx_ref_clk_0 (rx_ref_clk),
|
||||
.rx_sync_0 (rx_sync),
|
||||
.rx_sysref_0 (rx_sysref),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (spi0_clk),
|
||||
.spi0_clk_o (spi0_clk),
|
||||
|
|
@ -511,11 +517,25 @@ module system_top (
|
|||
.sys_clk_clk_n (sys_clk_n),
|
||||
.sys_clk_clk_p (sys_clk_p),
|
||||
.sys_rst (sys_rst),
|
||||
.tx_data_n (tx_data_n),
|
||||
.tx_data_p (tx_data_p),
|
||||
.tx_ref_clk (tx_ref_clk),
|
||||
.tx_sync (tx_sync),
|
||||
.tx_sysref (tx_sysref));
|
||||
.tx_data_0_n (tx_data_n[0]),
|
||||
.tx_data_0_p (tx_data_p[0]),
|
||||
.tx_data_1_n (tx_data_n[1]),
|
||||
.tx_data_1_p (tx_data_p[1]),
|
||||
.tx_data_2_n (tx_data_n[2]),
|
||||
.tx_data_2_p (tx_data_p[2]),
|
||||
.tx_data_3_n (tx_data_n[3]),
|
||||
.tx_data_3_p (tx_data_p[3]),
|
||||
.tx_data_4_n (tx_data_n[4]),
|
||||
.tx_data_4_p (tx_data_p[4]),
|
||||
.tx_data_5_n (tx_data_n[5]),
|
||||
.tx_data_5_p (tx_data_p[5]),
|
||||
.tx_data_6_n (tx_data_n[6]),
|
||||
.tx_data_6_p (tx_data_p[6]),
|
||||
.tx_data_7_n (tx_data_n[7]),
|
||||
.tx_data_7_p (tx_data_p[7]),
|
||||
.tx_ref_clk_0 (tx_ref_clk),
|
||||
.tx_sync_0 (tx_sync),
|
||||
.tx_sysref_0 (tx_sysref));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue