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Add copyright and license to .xdc files 

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
main
Iulia Moldovan 2023-07-10 11:38:46 +03:00 committed by imoldovan
parent 27bb69b44c
commit 1cac2d82e1
179 changed files with 796 additions and 85 deletions
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4
library/axi_ad9122/axi_ad9122_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] \ set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}]

4
library/axi_ad9361/axi_ad9361_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier *enable_up_*] \ [get_cells -hier *enable_up_*] \

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library/axi_ad9434/axi_ad9434_constr.xdc
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@ -1,2 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to \ set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to \
[get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}] [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]

5
library/axi_ad9684/axi_ad9684_constr.xdc
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@ -1 +1,6 @@
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]

5
library/axi_ad9963/axi_ad9963_constr.xdc
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@ -1 +1,6 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_false_path -from [get_cells -hier -filter {name =~ *up_*clk_enb* && IS_SEQUENTIAL}] -to [get_pins -hier -filter {name =~ *bufgctrl*/S0}] set_false_path -from [get_cells -hier -filter {name =~ *up_*clk_enb* && IS_SEQUENTIAL}] -to [get_pins -hier -filter {name =~ *bufgctrl*/S0}]

5
library/axi_adc_trigger/axi_adc_trigger_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_a_d*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_a_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_b_d*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_b_d*}]

5
library/axi_adrv9001/axi_adrv9001_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_false_path -quiet -from [get_cells -quiet -hier *in_toggle_d1_reg* -filter {NAME =~ *i_serdes* && IS_SEQUENTIAL}] set_false_path -quiet -from [get_cells -quiet -hier *in_toggle_d1_reg* -filter {NAME =~ *i_serdes* && IS_SEQUENTIAL}]
set_false_path -quiet -from [get_cells -quiet -hier *out_toggle_d1_reg* -filter {NAME =~ *i_serdes* && IS_SEQUENTIAL}] set_false_path -quiet -from [get_cells -quiet -hier *out_toggle_d1_reg* -filter {NAME =~ *i_serdes* && IS_SEQUENTIAL}]

6
library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_i_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_i_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_adc_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_adc_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_la_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_la_m*}]
@ -5,4 +10,3 @@ set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_la_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_i_m1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *trigger_i_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_adc_m1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *trigger_adc_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_la_m1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *trigger_la_m1_reg* && IS_SEQUENTIAL}]

4
library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_cal_done_t_m1* && IS_SEQUENTIAL}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_cal_done_t_m1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sysref_ack_t_m1* && IS_SEQUENTIAL}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sysref_ack_t_m1* && IS_SEQUENTIAL}]

4
library/axi_hdmi_tx/axi_hdmi_tx_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_fs_toggle*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_fs_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_raddr_g*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_raddr_g*}]

5
library/axi_i2s_adi/axi_i2s_adi_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set ctrl_clk [get_clocks -of_objects [get_ports s_axi_aclk]] set ctrl_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set data_clk [get_clocks -of_objects [get_ports data_clk_i]] set data_clk [get_clocks -of_objects [get_ports data_clk_i]]

4
library/axi_laser_driver/axi_laser_driver_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier {*cdc_sync_stage1_reg*}] \ [get_cells -hier {*cdc_sync_stage1_reg*}] \

5
library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *data_fixed_delay*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *data_fixed_delay*}]

5
library/axi_spdif_tx/axi_spdif_tx_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier cdc_sync_stage1_*_reg] \ [get_cells -hier cdc_sync_stage1_*_reg] \
[get_cells -hier cdc_sync_stage2_*_reg] [get_cells -hier cdc_sync_stage2_*_reg]

4
library/util_adcfifo/util_adcfifo_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier -filter {name =~ *adc_xfer_req_m*}] \ [get_cells -hier -filter {name =~ *adc_xfer_req_m*}] \

4
library/util_dacfifo/util_dacfifo_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *dac_waddr_m*}] \ set_property ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *dac_waddr_m*}] \
[get_cells -hierarchical -filter {name =~ *dac_lastaddr_m*}] \ [get_cells -hierarchical -filter {name =~ *dac_lastaddr_m*}] \

4
library/util_gmii_to_rgmii/util_gmii_to_rgmii_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier *tx_reset_d1_reg*] \ [get_cells -hier *tx_reset_d1_reg*] \

5
library/util_hbm/util_hbm_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage1_reg*] \ [get_cells -quiet -hier *cdc_sync_stage1_reg*] \
[get_cells -quiet -hier *cdc_sync_stage2_reg*] [get_cells -quiet -hier *cdc_sync_stage2_reg*]

4
library/util_mfifo/util_mfifo_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property SHREG_EXTRACT NO [get_cells -hier *din_dout_toggle_m*] set_property SHREG_EXTRACT NO [get_cells -hier *din_dout_toggle_m*]
set_property SHREG_EXTRACT NO [get_cells -hier *dout_din_toggle_m*] set_property SHREG_EXTRACT NO [get_cells -hier *dout_din_toggle_m*]

4
library/util_rfifo/util_rfifo_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_enable_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_enable_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_req_t_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_req_t_m*}]

4
library/util_tdd_sync/util_tdd_sync_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier *sync_mode_d*] [get_cells -hier *sync_mode_d*]

4
library/util_wfifo/util_wfifo_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_enable_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_enable_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_req_t_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_req_t_m*}]

4
library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier *axi_waddr_m1_reg*] \ [get_cells -hier *axi_waddr_m1_reg*] \

5
library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier *dma_mem_*_m*] \ [get_cells -hier *dma_mem_*_m*] \
[get_cells -hier *axi_xfer_*_m*] \ [get_cells -hier *axi_xfer_*_m*] \

4
library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]

5
library/xilinx/common/ad_rst_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# the "-quiet" option is added for the axi_spi_engine ip where the ad_rst.v # the "-quiet" option is added for the axi_spi_engine ip where the ad_rst.v
# module is not always inferred and this causes critical warnings # module is not always inferred and this causes critical warnings

4
library/xilinx/common/up_clock_mon_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_count_running_m*}] set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_count_running_m*}]
set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *d_count_run_m*}] set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *d_count_run_m*}]

4
library/xilinx/common/up_xfer_cntrl_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle_m*}]

4
library/xilinx/common/up_xfer_status_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle_m*}]

4
library/xilinx/util_adxcvr/util_adxcvr_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_rx_rst_done*}] set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_tx_rst_done*}] set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_tx_rst_done*}]

5
library/xilinx/util_clkdiv/util_clkdiv_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_clock_groups \ set_clock_groups \
-group [get_clocks -of_objects [get_pins clk_divide_sel_0/O]] \ -group [get_clocks -of_objects [get_pins clk_divide_sel_0/O]] \
-group [get_clocks -of_objects [get_pins clk_divide_sel_1/O]] \ -group [get_clocks -of_objects [get_pins clk_divide_sel_1/O]] \

4
projects/ad40xx_fmc/zed/system_constr_ad40xx.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad40xx_fmc SPI interface # ad40xx_fmc SPI interface

4
projects/ad40xx_fmc/zed/system_constr_adaq400x.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# adaq400x PMOD SPI interface - the PMOD JA1 is used # adaq400x PMOD SPI interface - the PMOD JA1 is used

5
projects/ad4110/zed/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi_csn] set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi_csn]
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports spi_clk] set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports spi_clk]
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi_mosi] set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi_mosi]

6
projects/ad4134_fmc/zed/system_constr.xdc
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@ -1,5 +1,9 @@
# ad4134 SPI configuration interface ###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad4134 SPI configuration interface
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdi] ; ## FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdi] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdo] ; ## FMC_LPC_LA04_N set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdo] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sclk] ; ## FMC_LPC_LA01_CC_P set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sclk] ; ## FMC_LPC_LA01_CC_P

6
projects/ad4630_fmc/zed/system_constr.xdc
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@ -1,5 +1,9 @@
# ad463x_fmc SPI interface ###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad463x_fmc SPI interface
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo] set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sdo]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk] set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad463x_spi_sclk]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs] set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_cs]

6
projects/ad4630_fmc/zed/system_constr_1sdi.xdc
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@ -1,5 +1,9 @@
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi] ; ## H07 FMC_LPC_LA02_P ###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi] ; ## H07 FMC_LPC_LA02_P
# input delays for MISO lines (SDO for the device) # input delays for MISO lines (SDO for the device)
# data is latched on negative edge # data is latched on negative edge

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projects/ad4630_fmc/zed/system_constr_2sdi.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H10 FMC_LPC_LA04_P set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H10 FMC_LPC_LA04_P

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projects/ad4630_fmc/zed/system_constr_4sdi.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}] set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[0]}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}] set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[1]}]
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}] set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports {ad463x_spi_sdi[2]}]

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projects/ad4630_fmc/zed/system_constr_8sdi.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[0]] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[1]] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad463x_spi_sdi[2]] ; ## G09 FMC_LPC_LA03_P

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projects/ad469x_fmc/zed/system_constr.xdc
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@ -1,5 +1,9 @@
# ad4696_fmc SPI interface ###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad4696_fmc SPI interface
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdo] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdo] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sclk] ; ## D09 FMC_LPC_LA01_CC_N set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sclk] ; ## D09 FMC_LPC_LA01_CC_N

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projects/ad5758_sdz/zed/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# DAC SPI interface # DAC SPI interface

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projects/ad5766_sdz/zed/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# SPI interface # SPI interface
@ -9,4 +13,3 @@ set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports spi_cs]
# reset signal # reset signal
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports reset] ; ## FMC_LPC_LA21_P set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports reset] ; ## FMC_LPC_LA21_P

4
projects/ad6676evb/vc707/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad6676 # ad6676

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projects/ad6676evb/zc706/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad6676 # ad6676

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projects/ad7134_fmc/zed/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad713x SPI configuration interface # ad713x SPI configuration interface
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sdi] ; ## FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad713x_spi_sdi] ; ## FMC_LPC_LA03_P

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projects/ad719x_asdz/coraz7s/system_constr.xdc
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@ -1,5 +1,9 @@
# coraz7s ###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# coraz7s
# ad719x spi connections # ad719x spi connections
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {adc_spi_sclk}]; # IO_L7N_T1_34 Sch=ja_n[2] set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {adc_spi_sclk}]; # IO_L7N_T1_34 Sch=ja_n[2]

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projects/ad738x_fmc/zed/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# SPI interface # SPI interface
@ -6,4 +10,3 @@ set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports spi_sdia]
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports spi_sdib] ; ## FMC_LPC_LA01_CC_N set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports spi_sdib] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports spi_cs] ; ## FMC_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports spi_cs] ; ## FMC_LPC_LA00_CC_N

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projects/ad7405_fmc/zed/system_constr_differential.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports adc_clk_p] ; ## FMC_LPC_LA00_CC_P set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports adc_clk_p] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports adc_clk_n] ; ## FMC_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports adc_clk_n] ; ## FMC_LPC_LA00_CC_N

4
projects/ad7405_fmc/zed/system_constr_singlended.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_clk] ; ## FMC_LPC_LA00_CC_P set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_clk] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_data] ; ## FMC_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_data] ; ## FMC_LPC_LA00_CC_N

4
projects/ad7606x_fmc/zed/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad7606x # ad7606x

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projects/ad7616_sdz/zc706/parallel_if_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad7616 # ad7616
@ -33,4 +37,3 @@ set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_bus
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N

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projects/ad7616_sdz/zc706/serial_if_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad7616 # ad7616

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projects/ad7616_sdz/zed/parallel_if_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad7616 # ad7616
@ -34,4 +38,3 @@ set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_busy
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N

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projects/ad7616_sdz/zed/serial_if_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad7616 # ad7616

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projects/ad77681evb/zed/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# SPI interface # SPI interface
@ -19,4 +23,3 @@ set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25}
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad7768_drdy] ; ## FMC_LPC_LA05_P set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports ad7768_drdy] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports ad7768_sync_out] ; ## FMC_LPC_CLK0_M2C_N set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports ad7768_sync_out] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad7768_sync_in] ; ## FMC_LPC_LA06_P set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad7768_sync_in] ; ## FMC_LPC_LA06_P

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@ -1,27 +1,29 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports clk_in] ; ## H04 FMC_LPC_CLK0_M2C_P IO_L12P_T1_MRCC_34
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports clk_in] ; ## H04 FMC_LPC_CLK0_M2C_P IO_L12P_T1_MRCC_34 set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ready_in] ; ## G06 FMC_LPC_LA00_CC_P IO_L13P_T2_MRCC_34
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ready_in] ; ## G06 FMC_LPC_LA00_CC_P IO_L13P_T2_MRCC_34 set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports data_in[0]] ; ## G07 FMC_LPC_LA00_CC_N IO_L13N_T2_MRCC_34
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports data_in[0]] ; ## G07 FMC_LPC_LA00_CC_N IO_L13N_T2_MRCC_34 set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports data_in[1]] ; ## C11 FMC_LPC_LA06_N IO_L10N_T1_34
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports data_in[1]] ; ## C11 FMC_LPC_LA06_N IO_L10N_T1_34 set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports data_in[2]] ; ## H07 FMC_LPC_LA02_P IO_L20P_T3_34
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports data_in[2]] ; ## H07 FMC_LPC_LA02_P IO_L20P_T3_34 set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports data_in[3]] ; ## H08 FMC_LPC_LA02_N IO_L20N_T3_34
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports data_in[3]] ; ## H08 FMC_LPC_LA02_N IO_L20N_T3_34 set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports data_in[4]] ; ## G12 FMC_LPC_LA08_P IO_L8P_T1_34
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports data_in[4]] ; ## G12 FMC_LPC_LA08_P IO_L8P_T1_34 set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports data_in[5]] ; ## G13 FMC_LPC_LA08_N IO_L8N_T1_34
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports data_in[5]] ; ## G13 FMC_LPC_LA08_N IO_L8N_T1_34 set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports data_in[6]] ; ## D14 FMC_LPC_LA09_P IO_L17P_T2_34
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports data_in[6]] ; ## D14 FMC_LPC_LA09_P IO_L17P_T2_34 set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports data_in[7]] ; ## D15 FMC_LPC_LA09_N IO_L17N_T2_34
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports data_in[7]] ; ## D15 FMC_LPC_LA09_N IO_L17N_T2_34 set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D11 FMC_LPC_LA05_P IO_L7P_T1_34
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D11 FMC_LPC_LA05_P IO_L7P_T1_34 set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D08 FMC_LPC_LA01_CC_P IO_L14P_T2_SRCC_34
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D08 FMC_LPC_LA01_CC_P IO_L14P_T2_SRCC_34 set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H11 FMC_LPC_LA04_N IO_L15N_T2_DQS_34
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H11 FMC_LPC_LA04_N IO_L15N_T2_DQS_34 set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G09 FMC_LPC_LA03_P IO_L16P_T2_34
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G09 FMC_LPC_LA03_P IO_L16P_T2_34 set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports gpio_0_mode_0] ; ## C15 FMC_LPC_LA10_N IO_L22N_T3_34
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports gpio_0_mode_0] ; ## C15 FMC_LPC_LA10_N IO_L22N_T3_34 set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports gpio_1_mode_1] ; ## H13 FMC_LPC_LA07_P IO_L21P_T3_DQS_34
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports gpio_1_mode_1] ; ## H13 FMC_LPC_LA07_P IO_L21P_T3_DQS_34 set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gpio_2_mode_2] ; ## H14 FMC_LPC_LA07_N IO_L21N_T3_DQS_34
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gpio_2_mode_2] ; ## H14 FMC_LPC_LA07_N IO_L21N_T3_DQS_34 set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_3_mode_3] ; ## H16 FMC_LPC_LA11_P IO_L5P_T0_34
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_3_mode_3] ; ## H16 FMC_LPC_LA11_P IO_L5P_T0_34 set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_4_filter] ; ## C14 FMC_LPC_LA10_P IO_L22P_T3_34
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_4_filter] ; ## C14 FMC_LPC_LA10_P IO_L22P_T3_34 set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports reset_n] ; ## C10 FMC_LPC_LA06_P IO_L10P_T1_34
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports reset_n] ; ## C10 FMC_LPC_LA06_P IO_L10P_T1_34 set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports start_n] ; ## G10 FMC_LPC_LA03_N IO_L16N_T2_34
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports start_n] ; ## G10 FMC_LPC_LA03_N IO_L16N_T2_34 set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports mclk] ; ## D09 FMC_LPC_LA01_CC_N IO_L14N_T2_SRCC_34
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports mclk] ; ## D09 FMC_LPC_LA01_CC_N IO_L14N_T2_SRCC_34
create_clock -name adc_clk -period 20 [get_ports clk_in] create_clock -name adc_clk -period 20 [get_ports clk_in]

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projects/ad777x_ardz/zed/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports adc_clk_in] ; #DCLK P24_P9 JA1_9 set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports adc_clk_in] ; #DCLK P24_P9 JA1_9
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS33} [get_ports adc_ready_in] ; #DRDY_N P24_P8 JA1_8 set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS33} [get_ports adc_ready_in] ; #DRDY_N P24_P8 JA1_8
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports adc_data_in[0]] ; #DOUT0 P24_P10 JA1_10 set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports adc_data_in[0]] ; #DOUT0 P24_P10 JA1_10

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projects/ad9081_fmca_ebz/vck190/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# #
## mxfe ## mxfe
# #

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projects/ad9081_fmca_ebz/vck190/timing_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# Primary clock definitions # Primary clock definitions
create_clock -name refclk -period 2.667 [get_ports fpga_refclk_in_p] create_clock -name refclk -period 2.667 [get_ports fpga_refclk_in_p]

5
projects/ad9081_fmca_ebz/vcu118/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# #
## mxfe ## mxfe
# #

4
projects/ad9081_fmca_ebz/vcu118/timing_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# Primary clock definitions # Primary clock definitions

5
projects/ad9081_fmca_ebz/vcu128/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# #
## mxfe ## mxfe
# #

4
projects/ad9081_fmca_ebz/vcu128/timing_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# Primary clock definitions # Primary clock definitions

5
projects/ad9081_fmca_ebz/zc706/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# #
## mxfe ## mxfe
# #

5
projects/ad9081_fmca_ebz/zc706/timing_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# Primary clock definitions # Primary clock definitions
create_clock -name refclk -period 4 [get_ports fpga_refclk_in_p] create_clock -name refclk -period 4 [get_ports fpga_refclk_in_p]

5
projects/ad9081_fmca_ebz/zcu102/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# #
## mxfe ## mxfe
# #

5
projects/ad9081_fmca_ebz/zcu102/timing_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# Primary clock definitions # Primary clock definitions
create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p] create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p]

4
projects/ad9081_fmca_ebz_x_band/zcu102/xband_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports pmod0_0_1_PA_ON ]; ## J55.1 set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports pmod0_0_1_PA_ON ]; ## J55.1
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports pmod0_1_3_MOSI ]; ## J55.3 set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports pmod0_1_3_MOSI ]; ## J55.3

4
projects/ad9083_evb/zcu102/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad9083 # ad9083

4
projects/ad9083_vna/zcu102/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad9083 # ad9083

9
projects/ad9208_dual_ebz/vcu118/system_constr.xdc
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@ -1,8 +1,10 @@
# ###############################################################################
## dual_ad9208 ## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
# ### SPDX short identifier: ADIBSD
###############################################################################
# #
## dual_ad9208
## FMCp_PORT FPGA_IO ## FMCp_PORT FPGA_IO
# #
set_property -dict {PACKAGE_PIN AK38} [get_ports rx_ref_clk_0_p] ; ## GBTCLK0_M2C_P MGTREFCLK0P_121 set_property -dict {PACKAGE_PIN AK38} [get_ports rx_ref_clk_0_p] ; ## GBTCLK0_M2C_P MGTREFCLK0P_121
@ -88,4 +90,3 @@ create_clock -name global_clk_0 -period 2.66 [get_ports glbl_clk_0_p]
set_input_delay -clock [get_clocks global_clk_0] \ set_input_delay -clock [get_clocks global_clk_0] \
[expr [get_property PERIOD [get_clocks global_clk_0]] / 2] \ [expr [get_property PERIOD [get_clocks global_clk_0]] / 2] \
[get_ports {rx_sysref_*}] [get_ports {rx_sysref_*}]

5
projects/ad9209_fmca_ebz/vck190/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# #
## mxfe ## mxfe
# #

5
projects/ad9209_fmca_ebz/vck190/timing_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# Primary clock definitions # Primary clock definitions
create_clock -name refclk -period 2.667 [get_ports fpga_refclk_in_p] create_clock -name refclk -period 2.667 [get_ports fpga_refclk_in_p]

4
projects/ad9265_fmc/zc706/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad9265 # ad9265

6
projects/ad9434_fmc/zc706/system_constr.xdc
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@ -1,5 +1,9 @@
# ad9434 ###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad9434
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_p] ; ## G6 FMC_LPC_LA00_CC_P set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_p] ; ## G6 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_n] ; ## G7 FMC_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_n] ; ## G7 FMC_LPC_LA00_CC_N

4
projects/ad9467_fmc/kc705/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad9467 # ad9467

4
projects/ad9467_fmc/zed/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad9467 # ad9467

4
projects/ad9656_fmc/zcu102/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad9656 # ad9656

4
projects/ad9695_fmc/zcu102/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad9695 # ad9695

4
projects/ad9739a_fmc/zc706/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad9739a # ad9739a

4
projects/ad9783_ebz/zcu102/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# constraints # constraints
# ad9783 # ad9783

4
projects/ad_fmclidar1_ebz/zc706/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ADC digital interface (JESD204B) # ADC digital interface (JESD204B)

4
projects/ad_fmclidar1_ebz/zcu102/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ADC digital interface (JESD204B) # ADC digital interface (JESD204B)

5
projects/ad_quadmxfe1_ebz/vcu118/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# #
## quad mxfe ## quad mxfe
# #

6
projects/ad_quadmxfe1_ebz/vcu118/timing_constr.xdc
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@ -1,5 +1,9 @@
# Primary clock definitions ###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# Primary clock definitions
# These two reference clocks are connect to the same source on the PCB # These two reference clocks are connect to the same source on the PCB
create_clock -name refclk -period 4.00 [get_ports fpga_clk_m2c_p[0]] create_clock -name refclk -period 4.00 [get_ports fpga_clk_m2c_p[0]]
create_clock -name refclk_replica -period 4.00 [get_ports fpga_clk_m2c_0_replica_n] create_clock -name refclk_replica -period 4.00 [get_ports fpga_clk_m2c_0_replica_n]

5
projects/adaq7980_sdz/zed/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# SPI interface # SPI interface
@ -20,4 +24,3 @@ set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports adaq7980_gp
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports adaq7980_ref_pd] ; ## FMC_LPC_LA28_P set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports adaq7980_ref_pd] ; ## FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports adaq7980_rbuf_pd] ; ## FMC_LPC_LA29_P set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports adaq7980_rbuf_pd] ; ## FMC_LPC_LA29_P

6
projects/adaq8092_fmc/zed/system_constr.xdc
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@ -1,5 +1,9 @@
# adaq8092 ###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# adaq8092
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; #G06 FMC_LPC_LA00_P set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; #G06 FMC_LPC_LA00_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; #G07 FMC_LPC_LA00_N set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; #G07 FMC_LPC_LA00_N
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_p[0]] ; #H07 FMC_LPC_LA02_P D1_0 set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in1_p[0]] ; #H07 FMC_LPC_LA02_P D1_0

5
projects/adrv9001/zc706/cmos_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS18} [get_ports rx1_dclk_in_n] ;## G07 FMC_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS18} [get_ports rx1_dclk_in_n] ;## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS18} [get_ports rx1_dclk_in_p] ;## G06 FMC_LPC_LA00_CC_P set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS18} [get_ports rx1_dclk_in_p] ;## G06 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS18} [get_ports rx1_idata_in_n] ;## G10 FMC_LPC_LA03_N set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS18} [get_ports rx1_idata_in_n] ;## G10 FMC_LPC_LA03_N

5
projects/adrv9001/zc706/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# #
# !!! WARNING !!! # !!! WARNING !!!
# #

5
projects/adrv9001/zcu102/cmos_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66 set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66 set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_in_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_in_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66

5
projects/adrv9001/zcu102/lvds_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_in_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66 set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_in_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_in_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66 set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_in_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_in_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_in_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66

5
projects/adrv9001/zcu102/system_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS18} [get_ports dev_clk_in] ; #FMC_HPC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66 set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS18} [get_ports dev_clk_in] ; #FMC_HPC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_out_n] ; #FMC_HPC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66 set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_out_n] ; #FMC_HPC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_out_p] ; #FMC_HPC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66 set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_out_p] ; #FMC_HPC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66

5
projects/adrv9001/zed/cmos_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_n] ;## G07 FMC_HPC0_LA00_CC_N IO_L13N_T2_MRCC_34 set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_n] ;## G07 FMC_HPC0_LA00_CC_N IO_L13N_T2_MRCC_34
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_p] ;## G06 FMC_HPC0_LA00_CC_P IO_L13P_T2_MRCC_34 set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_p] ;## G06 FMC_HPC0_LA00_CC_P IO_L13P_T2_MRCC_34
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_in_n] ;## G10 FMC_HPC0_LA03_N IO_L16N_T2_34 set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_in_n] ;## G10 FMC_HPC0_LA03_N IO_L16N_T2_34

4
projects/adrv9001/zed/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# constraints # constraints
# adrv9001 # adrv9001

4
projects/adrv9009/zc706/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# adrv9009 # adrv9009

4
projects/adrv9009/zcu102/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# adrv9009 # adrv9009

5
projects/adrv9009zu11eg/adrv2crr_fmcomms8/fmcomms8_constr.xdc
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@ -1,3 +1,8 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property PACKAGE_PIN V10 [get_ports ref_clk_c_p]; set_property PACKAGE_PIN V10 [get_ports ref_clk_c_p];
set_property PACKAGE_PIN V9 [get_ports ref_clk_c_n]; set_property PACKAGE_PIN V9 [get_ports ref_clk_c_n];

4
projects/adrv9009zu11eg/adrv2crr_fmcxmwbr1/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# gpios # gpios

4
projects/adrv9009zu11eg/adrv2crr_xmicrowave/system_constr.xdc
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@ -1,3 +1,7 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# gpios # gpios

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