From 1c23cf46216af443e7fd71270be324cf404152f3 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 13 Apr 2017 11:45:54 +0300 Subject: [PATCH] all: Update verilog files to verilog-2001 --- library/altera/common/ad_cmos_clk.v | 17 +- library/altera/common/ad_cmos_in.v | 58 +--- library/altera/common/ad_lvds_clk.v | 19 +- library/altera/common/ad_lvds_in.v | 61 +--- library/altera/common/ad_lvds_out.v | 60 ++-- library/altera/common/ad_mul.v | 32 +- library/axi_ad6676/axi_ad6676.v | 128 +++---- library/axi_ad6676/axi_ad6676_channel.v | 75 ++-- library/axi_ad6676/axi_ad6676_if.v | 45 +-- library/axi_ad6676/axi_ad6676_pnmon.v | 24 +- library/axi_ad7616/axi_ad7616.v | 132 +++---- library/axi_ad7616/axi_ad7616_control.v | 76 ++--- library/axi_ad7616/axi_ad7616_maxis2wrfifo.v | 48 +-- library/axi_ad7616/axi_ad7616_pif.v | 69 ++-- library/axi_ad9122/axi_ad9122.v | 160 +++------ library/axi_ad9122/axi_ad9122_channel.v | 78 ++--- library/axi_ad9122/axi_ad9122_core.v | 172 +++------- library/axi_ad9122/axi_ad9122_if.v | 154 +++------ library/axi_ad9144/axi_ad9144.v | 143 +++----- library/axi_ad9144/axi_ad9144_channel.v | 73 ++-- library/axi_ad9144/axi_ad9144_core.v | 148 +++----- library/axi_ad9144/axi_ad9144_if.v | 76 ++--- library/axi_ad9152/axi_ad9152.v | 123 +++---- library/axi_ad9152/axi_ad9152_channel.v | 71 ++-- library/axi_ad9152/axi_ad9152_core.v | 106 ++---- library/axi_ad9162/axi_ad9162.v | 107 ++---- library/axi_ad9162/axi_ad9162_channel.v | 64 ++-- library/axi_ad9162/axi_ad9162_core.v | 80 ++--- library/axi_ad9162/axi_ad9162_if.v | 25 +- library/axi_ad9234/axi_ad9234.v | 116 ++----- library/axi_ad9234/axi_ad9234_channel.v | 75 ++-- library/axi_ad9234/axi_ad9234_if.v | 36 +- library/axi_ad9234/axi_ad9234_pnmon.v | 24 +- library/axi_ad9250/axi_ad9250.v | 125 +++---- library/axi_ad9250/axi_ad9250_channel.v | 75 ++-- library/axi_ad9250/axi_ad9250_if.v | 46 +-- library/axi_ad9250/axi_ad9250_pnmon.v | 24 +- library/axi_ad9265/axi_ad9265.v | 131 +++---- library/axi_ad9265/axi_ad9265_channel.v | 78 ++--- library/axi_ad9265/axi_ad9265_if.v | 73 ++-- library/axi_ad9265/axi_ad9265_pnmon.v | 21 +- .../axi_ad9361/altera/axi_ad9361_cmos_if.v | 146 +++----- library/axi_ad9361/axi_ad9361_rx_pnmon.v | 36 +- library/axi_ad9361/axi_ad9361_tdd.v | 82 ++--- library/axi_ad9361/axi_ad9361_tdd_if.v | 48 +-- .../axi_ad9361/xilinx/axi_ad9361_cmos_if.v | 146 +++----- .../axi_ad9361/xilinx/axi_ad9361_lvds_if.v | 188 +++------- library/axi_ad9371/axi_ad9371.v | 249 +++++--------- library/axi_ad9371/axi_ad9371_if.v | 49 +-- library/axi_ad9371/axi_ad9371_rx.v | 102 ++---- library/axi_ad9371/axi_ad9371_rx_channel.v | 90 ++--- library/axi_ad9371/axi_ad9371_rx_os.v | 87 ++--- library/axi_ad9371/axi_ad9371_tx.v | 109 ++---- library/axi_ad9371/axi_ad9371_tx_channel.v | 79 ++--- library/axi_ad9434/axi_ad9434.v | 120 +++---- library/axi_ad9434/axi_ad9434_core.v | 116 ++----- library/axi_ad9434/axi_ad9434_if.v | 105 ++---- library/axi_ad9434/axi_ad9434_pnmon.v | 19 +- library/axi_ad9467/axi_ad9467.v | 126 +++---- library/axi_ad9467/axi_ad9467_channel.v | 73 ++-- library/axi_ad9467/axi_ad9467_if.v | 74 ++-- library/axi_ad9467/axi_ad9467_pnmon.v | 21 +- library/axi_ad9625/axi_ad9625.v | 128 +++---- library/axi_ad9625/axi_ad9625_channel.v | 66 ++-- library/axi_ad9625/axi_ad9625_if.v | 53 +-- library/axi_ad9625/axi_ad9625_pnmon.v | 24 +- library/axi_ad9643/axi_ad9643.v | 146 +++----- library/axi_ad9643/axi_ad9643_channel.v | 83 ++--- library/axi_ad9643/axi_ad9643_if.v | 89 ++--- library/axi_ad9643/axi_ad9643_pnmon.v | 21 +- library/axi_ad9652/axi_ad9652.v | 146 +++----- library/axi_ad9652/axi_ad9652_channel.v | 83 ++--- library/axi_ad9652/axi_ad9652_if.v | 87 ++--- library/axi_ad9652/axi_ad9652_pnmon.v | 21 +- library/axi_ad9671/axi_ad9671.v | 127 +++---- library/axi_ad9671/axi_ad9671_channel.v | 79 ++--- library/axi_ad9671/axi_ad9671_if.v | 119 ++----- library/axi_ad9671/axi_ad9671_pnmon.v | 24 +- library/axi_ad9680/axi_ad9680.v | 124 +++---- library/axi_ad9680/axi_ad9680_channel.v | 73 ++-- library/axi_ad9680/axi_ad9680_if.v | 46 +-- library/axi_ad9680/axi_ad9680_pnmon.v | 24 +- library/axi_ad9684/axi_ad9684.v | 135 +++----- library/axi_ad9684/axi_ad9684_channel.v | 80 ++--- library/axi_ad9684/axi_ad9684_if.v | 108 ++---- library/axi_ad9684/axi_ad9684_pnmon.v | 24 +- library/axi_ad9739a/axi_ad9739a.v | 132 +++---- library/axi_ad9739a/axi_ad9739a_channel.v | 131 ++----- library/axi_ad9739a/axi_ad9739a_core.v | 124 +++---- library/axi_ad9739a/axi_ad9739a_if.v | 102 ++---- library/axi_clkgen/axi_clkgen.v | 112 +++--- library/axi_gpreg/axi_gpreg_clock_mon.v | 51 +-- library/axi_gpreg/axi_gpreg_io.v | 58 +--- library/axi_hdmi_rx/axi_hdmi_rx.v | 104 ++---- library/axi_hdmi_rx/axi_hdmi_rx_core.v | 72 ++-- library/axi_hdmi_rx/axi_hdmi_rx_es.v | 31 +- library/axi_hdmi_rx/axi_hdmi_rx_tpm.v | 17 +- library/axi_hdmi_tx/axi_hdmi_tx.v | 159 +++------ library/axi_hdmi_tx/axi_hdmi_tx_core.v | 171 +++------- library/axi_hdmi_tx/axi_hdmi_tx_es.v | 26 +- library/axi_hdmi_tx/axi_hdmi_tx_vdma.v | 69 +--- library/axi_usb_fx3/axi_usb_fx3.v | 164 +++------ library/axi_usb_fx3/axi_usb_fx3_core.v | 243 ++++--------- library/axi_usb_fx3/axi_usb_fx3_if.v | 103 ++---- library/axi_usb_fx3/axi_usb_fx3_reg.v | 194 +++-------- library/common/ad_addsub.v | 29 +- library/common/ad_axis_inf_rx.v | 43 +-- library/common/ad_csc_1.v | 43 +-- library/common/ad_csc_1_add.v | 39 +-- library/common/ad_csc_1_mul.v | 32 +- library/common/ad_csc_CrYCb2RGB.v | 28 +- library/common/ad_csc_RGB2CrYCb.v | 28 +- library/common/ad_dds_1.v | 17 +- library/common/ad_dds_sine.v | 27 +- library/common/ad_edge_detect.v | 22 +- library/common/ad_gt_channel.v | 182 ++++------ library/common/ad_gt_channel_1.v | 292 +++++----------- library/common/ad_gt_common.v | 59 ++-- library/common/ad_gt_common_1.v | 87 ++--- library/common/ad_gt_es.v | 137 +++----- library/common/ad_gt_es_axi.v | 211 ++++-------- library/common/ad_jesd_align.v | 23 +- library/common/ad_mem.v | 31 +- library/common/ad_mem_asym.v | 40 +-- library/common/ad_pnmon.v | 33 +- library/common/ad_rst.v | 13 +- library/common/ad_ss_422to444.v | 36 +- library/common/ad_ss_444to422.v | 35 +- library/common/ad_tdd_control.v | 147 +++----- library/common/ad_xcvr_rx_if.v | 30 +- library/common/up_axi.v | 108 ++---- library/common/up_clkgen.v | 84 ++--- library/common/up_clock_mon.v | 22 +- library/common/up_gt.v | 90 ++--- library/common/up_gt_channel.v | 315 +++++------------ library/common/up_hdmi_rx.v | 100 ++---- library/common/up_hdmi_tx.v | 127 +++---- library/common/up_pmod.v | 53 +-- library/common/up_tdd_cntrl.v | 158 +++------ library/common/up_xfer_cntrl.v | 36 +- library/common/up_xfer_status.v | 32 +- library/common/util_pulse_gen.v | 17 +- library/prcfg/bist/prcfg_adc.v | 43 +-- library/prcfg/bist/prcfg_dac.v | 42 +-- library/prcfg/common/prcfg_top.v | 176 ++++------ library/prcfg/default/prcfg_adc.v | 41 +-- library/prcfg/default/prcfg_dac.v | 41 +-- library/prcfg/qpsk/prcfg_adc.v | 44 +-- library/prcfg/qpsk/prcfg_dac.v | 43 +-- library/prcfg/qpsk/qpsk_demod.v | 17 +- library/prcfg/qpsk/qpsk_mod.v | 17 +- library/util_adcfifo/util_adcfifo.v | 53 +-- library/util_bsplit/util_bsplit.v | 37 +- library/util_ccat/util_ccat.v | 37 +- library/util_cpack/util_cpack.v | 105 ++---- library/util_cpack/util_cpack_dsf.v | 43 +-- library/util_cpack/util_cpack_mux.v | 86 ++--- library/util_dacfifo/util_dacfifo.v | 65 +--- library/util_extract/util_extract.v | 26 +- library/util_gmii_to_rgmii/mdc_mdio.v | 21 +- .../util_gmii_to_rgmii/util_gmii_to_rgmii.v | 92 ++--- library/util_mfifo/util_mfifo.v | 84 ++--- library/util_pmod_adc/util_pmod_adc.v | 64 +--- library/util_pmod_fmeter/util_pmod_fmeter.v | 83 ++--- .../util_pmod_fmeter/util_pmod_fmeter_core.v | 14 +- library/util_rfifo/util_rfifo.v | 182 ++++------ library/util_tdd_sync/util_tdd_sync.v | 23 +- library/util_upack/util_upack.v | 134 +++----- library/util_upack/util_upack_dmx.v | 51 +-- library/util_upack/util_upack_dsf.v | 44 +-- library/util_var_fifo/util_var_fifo.v | 31 +- library/util_wfifo/util_wfifo.v | 182 ++++------ library/xilinx/axi_adcfifo/axi_adcfifo.v | 195 ++++------- library/xilinx/axi_adcfifo/axi_adcfifo_adc.v | 48 +-- library/xilinx/axi_adcfifo/axi_adcfifo_dma.v | 51 +-- library/xilinx/axi_adcfifo/axi_adcfifo_rd.v | 124 ++----- library/xilinx/axi_adcfifo/axi_adcfifo_wr.v | 142 +++----- library/xilinx/axi_dacfifo/axi_dacfifo.v | 207 ++++------- library/xilinx/axi_dacfifo/axi_dacfifo_dac.v | 60 +--- library/xilinx/axi_dacfifo/axi_dacfifo_rd.v | 119 ++----- library/xilinx/axi_dacfifo/axi_dacfifo_wr.v | 151 +++----- library/xilinx/common/ad_cmos_clk.v | 19 +- library/xilinx/common/ad_cmos_in.v | 57 +--- library/xilinx/common/ad_cmos_out.v | 57 +--- library/xilinx/common/ad_iobuf.v | 16 +- library/xilinx/common/ad_lvds_clk.v | 24 +- library/xilinx/common/ad_lvds_out.v | 60 ++-- library/xilinx/common/ad_mmcm_drp.v | 84 ++--- library/xilinx/common/ad_mul.v | 32 +- projects/ad6676evb/vc707/system_top.v | 201 ++++------- projects/ad6676evb/zc706/system_top.v | 165 +++------ projects/ad7616_sdz/zc706/system_top_pi.v | 128 +++---- projects/ad7616_sdz/zc706/system_top_si.v | 140 +++----- projects/ad7616_sdz/zed/system_top_pi.v | 155 +++------ projects/ad7616_sdz/zed/system_top_si.v | 167 +++------ projects/ad7768evb/common/ad7768_if.v | 47 +-- projects/ad7768evb/zed/system_top.v | 176 +++------- projects/ad9265_fmc/common/ad9265_spi.v | 21 +- projects/ad9265_fmc/zc706/system_top.v | 129 +++---- projects/ad9434_fmc/common/ad9434_spi.v | 21 +- projects/ad9434_fmc/zc706/system_top.v | 128 +++---- projects/ad9467_fmc/common/ad9467_spi.v | 21 +- projects/ad9467_fmc/kc705/system_top.v | 178 +++------- projects/ad9467_fmc/zed/system_top.v | 156 +++------ projects/ad9739a_fmc/zc706/system_top.v | 137 +++----- projects/adrv9371x/zc706/system_top.v | 304 ++++++----------- projects/adv7511/ac701/system_top.v | 132 +++---- projects/adv7511/kc705/system_top.v | 166 +++------ projects/adv7511/kcu105/system_top.v | 123 +++---- projects/adv7511/mitx045/system_top.v | 112 ++---- projects/adv7511/vc707/system_top.v | 152 +++------ projects/adv7511/zc702/system_top.v | 96 ++---- projects/adv7511/zc706/system_top.v | 96 ++---- projects/adv7511/zed/system_top.v | 123 +++---- projects/cftl_cip/zed/system_top.v | 140 +++----- projects/cftl_std/zed/system_top.v | 162 +++------ projects/cn0363/microzed/system_top.v | 91 ++--- projects/cn0363/zed/system_top.v | 145 +++----- projects/common/a5gte/system_top.v | 66 ++-- projects/daq1/common/daq1_spi.v | 21 +- projects/daq1/cpld/daq1_cpld.v | 71 ++-- projects/daq1/zc706/system_top.v | 204 ++++------- projects/daq2/a10gx/system_top.v | 174 +++------- projects/daq2/common/daq2_spi.v | 24 +- projects/daq2/kc705/system_top.v | 248 +++++--------- projects/daq2/kcu105/system_top.v | 205 ++++------- projects/daq2/vc707/system_top.v | 234 ++++--------- projects/daq2/zc706/system_top.v | 254 +++++--------- projects/daq3/a10gx/system_top.v | 171 +++------- projects/daq3/common/daq3_spi.v | 24 +- projects/daq3/kcu105/system_top.v | 205 ++++------- projects/daq3/zc706/system_top.v | 254 +++++--------- projects/fmcadc2/common/fmcadc2_spi.v | 51 +-- projects/fmcadc2/vc707/system_top.v | 188 ++++------ projects/fmcadc2/zc706/system_top.v | 207 ++++------- projects/fmcadc4/common/fmcadc4_spi.v | 21 +- projects/fmcadc4/zc706/system_top.v | 230 ++++--------- projects/fmcadc5/common/fmcadc5_psync.v | 17 +- projects/fmcadc5/common/fmcadc5_spi.v | 27 +- projects/fmcjesdadc1/common/fmcjesdadc1_spi.v | 23 +- projects/fmcjesdadc1/kc705/system_top.v | 175 +++------- projects/fmcjesdadc1/vc707/system_top.v | 161 +++------ projects/fmcjesdadc1/zc706/system_top.v | 125 +++---- projects/fmcomms2/a10gx/system_top.v | 154 +++------ projects/fmcomms2/ac701/system_top.v | 187 ++++------ projects/fmcomms2/common/prcfg.v | 171 +++------- projects/fmcomms2/kc705/system_top.v | 220 ++++-------- projects/fmcomms2/mitx045/system_top.v | 185 ++++------ projects/fmcomms2/vc707/system_top.v | 206 ++++------- projects/fmcomms2/zc702/system_top.v | 188 ++++------ projects/fmcomms2/zc706/system_top.v | 192 ++++------- projects/fmcomms2/zc706pr/system_top.v | 192 ++++------- projects/fmcomms2/zed/system_top.v | 214 ++++-------- projects/fmcomms5/zc702/system_top.v | 266 +++++---------- projects/fmcomms5/zc706/system_top.v | 266 +++++---------- projects/fmcomms5/zcu102/system_top.v | 177 ++++------ projects/fmcomms7/common/fmcomms7_spi.v | 24 +- projects/fmcomms7/zc706/system_top.v | 323 ++++++------------ projects/imageon/zc706/system_top.v | 109 ++---- projects/imageon/zed/system_top.v | 136 +++----- projects/motcon2_fmc/zed/system_top.v | 298 +++++----------- projects/usdrx1/common/usdrx1_spi.v | 27 +- projects/usdrx1/cpld/usdrx1_cpld.v | 55 +-- projects/usdrx1/zc706/system_top.v | 270 +++++---------- 264 files changed, 8090 insertions(+), 18421 deletions(-) diff --git a/library/altera/common/ad_cmos_clk.v b/library/altera/common/ad_cmos_clk.v index 735b8fb01..32165aeaa 100644 --- a/library/altera/common/ad_cmos_clk.v +++ b/library/altera/common/ad_cmos_clk.v @@ -37,21 +37,16 @@ `timescale 1ns/100ps -module ad_cmos_clk ( +module ad_cmos_clk #( - rst, - locked, + parameter DEVICE_TYPE = 0) ( - clk_in, - clk); + input rst, + output locked, - parameter DEVICE_TYPE = 0; + input clk_in, + output clk); - input rst; - output locked; - - input clk_in; - output clk; // instantiations diff --git a/library/altera/common/ad_cmos_in.v b/library/altera/common/ad_cmos_in.v index 4860361ea..5a3d77034 100644 --- a/library/altera/common/ad_cmos_in.v +++ b/library/altera/common/ad_cmos_in.v @@ -37,60 +37,36 @@ `timescale 1ns/100ps -module ad_cmos_in ( +module ad_cmos_in #( + + parameter SINGLE_ENDED = 0, + parameter DEVICE_TYPE = 0, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( // data interface - rx_clk, - rx_data_in, - rx_data_p, - rx_data_n, + input rx_clk, + input rx_data_in, + output reg rx_data_p, + output reg rx_data_n, // delay-data interface - up_clk, - up_dld, - up_dwdata, - up_drdata, + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, // delay-cntrl interface - delay_clk, - delay_rst, - delay_locked); + input delay_clk, + input delay_rst, + output delay_locked); - // parameters - - parameter SINGLE_ENDED = 0; - parameter DEVICE_TYPE = 0; - parameter IODELAY_CTRL = 0; - parameter IODELAY_GROUP = "dev_if_delay_group"; - - // data interface - - input rx_clk; - input rx_data_in; - output rx_data_p; - output rx_data_n; - - // delay-data interface - - input up_clk; - input up_dld; - input [ 4:0] up_dwdata; - output [ 4:0] up_drdata; - - // delay-cntrl interface - - input delay_clk; - input delay_rst; - output delay_locked; // internal registers - reg rx_data_p = 'd0; - reg rx_data_n = 'd0; - // internal signals wire rx_data_p_s; diff --git a/library/altera/common/ad_lvds_clk.v b/library/altera/common/ad_lvds_clk.v index 983a94723..16ddcd247 100644 --- a/library/altera/common/ad_lvds_clk.v +++ b/library/altera/common/ad_lvds_clk.v @@ -37,23 +37,18 @@ `timescale 1ns/100ps -module ad_lvds_clk ( +module ad_lvds_clk #( - rst, - locked, + parameter DEVICE_TYPE = 0) ( - clk_in_p, - clk_in_n, - clk); + input rst, + output locked, - parameter DEVICE_TYPE = 0; + input clk_in_p, + input clk_in_n, + output clk); - input rst; - output locked; - input clk_in_p; - input clk_in_n; - output clk; // instantiations diff --git a/library/altera/common/ad_lvds_in.v b/library/altera/common/ad_lvds_in.v index 91774bdf1..80d309dab 100644 --- a/library/altera/common/ad_lvds_in.v +++ b/library/altera/common/ad_lvds_in.v @@ -37,62 +37,37 @@ `timescale 1ns/100ps -module ad_lvds_in ( +module ad_lvds_in #( + + parameter SINGLE_ENDED = 0, + parameter DEVICE_TYPE = 0, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( // data interface - rx_clk, - rx_data_in_p, - rx_data_in_n, - rx_data_p, - rx_data_n, + input rx_clk, + input rx_data_in_p, + input rx_data_in_n, + output reg rx_data_p, + output reg rx_data_n, // delay-data interface - up_clk, - up_dld, - up_dwdata, - up_drdata, + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, // delay-cntrl interface - delay_clk, - delay_rst, - delay_locked); + input delay_clk, + input delay_rst, + output delay_locked); - // parameters - - parameter SINGLE_ENDED = 0; - parameter DEVICE_TYPE = 0; - parameter IODELAY_CTRL = 0; - parameter IODELAY_GROUP = "dev_if_delay_group"; - - // data interface - - input rx_clk; - input rx_data_in_p; - input rx_data_in_n; - output rx_data_p; - output rx_data_n; - - // delay-data interface - - input up_clk; - input up_dld; - input [ 4:0] up_dwdata; - output [ 4:0] up_drdata; - - // delay-cntrl interface - - input delay_clk; - input delay_rst; - output delay_locked; // internal registers - reg rx_data_p = 'd0; - reg rx_data_n = 'd0; - // internal signals wire rx_data_p_s; diff --git a/library/altera/common/ad_lvds_out.v b/library/altera/common/ad_lvds_out.v index 9f8bf8cec..c8601c5be 100644 --- a/library/altera/common/ad_lvds_out.v +++ b/library/altera/common/ad_lvds_out.v @@ -37,57 +37,35 @@ `timescale 1ns/100ps -module ad_lvds_out ( +module ad_lvds_out #( + + parameter DEVICE_TYPE = 0, + parameter SINGLE_ENDED = 0, + parameter IODELAY_ENABLE = 0, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( // data interface - tx_clk, - tx_data_p, - tx_data_n, - tx_data_out_p, - tx_data_out_n, + input tx_clk, + input tx_data_p, + input tx_data_n, + output tx_data_out_p, + output tx_data_out_n, // delay-data interface - up_clk, - up_dld, - up_dwdata, - up_drdata, + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, // delay-cntrl interface - delay_clk, - delay_rst, - delay_locked); + input delay_clk, + input delay_rst, + output delay_locked); - // parameters - - parameter DEVICE_TYPE = 0; - parameter SINGLE_ENDED = 0; - parameter IODELAY_ENABLE = 0; - parameter IODELAY_CTRL = 0; - parameter IODELAY_GROUP = "dev_if_delay_group"; - - // data interface - - input tx_clk; - input tx_data_p; - input tx_data_n; - output tx_data_out_p; - output tx_data_out_n; - - // delay-data interface - - input up_clk; - input up_dld; - input [ 4:0] up_dwdata; - output [ 4:0] up_drdata; - - // delay-cntrl interface - - input delay_clk; - input delay_rst; - output delay_locked; // defaults diff --git a/library/altera/common/ad_mul.v b/library/altera/common/ad_mul.v index 896f9f185..7ef6ce51d 100644 --- a/library/altera/common/ad_mul.v +++ b/library/altera/common/ad_mul.v @@ -39,41 +39,27 @@ `timescale 1ps/1ps -module ad_mul ( +module ad_mul #( + + parameter DELAY_DATA_WIDTH = 16) ( // data_p = data_a * data_b; - clk, - data_a, - data_b, - data_p, + input clk, + input [16:0] data_a, + input [16:0] data_b, + output [33:0] data_p, // delay interface - ddata_in, - ddata_out); + input [(DELAY_DATA_WIDTH-1):0] ddata_in, + output reg [(DELAY_DATA_WIDTH-1):0] ddata_out); - // delayed data bus width - - parameter DELAY_DATA_WIDTH = 16; - - // data_p = data_a * data_b; - - input clk; - input [16:0] data_a; - input [16:0] data_b; - output [33:0] data_p; - - // delay interface - - input [(DELAY_DATA_WIDTH-1):0] ddata_in; - output [(DELAY_DATA_WIDTH-1):0] ddata_out; // internal registers reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0; reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0; - reg [(DELAY_DATA_WIDTH-1):0] ddata_out = 'd0; // a/b reg, m-reg, p-reg delay match diff --git a/library/axi_ad6676/axi_ad6676.v b/library/axi_ad6676/axi_ad6676.v index 4de586635..115ab5902 100755 --- a/library/axi_ad6676/axi_ad6676.v +++ b/library/axi_ad6676/axi_ad6676.v @@ -39,103 +39,57 @@ `timescale 1ns/100ps -module axi_ad6676 ( +module axi_ad6676 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_valid, - rx_ready, - rx_data, + input rx_clk, + input [ 3:0] rx_sof, + input rx_valid, + output rx_ready, + input [63:0] rx_data, // dma interface - adc_clk, - adc_rst, - adc_valid_0, - adc_enable_0, - adc_data_0, - adc_valid_1, - adc_enable_1, - adc_data_1, - adc_dovf, - adc_dunf, + output adc_clk, + output adc_rst, + output adc_valid_0, + output adc_enable_0, + output [31:0] adc_data_0, + output adc_valid_1, + output adc_enable_1, + output [31:0] adc_data_1, + input adc_dovf, + input adc_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [ 3:0] rx_sof; - input rx_valid; - output rx_ready; - input [63:0] rx_data; - - // dma interface - - output adc_clk; - output adc_rst; - output adc_valid_0; - output adc_enable_0; - output [31:0] adc_data_0; - output adc_valid_1; - output adc_enable_1; - output [31:0] adc_data_1; - input adc_dovf; - input adc_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal registers diff --git a/library/axi_ad6676/axi_ad6676_channel.v b/library/axi_ad6676/axi_ad6676_channel.v index 63299c6ff..37b3b4ef9 100755 --- a/library/axi_ad6676/axi_ad6676_channel.v +++ b/library/axi_ad6676/axi_ad6676_channel.v @@ -40,68 +40,39 @@ `timescale 1ns/100ps -module axi_ad6676_channel ( +module axi_ad6676_channel #( + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0) ( // adc interface - adc_clk, - adc_rst, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input [31:0] adc_data, + input adc_or, // channel interface - adc_dfmt_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [31:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter Q_OR_I_N = 0; - parameter CHANNEL_ID = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input [31:0] adc_data; - input adc_or; - - // channel interface - - output [31:0] adc_dfmt_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad6676/axi_ad6676_if.v b/library/axi_ad6676/axi_ad6676_if.v index ecd68a454..c598b1eb5 100755 --- a/library/axi_ad6676/axi_ad6676_if.v +++ b/library/axi_ad6676/axi_ad6676_if.v @@ -39,49 +39,30 @@ `timescale 1ns/100ps -module axi_ad6676_if ( +module axi_ad6676_if #( + + parameter DEVICE_TYPE = 0) ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_data, + input rx_clk, + input [ 3:0] rx_sof, + input [63:0] rx_data, // adc data output - adc_clk, - adc_rst, - adc_data_a, - adc_data_b, - adc_or_a, - adc_or_b, - adc_status); + output adc_clk, + input adc_rst, + output [31:0] adc_data_a, + output [31:0] adc_data_b, + output adc_or_a, + output adc_or_b, + output reg adc_status); - // parameters - - parameter DEVICE_TYPE = 0; - - // jesd interface - - input rx_clk; - input [ 3:0] rx_sof; - input [63:0] rx_data; - - // adc data output - - output adc_clk; - input adc_rst; - output [31:0] adc_data_a; - output [31:0] adc_data_b; - output adc_or_a; - output adc_or_b; - output adc_status; // internal registers - reg adc_status = 'd0; - // internal signals wire [15:0] adc_data_a_s1_s; diff --git a/library/axi_ad6676/axi_ad6676_pnmon.v b/library/axi_ad6676/axi_ad6676_pnmon.v index fff17b1a0..a4faba4ab 100755 --- a/library/axi_ad6676/axi_ad6676_pnmon.v +++ b/library/axi_ad6676/axi_ad6676_pnmon.v @@ -44,31 +44,17 @@ module axi_ad6676_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [31:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, + output adc_pn_oos, + output adc_pn_err, // processor interface - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [31:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - - // processor interface PN9 (0x0), PN23 (0x1) - - input [ 3:0] adc_pnseq_sel; + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v index 8027d41c5..846c70544 100644 --- a/library/axi_ad7616/axi_ad7616.v +++ b/library/axi_ad7616/axi_ad7616.v @@ -39,66 +39,62 @@ `timescale 1ns/100ps -module axi_ad7616 ( +module axi_ad7616 #( + + parameter ID = 0, + parameter IF_TYPE = 1) ( // physical data interface - rx_sclk, - rx_cs_n, - rx_sdo, - rx_sdi_0, - rx_sdi_1, + output rx_sclk, + output rx_cs_n, + output rx_sdo, + input rx_sdi_0, + input rx_sdi_1, - rx_db_o, - rx_db_i, - rx_db_t, - rx_rd_n, - rx_wr_n, + output [15:0] rx_db_o, + input [15:0] rx_db_i, + output rx_db_t, + output rx_rd_n, + output rx_wr_n, // physical control interface - rx_cnvst, - rx_busy, + output rx_cnvst, + input rx_busy, // AXI Slave Memory Map - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, // Write FIFO interface - adc_valid, - adc_data, - adc_sync, + output adc_valid, + output [15:0] adc_data, + output adc_sync, - irq -); + output irq); - // parameters - - parameter ID = 0; - parameter IF_TYPE = 1; - - // local parameters localparam NUM_OF_SDI = 2; localparam SERIAL = 0; @@ -106,52 +102,6 @@ module axi_ad7616 ( localparam NEG_EDGE = 1; localparam UP_ADDRESS_WIDTH = 14; - // IO definitions - - output rx_sclk; - output rx_cs_n; - output rx_sdo; - input rx_sdi_0; - input rx_sdi_1; - - output [15:0] rx_db_o; - input [15:0] rx_db_i; - output rx_db_t; - output rx_rd_n; - output rx_wr_n; - - output rx_cnvst; - input rx_busy; - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; - - - output adc_valid; - output [15:0] adc_data; - output adc_sync; - - output irq; - // internal registers reg up_wack = 1'b0; diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v index af013aa96..bf272823c 100644 --- a/library/axi_ad7616/axi_ad7616_control.v +++ b/library/axi_ad7616/axi_ad7616_control.v @@ -39,39 +39,39 @@ `timescale 1ns/100ps -module axi_ad7616_control ( +module axi_ad7616_control #( + + parameter ID = 0, + parameter IF_TYPE = 0) ( // control signals - cnvst, - busy, + output cnvst, + input busy, - up_read_data, - up_read_valid, - up_write_data, - up_read_req, - up_write_req, + input [15:0] up_read_data, + input up_read_valid, + output reg [15:0] up_write_data, + output up_read_req, + output up_write_req, - up_burst_length, - end_of_conv, + output reg [ 4:0] up_burst_length, + output end_of_conv, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack - + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack ); - parameter ID = 0; - parameter IF_TYPE = 0; localparam PCORE_VERSION = 'h0001001; localparam POS_EDGE = 0; @@ -79,42 +79,12 @@ module axi_ad7616_control ( localparam SERIAL = 0; localparam PARALLEL = 1; - output cnvst; - input busy; - - output end_of_conv; - output [ 4:0] up_burst_length; - - input [15:0] up_read_data; - input up_read_valid; - output [15:0] up_write_data; - output up_read_req; - output up_write_req; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - // internal signals reg [31:0] up_scratch = 32'b0; reg up_resetn = 1'b0; reg up_cnvst_en = 1'b0; - reg up_wack = 1'b0; - reg up_rack = 1'b0; - reg [31:0] up_rdata = 32'b0; reg [31:0] up_conv_rate = 32'b0; - reg [ 4:0] up_burst_length = 5'h0; - reg [15:0] up_write_data = 16'h0; reg [31:0] cnvst_counter = 32'b0; reg [ 3:0] pulse_counter = 8'b0; diff --git a/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v index 03448feed..dcf4146bf 100644 --- a/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v +++ b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v @@ -39,49 +39,29 @@ `timescale 1ns/100ps -module axi_ad7616_maxis2wrfifo ( +module axi_ad7616_maxis2wrfifo #( - clk, - rstn, - sync_in, + parameter DATA_WIDTH = 16) ( + + input clk, + input rstn, + input sync_in, // m_axis interface - m_axis_data, - m_axis_ready, - m_axis_valid, - m_axis_xfer_req, + input [DATA_WIDTH-1:0] m_axis_data, + output reg m_axis_ready, + input m_axis_valid, + output reg m_axis_xfer_req, // write fifo interface - fifo_wr_en, - fifo_wr_data, - fifo_wr_sync, - fifo_wr_xfer_req - + output reg fifo_wr_en, + output reg [DATA_WIDTH-1:0] fifo_wr_data, + output reg fifo_wr_sync, + input fifo_wr_xfer_req ); - parameter DATA_WIDTH = 16; - - input clk; - input rstn; - input sync_in; - - input [DATA_WIDTH-1:0] m_axis_data; - output m_axis_ready; - input m_axis_valid; - output m_axis_xfer_req; - - output fifo_wr_en; - output [DATA_WIDTH-1:0] fifo_wr_data; - output fifo_wr_sync; - input fifo_wr_xfer_req; - - reg m_axis_ready = 1'b0; - reg m_axis_xfer_req = 1'b0; - reg fifo_wr_en = 1'b0; - reg [DATA_WIDTH-1:0] fifo_wr_data = 'b0; - reg fifo_wr_sync = 1'b0; always @(posedge clk) begin if (rstn == 1'b0) begin diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v index 491222f30..89aba8d80 100644 --- a/library/axi_ad7616/axi_ad7616_pif.v +++ b/library/axi_ad7616/axi_ad7616_pif.v @@ -39,64 +39,40 @@ `timescale 1ns/100ps -module axi_ad7616_pif ( +module axi_ad7616_pif #( + + parameter UP_ADDRESS_WIDTH = 14) ( // physical interface - cs_n, - db_o, - db_i, - db_t, - rd_n, - wr_n, + output cs_n, + output [15:0] db_o, + input [15:0] db_i, + output db_t, + output rd_n, + output wr_n, // FIFO interface - adc_data, - adc_valid, - adc_sync, + output [15:0] adc_data, + output adc_valid, + output reg adc_sync, // end of convertion - end_of_conv, - burst_length, + input end_of_conv, + input [ 4:0] burst_length, // register access - clk, - rstn, - rd_req, - wr_req, - wr_data, - rd_data, - rd_valid -); + input clk, + input rstn, + input rd_req, + input wr_req, + input [15:0] wr_data, + output reg [15:0] rd_data, + output reg rd_valid); - parameter UP_ADDRESS_WIDTH = 14; - - // IO definitions - - output cs_n; - output [15:0] db_o; - input [15:0] db_i; - output db_t; - output rd_n; - output wr_n; - - input end_of_conv; - input [ 4:0] burst_length; - - input clk; - input rstn; - input rd_req; - input wr_req; - input [15:0] wr_data; - output [15:0] rd_data; - output rd_valid; - - output [15:0] adc_data; - output adc_valid; - output adc_sync; // state registers @@ -121,10 +97,7 @@ module axi_ad7616_pif ( reg xfer_req_d = 1'h0; - reg adc_sync = 1'h0; - reg rd_valid = 1'h0; reg rd_valid_d = 1'h0; - reg [15:0] rd_data = 16'h0; // internal wires diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v index c20ceeb8d..64072e426 100644 --- a/library/axi_ad9122/axi_ad9122.v +++ b/library/axi_ad9122/axi_ad9122.v @@ -37,125 +37,71 @@ `timescale 1ns/100ps -module axi_ad9122 ( +module axi_ad9122 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter SERDES_OR_DDR_N = 1, + parameter MMCM_OR_BUFIO_N = 1, + parameter MMCM_CLKIN_PERIOD = 1.667, + parameter MMCM_VCO_DIV = 2, + parameter MMCM_VCO_MUL = 4, + parameter MMCM_CLK0_DIV = 2, + parameter MMCM_CLK1_DIV = 8, + parameter DAC_DATAPATH_DISABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // dac interface - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_frame_out_p, - dac_frame_out_n, - dac_data_out_p, - dac_data_out_n, + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output dac_frame_out_p, + output dac_frame_out_n, + output [15:0] dac_data_out_p, + output [15:0] dac_data_out_n, // master/slave - dac_sync_out, - dac_sync_in, + output dac_sync_out, + input dac_sync_in, // dma interface - dac_div_clk, - dac_valid_0, - dac_enable_0, - dac_ddata_0, - dac_valid_1, - dac_enable_1, - dac_ddata_1, - dac_dovf, - dac_dunf, + output dac_div_clk, + output dac_valid_0, + output dac_enable_0, + input [63:0] dac_ddata_0, + output dac_valid_1, + output dac_enable_1, + input [63:0] dac_ddata_1, + input dac_dovf, + input dac_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter SERDES_OR_DDR_N = 1; - parameter MMCM_OR_BUFIO_N = 1; - parameter MMCM_CLKIN_PERIOD = 1.667; - parameter MMCM_VCO_DIV = 2; - parameter MMCM_VCO_MUL = 4; - parameter MMCM_CLK0_DIV = 2; - parameter MMCM_CLK1_DIV = 8; - parameter DAC_DATAPATH_DISABLE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // dac interface - - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output dac_frame_out_p; - output dac_frame_out_n; - output [15:0] dac_data_out_p; - output [15:0] dac_data_out_n; - - // master/slave - - output dac_sync_out; - input dac_sync_in; - - // dma interface - - output dac_div_clk; - output dac_valid_0; - output dac_enable_0; - input [63:0] dac_ddata_0; - output dac_valid_1; - output dac_enable_1; - input [63:0] dac_ddata_1; - input dac_dovf; - input dac_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal clocks and resets diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v index d936f9048..93070e1bd 100644 --- a/library/axi_ad9122/axi_ad9122_channel.v +++ b/library/axi_ad9122/axi_ad9122_channel.v @@ -39,74 +39,42 @@ `timescale 1ns/100ps -module axi_ad9122_channel ( +module axi_ad9122_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_div_clk, - dac_rst, - dac_enable, - dac_data, - dac_frame, - dma_data, + input dac_div_clk, + input dac_rst, + output reg dac_enable, + output reg [63:0] dac_data, + output reg [ 3:0] dac_frame, + input [63:0] dma_data, // processor interface - dac_data_frame, - dac_data_sync, - dac_dds_format, + input dac_data_frame, + input dac_data_sync, + input dac_dds_format, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter CHANNEL_ID = 32'h0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_div_clk; - input dac_rst; - output dac_enable; - output [63:0] dac_data; - output [ 3:0] dac_frame; - input [63:0] dma_data; - - // processor interface - - input dac_data_frame; - input dac_data_sync; - input dac_dds_format; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg dac_enable = 'd0; - reg [63:0] dac_data = 'd0; - reg [ 3:0] dac_frame = 'd0; reg [15:0] dac_dds_phase_0_0 = 'd0; reg [15:0] dac_dds_phase_0_1 = 'd0; reg [15:0] dac_dds_phase_1_0 = 'd0; diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v index d3b79271c..be6ccbf8c 100644 --- a/library/axi_ad9122/axi_ad9122_core.v +++ b/library/axi_ad9122/axi_ad9122_core.v @@ -37,149 +37,79 @@ `timescale 1ns/100ps -module axi_ad9122_core ( +module axi_ad9122_core #( + + parameter ID = 0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_div_clk, - dac_rst, - dac_frame_i0, - dac_data_i0, - dac_frame_i1, - dac_data_i1, - dac_frame_i2, - dac_data_i2, - dac_frame_i3, - dac_data_i3, - dac_frame_q0, - dac_data_q0, - dac_frame_q1, - dac_data_q1, - dac_frame_q2, - dac_data_q2, - dac_frame_q3, - dac_data_q3, - dac_status, + input dac_div_clk, + output dac_rst, + output dac_frame_i0, + output [15:0] dac_data_i0, + output dac_frame_i1, + output [15:0] dac_data_i1, + output dac_frame_i2, + output [15:0] dac_data_i2, + output dac_frame_i3, + output [15:0] dac_data_i3, + output dac_frame_q0, + output [15:0] dac_data_q0, + output dac_frame_q1, + output [15:0] dac_data_q1, + output dac_frame_q2, + output [15:0] dac_data_q2, + output dac_frame_q3, + output [15:0] dac_data_q3, + input dac_status, // master/slave - dac_sync_out, - dac_sync_in, + output dac_sync_out, + input dac_sync_in, // dma interface - dac_valid_0, - dac_enable_0, - dac_ddata_0, - dac_valid_1, - dac_enable_1, - dac_ddata_1, - dac_dovf, - dac_dunf, + output dac_valid_0, + output dac_enable_0, + input [63:0] dac_ddata_0, + output dac_valid_1, + output dac_enable_1, + input [63:0] dac_ddata_1, + input dac_dovf, + input dac_dunf, // mmcm reset - mmcm_rst, + output mmcm_rst, // drp interface - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked, + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); - // parameters - - parameter ID = 0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_div_clk; - output dac_rst; - output dac_frame_i0; - output [15:0] dac_data_i0; - output dac_frame_i1; - output [15:0] dac_data_i1; - output dac_frame_i2; - output [15:0] dac_data_i2; - output dac_frame_i3; - output [15:0] dac_data_i3; - output dac_frame_q0; - output [15:0] dac_data_q0; - output dac_frame_q1; - output [15:0] dac_data_q1; - output dac_frame_q2; - output [15:0] dac_data_q2; - output dac_frame_q3; - output [15:0] dac_data_q3; - input dac_status; - - // master/slave - - output dac_sync_out; - input dac_sync_in; - - // dma interface - - output dac_valid_0; - output dac_enable_0; - input [63:0] dac_ddata_0; - output dac_valid_1; - output dac_enable_1; - input [63:0] dac_ddata_1; - input dac_dovf; - input dac_dunf; - - // mmcm reset - - output mmcm_rst; - - // drp interface - - output up_drp_sel; - output up_drp_wr; - output [11:0] up_drp_addr; - output [31:0] up_drp_wdata; - input [31:0] up_drp_rdata; - input up_drp_ready; - input up_drp_locked; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg [31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; - // internal signals wire dac_sync_s; diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v index 4eb921561..df4391fac 100644 --- a/library/axi_ad9122/axi_ad9122_if.v +++ b/library/axi_ad9122/axi_ad9122_if.v @@ -39,132 +39,76 @@ `timescale 1ns/100ps -module axi_ad9122_if ( +module axi_ad9122_if #( + + parameter DEVICE_TYPE = 0, + parameter SERDES_OR_DDR_N = 1, + parameter MMCM_OR_BUFIO_N = 1, + parameter MMCM_CLKIN_PERIOD = 1.667, + parameter MMCM_VCO_DIV = 6, + parameter MMCM_VCO_MUL = 12, + parameter MMCM_CLK0_DIV = 2, + parameter MMCM_CLK1_DIV = 8, + parameter IO_DELAY_GROUP = "dac_if_delay_group") ( // dac interface - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_frame_out_p, - dac_frame_out_n, - dac_data_out_p, - dac_data_out_n, + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output dac_frame_out_p, + output dac_frame_out_n, + output [15:0] dac_data_out_p, + output [15:0] dac_data_out_n, // internal resets and clocks - dac_rst, - dac_clk, - dac_div_clk, - dac_status, + input dac_rst, + output dac_clk, + output dac_div_clk, + output reg dac_status, // data interface - dac_frame_i0, - dac_data_i0, - dac_frame_i1, - dac_data_i1, - dac_frame_i2, - dac_data_i2, - dac_frame_i3, - dac_data_i3, + input dac_frame_i0, + input [15:0] dac_data_i0, + input dac_frame_i1, + input [15:0] dac_data_i1, + input dac_frame_i2, + input [15:0] dac_data_i2, + input dac_frame_i3, + input [15:0] dac_data_i3, - dac_frame_q0, - dac_data_q0, - dac_frame_q1, - dac_data_q1, - dac_frame_q2, - dac_data_q2, - dac_frame_q3, - dac_data_q3, + input dac_frame_q0, + input [15:0] dac_data_q0, + input dac_frame_q1, + input [15:0] dac_data_q1, + input dac_frame_q2, + input [15:0] dac_data_q2, + input dac_frame_q3, + input [15:0] dac_data_q3, // mmcm reset - mmcm_rst, + input mmcm_rst, // drp interface - up_clk, - up_rstn, - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked); + input up_clk, + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked); - // parameters - - parameter DEVICE_TYPE = 0; - parameter SERDES_OR_DDR_N = 1; - parameter MMCM_OR_BUFIO_N = 1; - parameter MMCM_CLKIN_PERIOD = 1.667; - parameter MMCM_VCO_DIV = 6; - parameter MMCM_VCO_MUL = 12; - parameter MMCM_CLK0_DIV = 2; - parameter MMCM_CLK1_DIV = 8; - parameter IO_DELAY_GROUP = "dac_if_delay_group"; - - // dac interface - - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output dac_frame_out_p; - output dac_frame_out_n; - output [15:0] dac_data_out_p; - output [15:0] dac_data_out_n; - - // internal resets and clocks - - input dac_rst; - output dac_clk; - output dac_div_clk; - output dac_status; - - // data interface - - input dac_frame_i0; - input [15:0] dac_data_i0; - input dac_frame_i1; - input [15:0] dac_data_i1; - input dac_frame_i2; - input [15:0] dac_data_i2; - input dac_frame_i3; - input [15:0] dac_data_i3; - - input dac_frame_q0; - input [15:0] dac_data_q0; - input dac_frame_q1; - input [15:0] dac_data_q1; - input dac_frame_q2; - input [15:0] dac_data_q2; - input dac_frame_q3; - input [15:0] dac_data_q3; - - // mmcm reset - - input mmcm_rst; - - // drp interface - - input up_clk; - input up_rstn; - input up_drp_sel; - input up_drp_wr; - input [11:0] up_drp_addr; - input [31:0] up_drp_wdata; - output [31:0] up_drp_rdata; - output up_drp_ready; - output up_drp_locked; // internal registers reg dac_status_m1 = 'd0; - reg dac_status = 'd0; // internal signals diff --git a/library/axi_ad9144/axi_ad9144.v b/library/axi_ad9144/axi_ad9144.v index 5aa391974..94ae1d01c 100644 --- a/library/axi_ad9144/axi_ad9144.v +++ b/library/axi_ad9144/axi_ad9144.v @@ -37,114 +37,63 @@ `timescale 1ns/100ps -module axi_ad9144 ( +module axi_ad9144 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter QUAD_OR_DUAL_N = 1, + parameter DAC_DATAPATH_DISABLE = 0) ( // jesd interface // tx_clk is (line-rate/40) - tx_clk, - tx_valid, - tx_data, - tx_ready, + input tx_clk, + output tx_valid, + output [(128*QUAD_OR_DUAL_N)+127:0] tx_data, + input tx_ready, // dma interface - dac_clk, - dac_valid_0, - dac_enable_0, - dac_ddata_0, - dac_valid_1, - dac_enable_1, - dac_ddata_1, - dac_valid_2, - dac_enable_2, - dac_ddata_2, - dac_valid_3, - dac_enable_3, - dac_ddata_3, - dac_dovf, - dac_dunf, + output dac_clk, + output dac_valid_0, + output dac_enable_0, + input [63:0] dac_ddata_0, + output dac_valid_1, + output dac_enable_1, + input [63:0] dac_ddata_1, + output dac_valid_2, + output dac_enable_2, + input [63:0] dac_ddata_2, + output dac_valid_3, + output dac_enable_3, + input [63:0] dac_ddata_3, + input dac_dovf, + input dac_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready); + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter QUAD_OR_DUAL_N = 1; - parameter DAC_DATAPATH_DISABLE = 0; - - // jesd interface - // tx_clk is (line-rate/40) - - input tx_clk; - output tx_valid; - output [(128*QUAD_OR_DUAL_N)+127:0] tx_data; - input tx_ready; - - // dma interface - - output dac_clk; - output dac_valid_0; - output dac_enable_0; - input [63:0] dac_ddata_0; - output dac_valid_1; - output dac_enable_1; - input [63:0] dac_ddata_1; - output dac_valid_2; - output dac_enable_2; - input [63:0] dac_ddata_2; - output dac_valid_3; - output dac_enable_3; - input [63:0] dac_ddata_3; - input dac_dovf; - input dac_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; // internal clocks and resets diff --git a/library/axi_ad9144/axi_ad9144_channel.v b/library/axi_ad9144/axi_ad9144_channel.v index 7794a4a5c..6cf6838e7 100644 --- a/library/axi_ad9144/axi_ad9144_channel.v +++ b/library/axi_ad9144/axi_ad9144_channel.v @@ -37,69 +37,40 @@ `timescale 1ns/100ps -module axi_ad9144_channel ( +module axi_ad9144_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_clk, - dac_rst, - dac_enable, - dac_data, - dma_data, + input dac_clk, + input dac_rst, + output reg dac_enable, + output reg [63:0] dac_data, + input [63:0] dma_data, // processor interface - dac_data_sync, - dac_dds_format, + input dac_data_sync, + input dac_dds_format, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter CHANNEL_ID = 32'h0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_clk; - input dac_rst; - output dac_enable; - output [63:0] dac_data; - input [63:0] dma_data; - - // processor interface - - input dac_data_sync; - input dac_dds_format; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg dac_enable = 'd0; - reg [63:0] dac_data = 'd0; reg [63:0] dac_pn7_data = 'd0; reg [63:0] dac_pn15_data = 'd0; reg [15:0] dac_dds_phase_0_0 = 'd0; @@ -456,6 +427,4 @@ endmodule // *************************************************************************** // *************************************************************************** - - diff --git a/library/axi_ad9144/axi_ad9144_core.v b/library/axi_ad9144/axi_ad9144_core.v index 8d4f9b0a1..73c014d5a 100644 --- a/library/axi_ad9144/axi_ad9144_core.v +++ b/library/axi_ad9144/axi_ad9144_core.v @@ -39,121 +39,65 @@ `timescale 1ns/100ps -module axi_ad9144_core ( +module axi_ad9144_core #( + + parameter ID = 0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_clk, - dac_rst, - dac_data_0_0, - dac_data_0_1, - dac_data_0_2, - dac_data_0_3, - dac_data_1_0, - dac_data_1_1, - dac_data_1_2, - dac_data_1_3, - dac_data_2_0, - dac_data_2_1, - dac_data_2_2, - dac_data_2_3, - dac_data_3_0, - dac_data_3_1, - dac_data_3_2, - dac_data_3_3, + input dac_clk, + output dac_rst, + output [15:0] dac_data_0_0, + output [15:0] dac_data_0_1, + output [15:0] dac_data_0_2, + output [15:0] dac_data_0_3, + output [15:0] dac_data_1_0, + output [15:0] dac_data_1_1, + output [15:0] dac_data_1_2, + output [15:0] dac_data_1_3, + output [15:0] dac_data_2_0, + output [15:0] dac_data_2_1, + output [15:0] dac_data_2_2, + output [15:0] dac_data_2_3, + output [15:0] dac_data_3_0, + output [15:0] dac_data_3_1, + output [15:0] dac_data_3_2, + output [15:0] dac_data_3_3, // dma interface - dac_valid_0, - dac_enable_0, - dac_ddata_0, - dac_valid_1, - dac_enable_1, - dac_ddata_1, - dac_valid_2, - dac_enable_2, - dac_ddata_2, - dac_valid_3, - dac_enable_3, - dac_ddata_3, - dac_dovf, - dac_dunf, + output dac_valid_0, + output dac_enable_0, + input [63:0] dac_ddata_0, + output dac_valid_1, + output dac_enable_1, + input [63:0] dac_ddata_1, + output dac_valid_2, + output dac_enable_2, + input [63:0] dac_ddata_2, + output dac_valid_3, + output dac_enable_3, + input [63:0] dac_ddata_3, + input dac_dovf, + input dac_dunf, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); - // parameters - - parameter ID = 0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_clk; - output dac_rst; - output [15:0] dac_data_0_0; - output [15:0] dac_data_0_1; - output [15:0] dac_data_0_2; - output [15:0] dac_data_0_3; - output [15:0] dac_data_1_0; - output [15:0] dac_data_1_1; - output [15:0] dac_data_1_2; - output [15:0] dac_data_1_3; - output [15:0] dac_data_2_0; - output [15:0] dac_data_2_1; - output [15:0] dac_data_2_2; - output [15:0] dac_data_2_3; - output [15:0] dac_data_3_0; - output [15:0] dac_data_3_1; - output [15:0] dac_data_3_2; - output [15:0] dac_data_3_3; - - // dma interface - - output dac_valid_0; - output dac_enable_0; - input [63:0] dac_ddata_0; - output dac_valid_1; - output dac_enable_1; - input [63:0] dac_ddata_1; - output dac_valid_2; - output dac_enable_2; - input [63:0] dac_ddata_2; - output dac_valid_3; - output dac_enable_3; - input [63:0] dac_ddata_3; - input dac_dovf; - input dac_dunf; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg [31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; - // internal signals wire dac_sync_s; diff --git a/library/axi_ad9144/axi_ad9144_if.v b/library/axi_ad9144/axi_ad9144_if.v index 7d3836631..671e34b57 100644 --- a/library/axi_ad9144/axi_ad9144_if.v +++ b/library/axi_ad9144/axi_ad9144_if.v @@ -37,70 +37,40 @@ `timescale 1ns/100ps -module axi_ad9144_if ( +module axi_ad9144_if #( + + parameter DEVICE_TYPE = 0) ( // jesd interface // tx_clk is (line-rate/40) - tx_clk, - tx_data, + input tx_clk, + output reg [255:0] tx_data, // dac interface - dac_clk, - dac_rst, - dac_data_0_0, - dac_data_0_1, - dac_data_0_2, - dac_data_0_3, - dac_data_1_0, - dac_data_1_1, - dac_data_1_2, - dac_data_1_3, - dac_data_2_0, - dac_data_2_1, - dac_data_2_2, - dac_data_2_3, - dac_data_3_0, - dac_data_3_1, - dac_data_3_2, - dac_data_3_3); + output dac_clk, + input dac_rst, + input [15:0] dac_data_0_0, + input [15:0] dac_data_0_1, + input [15:0] dac_data_0_2, + input [15:0] dac_data_0_3, + input [15:0] dac_data_1_0, + input [15:0] dac_data_1_1, + input [15:0] dac_data_1_2, + input [15:0] dac_data_1_3, + input [15:0] dac_data_2_0, + input [15:0] dac_data_2_1, + input [15:0] dac_data_2_2, + input [15:0] dac_data_2_3, + input [15:0] dac_data_3_0, + input [15:0] dac_data_3_1, + input [15:0] dac_data_3_2, + input [15:0] dac_data_3_3); - // altera (0x1) or xilinx (0x0) - - parameter DEVICE_TYPE = 0; - - // jesd interface - // tx_clk is (line-rate/40) - - input tx_clk; - output [255:0] tx_data; - - // dac interface - - output dac_clk; - input dac_rst; - input [15:0] dac_data_0_0; - input [15:0] dac_data_0_1; - input [15:0] dac_data_0_2; - input [15:0] dac_data_0_3; - input [15:0] dac_data_1_0; - input [15:0] dac_data_1_1; - input [15:0] dac_data_1_2; - input [15:0] dac_data_1_3; - input [15:0] dac_data_2_0; - input [15:0] dac_data_2_1; - input [15:0] dac_data_2_2; - input [15:0] dac_data_2_3; - input [15:0] dac_data_3_0; - input [15:0] dac_data_3_1; - input [15:0] dac_data_3_2; - input [15:0] dac_data_3_3; // internal registers - reg [255:0] tx_data = 'd0; - // reorder data for the jesd links assign dac_clk = tx_clk; diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v index 192c65a80..81ce1d5d8 100644 --- a/library/axi_ad9152/axi_ad9152.v +++ b/library/axi_ad9152/axi_ad9152.v @@ -39,101 +39,56 @@ `timescale 1ns/100ps -module axi_ad9152 ( +module axi_ad9152 #( + + parameter ID = 0, + parameter DAC_DATAPATH_DISABLE = 0, + parameter DEVICE_TYPE = 0) ( // jesd interface // tx_clk is (line-rate/40) - tx_clk, - tx_data, - tx_valid, - tx_ready, + input tx_clk, + output [127:0] tx_data, + output tx_valid, + input tx_ready, // dma interface - dac_clk, - dac_valid_0, - dac_enable_0, - dac_ddata_0, - dac_valid_1, - dac_enable_1, - dac_ddata_1, - dac_dovf, - dac_dunf, + output dac_clk, + output dac_valid_0, + output dac_enable_0, + input [ 63:0] dac_ddata_0, + output dac_valid_1, + output dac_enable_1, + input [ 63:0] dac_ddata_1, + input dac_dovf, + input dac_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready); + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); - // parameters - - parameter ID = 0; - parameter DAC_DATAPATH_DISABLE = 0; - parameter DEVICE_TYPE = 0; - - // jesd interface - // tx_clk is (line-rate/40) - - input tx_clk; - output [127:0] tx_data; - output tx_valid; - input tx_ready; - - // dma interface - - output dac_clk; - output dac_valid_0; - output dac_enable_0; - input [ 63:0] dac_ddata_0; - output dac_valid_1; - output dac_enable_1; - input [ 63:0] dac_ddata_1; - input dac_dovf; - input dac_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; // internal clocks and resets diff --git a/library/axi_ad9152/axi_ad9152_channel.v b/library/axi_ad9152/axi_ad9152_channel.v index 56f599594..91d34519a 100644 --- a/library/axi_ad9152/axi_ad9152_channel.v +++ b/library/axi_ad9152/axi_ad9152_channel.v @@ -37,69 +37,40 @@ `timescale 1ns/100ps -module axi_ad9152_channel ( +module axi_ad9152_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_clk, - dac_rst, - dac_enable, - dac_data, - dma_data, + input dac_clk, + input dac_rst, + output reg dac_enable, + output reg [63:0] dac_data, + input [63:0] dma_data, // processor interface - dac_data_sync, - dac_dds_format, + input dac_data_sync, + input dac_dds_format, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter CHANNEL_ID = 32'h0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_clk; - input dac_rst; - output dac_enable; - output [63:0] dac_data; - input [63:0] dma_data; - - // processor interface - - input dac_data_sync; - input dac_dds_format; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg dac_enable = 'd0; - reg [63:0] dac_data = 'd0; reg [63:0] dac_pn7_data = 'd0; reg [63:0] dac_pn15_data = 'd0; reg [15:0] dac_dds_phase_0_0 = 'd0; diff --git a/library/axi_ad9152/axi_ad9152_core.v b/library/axi_ad9152/axi_ad9152_core.v index e61643f74..c6bf8df32 100644 --- a/library/axi_ad9152/axi_ad9152_core.v +++ b/library/axi_ad9152/axi_ad9152_core.v @@ -39,93 +39,51 @@ `timescale 1ns/100ps -module axi_ad9152_core ( +module axi_ad9152_core #( + + parameter ID = 0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_clk, - dac_rst, - dac_data_0_0, - dac_data_0_1, - dac_data_0_2, - dac_data_0_3, - dac_data_1_0, - dac_data_1_1, - dac_data_1_2, - dac_data_1_3, + input dac_clk, + output dac_rst, + output [15:0] dac_data_0_0, + output [15:0] dac_data_0_1, + output [15:0] dac_data_0_2, + output [15:0] dac_data_0_3, + output [15:0] dac_data_1_0, + output [15:0] dac_data_1_1, + output [15:0] dac_data_1_2, + output [15:0] dac_data_1_3, // dma interface - dac_valid_0, - dac_enable_0, - dac_ddata_0, - dac_valid_1, - dac_enable_1, - dac_ddata_1, - dac_dovf, - dac_dunf, + output dac_valid_0, + output dac_enable_0, + input [63:0] dac_ddata_0, + output dac_valid_1, + output dac_enable_1, + input [63:0] dac_ddata_1, + input dac_dovf, + input dac_dunf, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); - // parameters - - parameter ID = 0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_clk; - output dac_rst; - output [15:0] dac_data_0_0; - output [15:0] dac_data_0_1; - output [15:0] dac_data_0_2; - output [15:0] dac_data_0_3; - output [15:0] dac_data_1_0; - output [15:0] dac_data_1_1; - output [15:0] dac_data_1_2; - output [15:0] dac_data_1_3; - - // dma interface - - output dac_valid_0; - output dac_enable_0; - input [63:0] dac_ddata_0; - output dac_valid_1; - output dac_enable_1; - input [63:0] dac_ddata_1; - input dac_dovf; - input dac_dunf; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg [31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; - // internal signals wire dac_sync_s; diff --git a/library/axi_ad9162/axi_ad9162.v b/library/axi_ad9162/axi_ad9162.v index 0912cbc2d..e8f30efff 100644 --- a/library/axi_ad9162/axi_ad9162.v +++ b/library/axi_ad9162/axi_ad9162.v @@ -37,95 +37,60 @@ `timescale 1ns / 1ps -module axi_ad9162 ( +module axi_ad9162 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter DAC_DATAPATH_DISABLE = 0) ( // jesd interface // tx_clk is (line-rate/40) - tx_clk, - tx_valid, - tx_data, - tx_ready, + input tx_clk, + output tx_valid, + output [255:0] tx_data, + input tx_ready, // dma interface - dac_clk, - dac_valid, - dac_enable, - dac_ddata, - dac_dovf, - dac_dunf, + output dac_clk, + output dac_valid, + output dac_enable, + input [255:0] dac_ddata, + input dac_dovf, + input dac_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready); + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); - // parameters - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter DAC_DATAPATH_DISABLE = 0; - // jesd interface - // tx_clk is (line-rate/40) - input tx_clk; - output tx_valid; - output [255:0] tx_data; - input tx_ready; - // dma interface - output dac_clk; - output dac_valid; - output dac_enable; - input [255:0] dac_ddata; - input dac_dovf; - input dac_dunf; - // axi interface - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; // internal clocks and resets diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v index d13fd047e..ddec94918 100644 --- a/library/axi_ad9162/axi_ad9162_channel.v +++ b/library/axi_ad9162/axi_ad9162_channel.v @@ -37,69 +37,47 @@ `timescale 1ns / 1ps -module axi_ad9162_channel ( +module axi_ad9162_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_clk, - dac_rst, - dac_enable, - dac_data, - dma_data, + input dac_clk, + input dac_rst, + output reg dac_enable, + output reg [255:0] dac_data, + input [255:0] dma_data, // processor interface - dac_data_sync, - dac_dds_format, + input dac_data_sync, + input dac_dds_format, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output [ 31:0] up_rdata, + output up_rack); - // parameters - parameter CHANNEL_ID = 32'h0; - parameter DATAPATH_DISABLE = 0; - // dac interface - input dac_clk; - input dac_rst; - output dac_enable; - output [255:0] dac_data; - input [255:0] dma_data; - // processor interface - input dac_data_sync; - input dac_dds_format; - // bus interface - input up_rstn; - input up_clk; - input up_wreq; - input [ 13:0] up_waddr; - input [ 31:0] up_wdata; - output up_wack; - input up_rreq; - input [ 13:0] up_raddr; - output [ 31:0] up_rdata; - output up_rack; // internal registers - reg dac_enable = 'd0; - reg [255:0] dac_data = 'd0; reg [255:0] dac_data_int = 'd0; reg [ 15:0] dac_dds_phase_00_0 = 'd0; reg [ 15:0] dac_dds_phase_00_1 = 'd0; diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v index 8f8555716..756e84061 100644 --- a/library/axi_ad9162/axi_ad9162_core.v +++ b/library/axi_ad9162/axi_ad9162_core.v @@ -37,73 +37,49 @@ `timescale 1ns / 1ps -module axi_ad9162_core ( +module axi_ad9162_core #( + + parameter ID = 0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_clk, - dac_rst, - dac_data, + input dac_clk, + output dac_rst, + output [255:0] dac_data, // dma interface - dac_valid, - dac_enable, - dac_ddata, - dac_dovf, - dac_dunf, + output dac_valid, + output dac_enable, + input [255:0] dac_ddata, + input dac_dovf, + input dac_dunf, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters - - parameter ID = 0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_clk; - output dac_rst; - output [255:0] dac_data; - - // dma interface - - output dac_valid; - output dac_enable; - input [255:0] dac_ddata; - input dac_dovf; - input dac_dunf; + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output reg [ 31:0] up_rdata, + output reg up_rack); + + + + + + - // processor interface - input up_rstn; - input up_clk; - input up_wreq; - input [ 13:0] up_waddr; - input [ 31:0] up_wdata; - output up_wack; - input up_rreq; - input [ 13:0] up_raddr; - output [ 31:0] up_rdata; - output up_rack; // internal registers - reg [ 31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; // internal signals diff --git a/library/axi_ad9162/axi_ad9162_if.v b/library/axi_ad9162/axi_ad9162_if.v index f114420a4..83664942e 100644 --- a/library/axi_ad9162/axi_ad9162_if.v +++ b/library/axi_ad9162/axi_ad9162_if.v @@ -37,39 +37,30 @@ `timescale 1ns / 1ps -module axi_ad9162_if ( +module axi_ad9162_if #( + + parameter DEVICE_TYPE = 0) ( // jesd interface // tx_clk is (line-rate/40) - tx_clk, - tx_data, + input tx_clk, + output reg [255:0] tx_data, // dac interface - dac_clk, - dac_rst, - dac_data); + output dac_clk, + input dac_rst, + input [255:0] dac_data); - // altera (0x1) or xilinx (0x0) - parameter DEVICE_TYPE = 0; - // jesd interface - // tx_clk is (line-rate/40) - input tx_clk; - output [255:0] tx_data; - // dac interface - output dac_clk; - input dac_rst; - input [255:0] dac_data; // internal registers - reg [255:0] tx_data = 'd0; // reorder data for the jesd links diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v index d26b48102..8968d1d1d 100644 --- a/library/axi_ad9234/axi_ad9234.v +++ b/library/axi_ad9234/axi_ad9234.v @@ -39,95 +39,53 @@ `timescale 1ns/100ps -module axi_ad9234 ( +module axi_ad9234 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_data, + input rx_clk, + input [127:0] rx_data, // dma interface - adc_clk, - adc_enable_0, - adc_valid_0, - adc_data_0, - adc_enable_1, - adc_valid_1, - adc_data_1, - adc_dovf, - adc_dunf, + output adc_clk, + output adc_enable_0, + output adc_valid_0, + output [63:0] adc_data_0, + output adc_enable_1, + output adc_valid_1, + output [63:0] adc_data_1, + input adc_dovf, + input adc_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [127:0] rx_data; - - // dma interface - - output adc_clk; - output adc_enable_0; - output adc_valid_0; - output [63:0] adc_data_0; - output adc_enable_1; - output adc_valid_1; - output [63:0] adc_data_1; - input adc_dovf; - input adc_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal registers diff --git a/library/axi_ad9234/axi_ad9234_channel.v b/library/axi_ad9234/axi_ad9234_channel.v index 6bb5c98dd..0e08f7bdd 100644 --- a/library/axi_ad9234/axi_ad9234_channel.v +++ b/library/axi_ad9234/axi_ad9234_channel.v @@ -40,68 +40,39 @@ `timescale 1ns/100ps -module axi_ad9234_channel ( +module axi_ad9234_channel #( + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0) ( // adc interface - adc_clk, - adc_rst, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input [63:0] adc_data, + input adc_or, // channel interface - adc_dfmt_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [63:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter Q_OR_I_N = 0; - parameter CHANNEL_ID = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input [63:0] adc_data; - input adc_or; - - // channel interface - - output [63:0] adc_dfmt_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad9234/axi_ad9234_if.v b/library/axi_ad9234/axi_ad9234_if.v index fa6f96913..b8debb516 100644 --- a/library/axi_ad9234/axi_ad9234_if.v +++ b/library/axi_ad9234/axi_ad9234_if.v @@ -45,39 +45,21 @@ module axi_ad9234_if ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_data, + input rx_clk, + input [127:0] rx_data, // adc data output - adc_clk, - adc_rst, - adc_data_a, - adc_data_b, - adc_or_a, - adc_or_b, - adc_status); - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [127:0] rx_data; - - // adc data output - - output adc_clk; - input adc_rst; - output [63:0] adc_data_a; - output [63:0] adc_data_b; - output adc_or_a; - output adc_or_b; - output adc_status; + output adc_clk, + input adc_rst, + output [63:0] adc_data_a, + output [63:0] adc_data_b, + output adc_or_a, + output adc_or_b, + output reg adc_status); // internal registers - reg adc_status = 'd0; - // internal signals wire [15:0] adc_data_a_s3_s; diff --git a/library/axi_ad9234/axi_ad9234_pnmon.v b/library/axi_ad9234/axi_ad9234_pnmon.v index d196cdcc9..ee70c315a 100644 --- a/library/axi_ad9234/axi_ad9234_pnmon.v +++ b/library/axi_ad9234/axi_ad9234_pnmon.v @@ -44,31 +44,17 @@ module axi_ad9234_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [63:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, + output adc_pn_oos, + output adc_pn_err, // processor interface PN9 (0x0), PN23 (0x1) - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [63:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - - // processor interface PN9 (0x0), PN23 (0x1) - - input [ 3:0] adc_pnseq_sel; + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v index 0367c7722..ad9f3ed42 100644 --- a/library/axi_ad9250/axi_ad9250.v +++ b/library/axi_ad9250/axi_ad9250.v @@ -37,102 +37,57 @@ `timescale 1ns/100ps -module axi_ad9250 ( +module axi_ad9250 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0) ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_valid, - rx_data, - rx_ready, + input rx_clk, + input [ 3:0] rx_sof, + input rx_valid, + input [63:0] rx_data, + output rx_ready, // dma interface - adc_clk, - adc_rst, - adc_valid_a, - adc_enable_a, - adc_data_a, - adc_valid_b, - adc_enable_b, - adc_data_b, - adc_dovf, - adc_dunf, + output adc_clk, + output adc_rst, + output adc_valid_a, + output adc_enable_a, + output [31:0] adc_data_a, + output adc_valid_b, + output adc_enable_b, + output [31:0] adc_data_b, + input adc_dovf, + input adc_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready); + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); - parameter ID = 0; - parameter DEVICE_TYPE = 0; - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [ 3:0] rx_sof; - input rx_valid; - input [63:0] rx_data; - output rx_ready; - - // dma interface - - output adc_clk; - output adc_rst; - output adc_valid_a; - output adc_enable_a; - output [31:0] adc_data_a; - output adc_valid_b; - output adc_enable_b; - output [31:0] adc_data_b; - input adc_dovf; - input adc_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; // internal registers diff --git a/library/axi_ad9250/axi_ad9250_channel.v b/library/axi_ad9250/axi_ad9250_channel.v index 41c766ad9..b650b6d75 100644 --- a/library/axi_ad9250/axi_ad9250_channel.v +++ b/library/axi_ad9250/axi_ad9250_channel.v @@ -40,68 +40,39 @@ `timescale 1ns/100ps -module axi_ad9250_channel ( +module axi_ad9250_channel #( + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0) ( // adc interface - adc_clk, - adc_rst, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input [27:0] adc_data, + input adc_or, // channel interface - adc_dfmt_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [31:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter Q_OR_I_N = 0; - parameter CHANNEL_ID = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input [27:0] adc_data; - input adc_or; - - // channel interface - - output [31:0] adc_dfmt_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad9250/axi_ad9250_if.v b/library/axi_ad9250/axi_ad9250_if.v index 0b8e603ff..0c54b9cf8 100644 --- a/library/axi_ad9250/axi_ad9250_if.v +++ b/library/axi_ad9250/axi_ad9250_if.v @@ -37,50 +37,30 @@ `timescale 1ns/100ps -module axi_ad9250_if ( +module axi_ad9250_if #( + + parameter DEVICE_TYPE = 0) ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_data, + input rx_clk, + input [ 3:0] rx_sof, + input [63:0] rx_data, // adc data output - adc_clk, - adc_rst, - adc_data_a, - adc_data_b, - adc_or_a, - adc_or_b, - adc_status); + output adc_clk, + input adc_rst, + output [27:0] adc_data_a, + output [27:0] adc_data_b, + output adc_or_a, + output adc_or_b, + output reg adc_status); - // parameters - - parameter DEVICE_TYPE = 0; - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [ 3:0] rx_sof; - input [63:0] rx_data; - - // adc data output - - output adc_clk; - input adc_rst; - output [27:0] adc_data_a; - output [27:0] adc_data_b; - output adc_or_a; - output adc_or_b; - output adc_status; // internal registers - reg adc_status = 'd0; - // internal signals wire [15:0] adc_data_a_s1_s; diff --git a/library/axi_ad9250/axi_ad9250_pnmon.v b/library/axi_ad9250/axi_ad9250_pnmon.v index 76cacfd1c..0b3ef3ef6 100644 --- a/library/axi_ad9250/axi_ad9250_pnmon.v +++ b/library/axi_ad9250/axi_ad9250_pnmon.v @@ -44,31 +44,17 @@ module axi_ad9250_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [27:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, + output adc_pn_oos, + output adc_pn_err, // processor interface - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [27:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - - // processor interface PN9 (0x0), PN23 (0x1) - - input [ 3:0] adc_pnseq_sel; + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v index 0ed145d04..67971474a 100644 --- a/library/axi_ad9265/axi_ad9265.v +++ b/library/axi_ad9265/axi_ad9265.v @@ -39,108 +39,59 @@ `timescale 1ns/100ps -module axi_ad9265 ( +module axi_ad9265 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter ADC_DATAPATH_DISABLE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // adc interface (clk, data, over-range) - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [ 7:0] adc_data_in_p, + input [ 7:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // delay interface - delay_clk, + input delay_clk, // dma interface - adc_clk, - adc_rst, - adc_valid, - adc_enable, - adc_data, - adc_dovf, - adc_dunf, + output adc_clk, + output adc_rst, + output adc_valid, + output adc_enable, + output [15:0] adc_data, + input adc_dovf, + input adc_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter ADC_DATAPATH_DISABLE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // adc interface (clk, data, over-range) - - input adc_clk_in_p; - input adc_clk_in_n; - input [ 7:0] adc_data_in_p; - input [ 7:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // delay interface - - input delay_clk; - - // dma interface - - output adc_clk; - output adc_rst; - output adc_valid; - output adc_enable; - output [15:0] adc_data; - input adc_dovf; - input adc_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal registers diff --git a/library/axi_ad9265/axi_ad9265_channel.v b/library/axi_ad9265/axi_ad9265_channel.v index cb5e76bca..052bd3d67 100644 --- a/library/axi_ad9265/axi_ad9265_channel.v +++ b/library/axi_ad9265/axi_ad9265_channel.v @@ -40,70 +40,40 @@ `timescale 1ns/100ps -module axi_ad9265_channel ( +module axi_ad9265_channel #( + + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0) ( // adc interface - adc_clk, - adc_rst, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input [15:0] adc_data, + input adc_or, // channel interface - adc_dcfilter_data_out, - adc_valid, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [15:0] adc_dcfilter_data_out, + output adc_valid, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter CHANNEL_ID = 0; - parameter DATAPATH_DISABLE = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input [15:0] adc_data; - input adc_or; - - // channel interface - - output [15:0] adc_dcfilter_data_out; - output adc_valid; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad9265/axi_ad9265_if.v b/library/axi_ad9265/axi_ad9265_if.v index 4225fa9f8..55d738f4e 100644 --- a/library/axi_ad9265/axi_ad9265_if.v +++ b/library/axi_ad9265/axi_ad9265_if.v @@ -39,76 +39,45 @@ `timescale 1ns/100ps -module axi_ad9265_if ( +module axi_ad9265_if #( + + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // adc interface (clk, data, over-range) // nominal clock 125 MHz, up to 300 MHz - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [ 7:0] adc_data_in_p, + input [ 7:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // interface outputs - adc_clk, - adc_data, - adc_or, - adc_status, + output adc_clk, + output reg [15:0] adc_data, + output reg adc_or, + output reg adc_status, // delay control signals - up_clk, - up_dld, - up_dwdata, - up_drdata, - delay_clk, - delay_rst, - delay_locked); + input up_clk, + input [ 8:0] up_dld, + input [44:0] up_dwdata, + output [44:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked); - // This parameter controls the buffer type based on the target device. - - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // adc interface (clk, data, over-range) - // nominal clock 125 MHz, up to 300 MHz - - input adc_clk_in_p; - input adc_clk_in_n; - input [ 7:0] adc_data_in_p; - input [ 7:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // interface outputs - - output adc_clk; - output [15:0] adc_data; - output adc_or; - output adc_status; - - // delay control signals - - input up_clk; - input [ 8:0] up_dld; - input [44:0] up_dwdata; - output [44:0] up_drdata; - input delay_clk; - input delay_rst; - output delay_locked; // internal registers - reg adc_status = 'd0; reg [ 7:0] adc_data_p = 'd0; reg [ 7:0] adc_data_n = 'd0; reg adc_or_p = 'd0; reg adc_or_n = 'd0; - reg [15:0] adc_data = 'd0; - reg adc_or = 'd0; // internal signals diff --git a/library/axi_ad9265/axi_ad9265_pnmon.v b/library/axi_ad9265/axi_ad9265_pnmon.v index ad4ae370b..4dd65f8f1 100644 --- a/library/axi_ad9265/axi_ad9265_pnmon.v +++ b/library/axi_ad9265/axi_ad9265_pnmon.v @@ -44,25 +44,14 @@ module axi_ad9265_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [15:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [15:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - input [ 3:0] adc_pnseq_sel; + output adc_pn_oos, + output adc_pn_err, + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9361/altera/axi_ad9361_cmos_if.v b/library/axi_ad9361/altera/axi_ad9361_cmos_if.v index 0ce506d71..5e6ecd9f3 100644 --- a/library/axi_ad9361/altera/axi_ad9361_cmos_if.v +++ b/library/axi_ad9361/altera/axi_ad9361_cmos_if.v @@ -37,133 +37,72 @@ `timescale 1ns/100ps -module axi_ad9361_cmos_if ( +module axi_ad9361_cmos_if #( + + parameter DEVICE_TYPE = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // physical interface (receive) - rx_clk_in, - rx_frame_in, - rx_data_in, + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, // physical interface (transmit) - tx_clk_out, - tx_frame_out, - tx_data_out, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, // ensm control - enable, - txnrx, + output enable, + output txnrx, // clock (common to both receive and transmit) - rst, - clk, - l_clk, + input rst, + input clk, + output l_clk, // receive data path interface - adc_valid, - adc_data, - adc_status, - adc_r1_mode, - adc_ddr_edgesel, + output reg adc_valid, + output reg [47:0] adc_data, + output reg adc_status, + input adc_r1_mode, + input adc_ddr_edgesel, // transmit data path interface - dac_valid, - dac_data, - dac_clksel, - dac_r1_mode, + input dac_valid, + input [47:0] dac_data, + input dac_clksel, + input dac_r1_mode, // tdd interface - tdd_enable, - tdd_txnrx, - tdd_mode, + input tdd_enable, + input tdd_txnrx, + input tdd_mode, // delay interface - mmcm_rst, - up_clk, - up_enable, - up_txnrx, - up_adc_dld, - up_adc_dwdata, - up_adc_drdata, - up_dac_dld, - up_dac_dwdata, - up_dac_drdata, - delay_clk, - delay_rst, - delay_locked); + input mmcm_rst, + input up_clk, + input up_enable, + input up_txnrx, + input [12:0] up_adc_dld, + input [64:0] up_adc_dwdata, + output [64:0] up_adc_drdata, + input [15:0] up_dac_dld, + input [79:0] up_dac_dwdata, + output [79:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked); - // this parameter controls the buffer type based on the target device. - - parameter DEVICE_TYPE = 0; - parameter DAC_IODELAY_ENABLE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // physical interface (receive) - - input rx_clk_in; - input rx_frame_in; - input [11:0] rx_data_in; - - // physical interface (transmit) - - output tx_clk_out; - output tx_frame_out; - output [11:0] tx_data_out; - - // ensm control - - output enable; - output txnrx; - - // clock (common to both receive and transmit) - - input rst; - input clk; - output l_clk; - - // receive data path interface - - output adc_valid; - output [47:0] adc_data; - output adc_status; - input adc_r1_mode; - input adc_ddr_edgesel; - - // transmit data path interface - - input dac_valid; - input [47:0] dac_data; - input dac_clksel; - input dac_r1_mode; - - // tdd interface - - input tdd_enable; - input tdd_txnrx; - input tdd_mode; - - // delay interface - - input mmcm_rst; - input up_clk; - input up_enable; - input up_txnrx; - input [12:0] up_adc_dld; - input [64:0] up_adc_dwdata; - output [64:0] up_adc_drdata; - input [15:0] up_dac_dld; - input [79:0] up_dac_dwdata; - output [79:0] up_dac_drdata; - input delay_clk; - input delay_rst; - output delay_locked; // internal registers @@ -184,9 +123,6 @@ module axi_ad9361_cmos_if ( reg adc_valid_int = 'd0; reg [47:0] adc_data_int = 'd0; reg adc_status_int = 'd0; - reg adc_valid = 'd0; - reg [47:0] adc_data = 'd0; - reg adc_status = 'd0; reg [ 1:0] tx_data_cnt = 'd0; reg [47:0] tx_data = 'd0; reg tx_frame_p = 'd0; diff --git a/library/axi_ad9361/axi_ad9361_rx_pnmon.v b/library/axi_ad9361/axi_ad9361_rx_pnmon.v index d69320178..09b7980c2 100644 --- a/library/axi_ad9361/axi_ad9361_rx_pnmon.v +++ b/library/axi_ad9361/axi_ad9361_rx_pnmon.v @@ -40,43 +40,29 @@ `timescale 1ns/100ps -module axi_ad9361_rx_pnmon ( +module axi_ad9361_rx_pnmon #( + + parameter Q_OR_I_N = 0, + parameter PRBS_SEL = 0) ( // adc interface - adc_clk, - adc_valid, - adc_data_i, - adc_data_q, + input adc_clk, + input adc_valid, + input [11:0] adc_data_i, + input [11:0] adc_data_q, // pn out of sync and error - adc_pnseq_sel, - adc_pn_oos, - adc_pn_err); + input [ 3:0] adc_pnseq_sel, + output adc_pn_oos, + output adc_pn_err); - // parameters - - parameter Q_OR_I_N = 0; - parameter PRBS_SEL = 0; localparam PRBS_P09 = 0; localparam PRBS_P11 = 1; localparam PRBS_P15 = 2; localparam PRBS_P20 = 3; - // adc interface - - input adc_clk; - input adc_valid; - input [11:0] adc_data_i; - input [11:0] adc_data_q; - - // pn out of sync and error - - input [ 3:0] adc_pnseq_sel; - output adc_pn_oos; - output adc_pn_err; - // internal registers reg adc_pn0_valid = 'd0; diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v index c61e53532..e55347a6a 100644 --- a/library/axi_ad9361/axi_ad9361_tdd.v +++ b/library/axi_ad9361/axi_ad9361_tdd.v @@ -43,81 +43,43 @@ module axi_ad9361_tdd ( // clock - clk, - rst, + input clk, + input rst, // control signals from the tdd control - tdd_rx_vco_en, - tdd_tx_vco_en, - tdd_rx_rf_en, - tdd_tx_rf_en, + output tdd_rx_vco_en, + output tdd_tx_vco_en, + output tdd_rx_rf_en, + output tdd_tx_rf_en, // status signal - tdd_enabled, - tdd_status, + output tdd_enabled, + input [ 7:0] tdd_status, // sync signal - tdd_sync, - tdd_sync_cntr, + input tdd_sync, + output reg tdd_sync_cntr, // tx/rx data flow control - tdd_tx_valid, - tdd_rx_valid, + output reg tdd_tx_valid, + output reg tdd_rx_valid, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - input clk; - input rst; - - // control signals from the tdd control - - output tdd_rx_vco_en; - output tdd_tx_vco_en; - output tdd_rx_rf_en; - output tdd_tx_rf_en; - - output tdd_enabled; - input [ 7:0] tdd_status; - - input tdd_sync; - output tdd_sync_cntr; - - // data flow control - - output tdd_tx_valid; - output tdd_rx_valid; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - - reg tdd_tx_valid = 1'b0; - reg tdd_rx_valid = 1'b0; - reg tdd_sync_cntr = 1'b0; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); // internal signals diff --git a/library/axi_ad9361/axi_ad9361_tdd_if.v b/library/axi_ad9361/axi_ad9361_tdd_if.v index c7fcb7d8d..ec99f0592 100644 --- a/library/axi_ad9361/axi_ad9361_tdd_if.v +++ b/library/axi_ad9361/axi_ad9361_tdd_if.v @@ -39,59 +39,35 @@ `timescale 1ns/1ps -module axi_ad9361_tdd_if( +module axi_ad9361_tdd_if#( + + parameter LEVEL_OR_PULSE_N = 0) ( // clock - clk, - rst, + input clk, + input rst, // control signals from the tdd control - tdd_rx_vco_en, - tdd_tx_vco_en, - tdd_rx_rf_en, - tdd_tx_rf_en, + input tdd_rx_vco_en, + input tdd_tx_vco_en, + input tdd_rx_rf_en, + input tdd_tx_rf_en, // device interface - ad9361_txnrx, - ad9361_enable, + output ad9361_txnrx, + output ad9361_enable, // interface status - ad9361_tdd_status -); + output [ 7:0] ad9361_tdd_status); - // parameters - - parameter LEVEL_OR_PULSE_N = 0; // the control signals are edge (pulse) or level sensitive localparam PULSE_MODE = 0; localparam LEVEL_MODE = 1; - // clock - - input clk; - input rst; - - // control signals from the tdd control - - input tdd_rx_vco_en; - input tdd_tx_vco_en; - input tdd_rx_rf_en; - input tdd_tx_rf_en; - - // device interface - - output ad9361_txnrx; - output ad9361_enable; - - // interface status - - output [ 7:0] ad9361_tdd_status; - - // internal registers reg tdd_rx_rf_en_d = 1'b0; diff --git a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v index 0ce506d71..5e6ecd9f3 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v @@ -37,133 +37,72 @@ `timescale 1ns/100ps -module axi_ad9361_cmos_if ( +module axi_ad9361_cmos_if #( + + parameter DEVICE_TYPE = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // physical interface (receive) - rx_clk_in, - rx_frame_in, - rx_data_in, + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, // physical interface (transmit) - tx_clk_out, - tx_frame_out, - tx_data_out, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, // ensm control - enable, - txnrx, + output enable, + output txnrx, // clock (common to both receive and transmit) - rst, - clk, - l_clk, + input rst, + input clk, + output l_clk, // receive data path interface - adc_valid, - adc_data, - adc_status, - adc_r1_mode, - adc_ddr_edgesel, + output reg adc_valid, + output reg [47:0] adc_data, + output reg adc_status, + input adc_r1_mode, + input adc_ddr_edgesel, // transmit data path interface - dac_valid, - dac_data, - dac_clksel, - dac_r1_mode, + input dac_valid, + input [47:0] dac_data, + input dac_clksel, + input dac_r1_mode, // tdd interface - tdd_enable, - tdd_txnrx, - tdd_mode, + input tdd_enable, + input tdd_txnrx, + input tdd_mode, // delay interface - mmcm_rst, - up_clk, - up_enable, - up_txnrx, - up_adc_dld, - up_adc_dwdata, - up_adc_drdata, - up_dac_dld, - up_dac_dwdata, - up_dac_drdata, - delay_clk, - delay_rst, - delay_locked); + input mmcm_rst, + input up_clk, + input up_enable, + input up_txnrx, + input [12:0] up_adc_dld, + input [64:0] up_adc_dwdata, + output [64:0] up_adc_drdata, + input [15:0] up_dac_dld, + input [79:0] up_dac_dwdata, + output [79:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked); - // this parameter controls the buffer type based on the target device. - - parameter DEVICE_TYPE = 0; - parameter DAC_IODELAY_ENABLE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // physical interface (receive) - - input rx_clk_in; - input rx_frame_in; - input [11:0] rx_data_in; - - // physical interface (transmit) - - output tx_clk_out; - output tx_frame_out; - output [11:0] tx_data_out; - - // ensm control - - output enable; - output txnrx; - - // clock (common to both receive and transmit) - - input rst; - input clk; - output l_clk; - - // receive data path interface - - output adc_valid; - output [47:0] adc_data; - output adc_status; - input adc_r1_mode; - input adc_ddr_edgesel; - - // transmit data path interface - - input dac_valid; - input [47:0] dac_data; - input dac_clksel; - input dac_r1_mode; - - // tdd interface - - input tdd_enable; - input tdd_txnrx; - input tdd_mode; - - // delay interface - - input mmcm_rst; - input up_clk; - input up_enable; - input up_txnrx; - input [12:0] up_adc_dld; - input [64:0] up_adc_dwdata; - output [64:0] up_adc_drdata; - input [15:0] up_dac_dld; - input [79:0] up_dac_dwdata; - output [79:0] up_dac_drdata; - input delay_clk; - input delay_rst; - output delay_locked; // internal registers @@ -184,9 +123,6 @@ module axi_ad9361_cmos_if ( reg adc_valid_int = 'd0; reg [47:0] adc_data_int = 'd0; reg adc_status_int = 'd0; - reg adc_valid = 'd0; - reg [47:0] adc_data = 'd0; - reg adc_status = 'd0; reg [ 1:0] tx_data_cnt = 'd0; reg [47:0] tx_data = 'd0; reg tx_frame_p = 'd0; diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v index 77a974b5e..122637e53 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v @@ -37,165 +37,88 @@ `timescale 1ns/100ps -module axi_ad9361_lvds_if ( +module axi_ad9361_lvds_if #( + + parameter DEVICE_TYPE = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // physical interface (receive) - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, // physical interface (transmit) - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, // ensm control - enable, - txnrx, + output enable, + output txnrx, // clock (common to both receive and transmit) - rst, - clk, - l_clk, + input rst, + input clk, + output l_clk, // receive data path interface - adc_valid, - adc_data, - adc_status, - adc_r1_mode, - adc_ddr_edgesel, + output reg adc_valid, + output reg [47:0] adc_data, + output reg adc_status, + input adc_r1_mode, + input adc_ddr_edgesel, // transmit data path interface - dac_valid, - dac_data, - dac_clksel, - dac_r1_mode, + input dac_valid, + input [47:0] dac_data, + input dac_clksel, + input dac_r1_mode, // tdd interface - tdd_enable, - tdd_txnrx, - tdd_mode, + input tdd_enable, + input tdd_txnrx, + input tdd_mode, // delay interface - mmcm_rst, - up_clk, - up_enable, - up_txnrx, - up_adc_dld, - up_adc_dwdata, - up_adc_drdata, - up_dac_dld, - up_dac_dwdata, - up_dac_drdata, - delay_clk, - delay_rst, - delay_locked, + input mmcm_rst, + input up_clk, + input up_enable, + input up_txnrx, + input [ 6:0] up_adc_dld, + input [34:0] up_adc_dwdata, + output [34:0] up_adc_drdata, + input [ 9:0] up_dac_dld, + input [49:0] up_dac_dwdata, + output [49:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked, //drp interface - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked); + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked); - // this parameter controls the buffer type based on the target device. - - parameter DEVICE_TYPE = 0; - parameter DAC_IODELAY_ENABLE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // physical interface (receive) - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - - // physical interface (transmit) - - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - // ensm control - - output enable; - output txnrx; - - // clock (common to both receive and transmit) - - input rst; - input clk; - output l_clk; - - // receive data path interface - - output adc_valid; - output [47:0] adc_data; - output adc_status; - input adc_r1_mode; - input adc_ddr_edgesel; - - // transmit data path interface - - input dac_valid; - input [47:0] dac_data; - input dac_clksel; - input dac_r1_mode; - - // tdd interface - - input tdd_enable; - input tdd_txnrx; - input tdd_mode; - - // delay interface - - input mmcm_rst; - input up_clk; - input up_enable; - input up_txnrx; - input [ 6:0] up_adc_dld; - input [34:0] up_adc_dwdata; - output [34:0] up_adc_drdata; - input [ 9:0] up_dac_dld; - input [49:0] up_dac_dwdata; - output [49:0] up_dac_drdata; - input delay_clk; - input delay_rst; - output delay_locked; - - //drp interface - - input up_drp_sel; - input up_drp_wr; - input [11:0] up_drp_addr; - input [31:0] up_drp_wdata; - output [31:0] up_drp_rdata; - output up_drp_ready; - output up_drp_locked; // internal registers @@ -223,9 +146,6 @@ module axi_ad9361_lvds_if ( reg adc_valid_int = 'd0; reg [47:0] adc_data_int = 'd0; reg adc_status_int = 'd0; - reg adc_valid = 'd0; - reg [47:0] adc_data = 'd0; - reg adc_status = 'd0; reg [ 2:0] tx_data_cnt = 'd0; reg [47:0] tx_data = 'd0; reg tx_frame = 'd0; diff --git a/library/axi_ad9371/axi_ad9371.v b/library/axi_ad9371/axi_ad9371.v index 90732411c..ce859c84f 100644 --- a/library/axi_ad9371/axi_ad9371.v +++ b/library/axi_ad9371/axi_ad9371.v @@ -37,194 +37,103 @@ `timescale 1ns/100ps -module axi_ad9371 ( +module axi_ad9371 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter DAC_DATAPATH_DISABLE = 0, + parameter ADC_DATAPATH_DISABLE = 0) ( // receive - adc_clk, - adc_rx_valid, - adc_rx_sof, - adc_rx_data, - adc_rx_ready, - adc_os_clk, - adc_rx_os_valid, - adc_rx_os_sof, - adc_rx_os_data, - adc_rx_os_ready, + input adc_clk, + input adc_rx_valid, + input [ 3:0] adc_rx_sof, + input [ 63:0] adc_rx_data, + output adc_rx_ready, + input adc_os_clk, + input adc_rx_os_valid, + input [ 3:0] adc_rx_os_sof, + input [ 63:0] adc_rx_os_data, + output adc_rx_os_ready, // transmit - dac_clk, - dac_tx_valid, - dac_tx_data, - dac_tx_ready, + input dac_clk, + output dac_tx_valid, + output [127:0] dac_tx_data, + input dac_tx_ready, // master/slave - dac_sync_in, - dac_sync_out, + input dac_sync_in, + output dac_sync_out, // dma interface - adc_enable_i0, - adc_valid_i0, - adc_data_i0, - adc_enable_q0, - adc_valid_q0, - adc_data_q0, - adc_enable_i1, - adc_valid_i1, - adc_data_i1, - adc_enable_q1, - adc_valid_q1, - adc_data_q1, - adc_dovf, - adc_dunf, + output adc_enable_i0, + output adc_valid_i0, + output [ 15:0] adc_data_i0, + output adc_enable_q0, + output adc_valid_q0, + output [ 15:0] adc_data_q0, + output adc_enable_i1, + output adc_valid_i1, + output [ 15:0] adc_data_i1, + output adc_enable_q1, + output adc_valid_q1, + output [ 15:0] adc_data_q1, + input adc_dovf, + input adc_dunf, - adc_os_enable_i0, - adc_os_valid_i0, - adc_os_data_i0, - adc_os_enable_q0, - adc_os_valid_q0, - adc_os_data_q0, - adc_os_dovf, - adc_os_dunf, + output adc_os_enable_i0, + output adc_os_valid_i0, + output [ 31:0] adc_os_data_i0, + output adc_os_enable_q0, + output adc_os_valid_q0, + output [ 31:0] adc_os_data_q0, + input adc_os_dovf, + input adc_os_dunf, - dac_enable_i0, - dac_valid_i0, - dac_data_i0, - dac_enable_q0, - dac_valid_q0, - dac_data_q0, - dac_enable_i1, - dac_valid_i1, - dac_data_i1, - dac_enable_q1, - dac_valid_q1, - dac_data_q1, - dac_dovf, - dac_dunf, + output dac_enable_i0, + output dac_valid_i0, + input [ 31:0] dac_data_i0, + output dac_enable_q0, + output dac_valid_q0, + input [ 31:0] dac_data_q0, + output dac_enable_i1, + output dac_valid_i1, + input [ 31:0] dac_data_i1, + output dac_enable_q1, + output dac_valid_q1, + input [ 31:0] dac_data_q1, + input dac_dovf, + input dac_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready); + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter DAC_DATAPATH_DISABLE = 0; - parameter ADC_DATAPATH_DISABLE = 0; - - // receive - - input adc_clk; - input adc_rx_valid; - input [ 3:0] adc_rx_sof; - input [ 63:0] adc_rx_data; - output adc_rx_ready; - input adc_os_clk; - input adc_rx_os_valid; - input [ 3:0] adc_rx_os_sof; - input [ 63:0] adc_rx_os_data; - output adc_rx_os_ready; - - // transmit - - input dac_clk; - output dac_tx_valid; - output [127:0] dac_tx_data; - input dac_tx_ready; - - // master/slave - - input dac_sync_in; - output dac_sync_out; - - // dma interface - - output adc_enable_i0; - output adc_valid_i0; - output [ 15:0] adc_data_i0; - output adc_enable_q0; - output adc_valid_q0; - output [ 15:0] adc_data_q0; - output adc_enable_i1; - output adc_valid_i1; - output [ 15:0] adc_data_i1; - output adc_enable_q1; - output adc_valid_q1; - output [ 15:0] adc_data_q1; - input adc_dovf; - input adc_dunf; - - output adc_os_enable_i0; - output adc_os_valid_i0; - output [ 31:0] adc_os_data_i0; - output adc_os_enable_q0; - output adc_os_valid_q0; - output [ 31:0] adc_os_data_q0; - input adc_os_dovf; - input adc_os_dunf; - - output dac_enable_i0; - output dac_valid_i0; - input [ 31:0] dac_data_i0; - output dac_enable_q0; - output dac_valid_q0; - input [ 31:0] dac_data_q0; - output dac_enable_i1; - output dac_valid_i1; - input [ 31:0] dac_data_i1; - output dac_enable_q1; - output dac_valid_q1; - input [ 31:0] dac_data_q1; - input dac_dovf; - input dac_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; // internal registers diff --git a/library/axi_ad9371/axi_ad9371_if.v b/library/axi_ad9371/axi_ad9371_if.v index 476c08012..5a8fbda60 100644 --- a/library/axi_ad9371/axi_ad9371_if.v +++ b/library/axi_ad9371/axi_ad9371_if.v @@ -37,49 +37,30 @@ `timescale 1ns/100ps -module axi_ad9371_if ( +module axi_ad9371_if #( + + parameter DEVICE_TYPE = 0) ( // receive - adc_clk, - adc_rx_sof, - adc_rx_data, - adc_os_clk, - adc_rx_os_sof, - adc_rx_os_data, + input adc_clk, + input [ 3:0] adc_rx_sof, + input [ 63:0] adc_rx_data, + input adc_os_clk, + input [ 3:0] adc_rx_os_sof, + input [ 63:0] adc_rx_os_data, - adc_data, - adc_os_valid, - adc_os_data, + output [ 63:0] adc_data, + output adc_os_valid, + output [ 63:0] adc_os_data, // transmit - dac_clk, - dac_tx_data, + input dac_clk, + output [127:0] dac_tx_data, - dac_data); + input [127:0] dac_data); - // parameters - - parameter DEVICE_TYPE = 0; - - // receive - - input adc_clk; - input [ 3:0] adc_rx_sof; - input [ 63:0] adc_rx_data; - input adc_os_clk; - input [ 3:0] adc_rx_os_sof; - input [ 63:0] adc_rx_os_data; - output [ 63:0] adc_data; - output adc_os_valid; - output [ 63:0] adc_os_data; - - // transmit - - input dac_clk; - output [127:0] dac_tx_data; - input [127:0] dac_data; // internal signals diff --git a/library/axi_ad9371/axi_ad9371_rx.v b/library/axi_ad9371/axi_ad9371_rx.v index 6d37e9577..8f73184eb 100644 --- a/library/axi_ad9371/axi_ad9371_rx.v +++ b/library/axi_ad9371/axi_ad9371_rx.v @@ -37,93 +37,53 @@ `timescale 1ns/100ps -module axi_ad9371_rx ( +module axi_ad9371_rx #( + + parameter DATAPATH_DISABLE = 0, + parameter ID = 0) ( // adc interface - adc_rst, - adc_clk, - adc_data, + output adc_rst, + input adc_clk, + input [ 63:0] adc_data, // dma interface - adc_enable_i0, - adc_valid_i0, - adc_data_i0, - adc_enable_q0, - adc_valid_q0, - adc_data_q0, - adc_enable_i1, - adc_valid_i1, - adc_data_i1, - adc_enable_q1, - adc_valid_q1, - adc_data_q1, - adc_dovf, - adc_dunf, + output adc_enable_i0, + output adc_valid_i0, + output [ 15:0] adc_data_i0, + output adc_enable_q0, + output adc_valid_q0, + output [ 15:0] adc_data_q0, + output adc_enable_i1, + output adc_valid_i1, + output [ 15:0] adc_data_i1, + output adc_enable_q1, + output adc_valid_q1, + output [ 15:0] adc_data_q1, + input adc_dovf, + input adc_dunf, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output reg [ 31:0] up_rdata, + output reg up_rack); - // parameters - - parameter DATAPATH_DISABLE = 0; - parameter ID = 0; - - // adc interface - - output adc_rst; - input adc_clk; - input [ 63:0] adc_data; - - // dma interface - - output adc_enable_i0; - output adc_valid_i0; - output [ 15:0] adc_data_i0; - output adc_enable_q0; - output adc_valid_q0; - output [ 15:0] adc_data_q0; - output adc_enable_i1; - output adc_valid_i1; - output [ 15:0] adc_data_i1; - output adc_enable_q1; - output adc_valid_q1; - output [ 15:0] adc_data_q1; - input adc_dovf; - input adc_dunf; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [ 13:0] up_waddr; - input [ 31:0] up_wdata; - output up_wack; - input up_rreq; - input [ 13:0] up_raddr; - output [ 31:0] up_rdata; - output up_rack; // internal registers reg up_status_pn_err = 'd0; reg up_status_pn_oos = 'd0; reg up_status_or = 'd0; - reg up_wack = 'd0; - reg up_rack = 'd0; - reg [ 31:0] up_rdata = 'd0; // internal signals diff --git a/library/axi_ad9371/axi_ad9371_rx_channel.v b/library/axi_ad9371/axi_ad9371_rx_channel.v index 040a6180c..c30328501 100644 --- a/library/axi_ad9371/axi_ad9371_rx_channel.v +++ b/library/axi_ad9371/axi_ad9371_rx_channel.v @@ -37,80 +37,48 @@ `timescale 1ns/100ps -module axi_ad9371_rx_channel ( +module axi_ad9371_rx_channel #( + + parameter Q_OR_I_N = 0, + parameter COMMON_ID = 0, + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0, + parameter DATA_WIDTH = 32) ( // adc interface - adc_clk, - adc_rst, - adc_valid_in, - adc_data_in, - adc_valid_out, - adc_data_out, - adc_data_iq_in, - adc_data_iq_out, - adc_enable, + input adc_clk, + input adc_rst, + input adc_valid_in, + input [(DATA_WIDTH-1):0] adc_data_in, + output adc_valid_out, + output [(DATA_WIDTH-1):0] adc_data_out, + input [(DATA_WIDTH-1):0] adc_data_iq_in, + output [(DATA_WIDTH-1):0] adc_data_iq_out, + output adc_enable, // channel interface - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter Q_OR_I_N = 0; - parameter COMMON_ID = 0; - parameter CHANNEL_ID = 0; - parameter DATAPATH_DISABLE = 0; - parameter DATA_WIDTH = 32; localparam NUM_OF_SAMPLES = DATA_WIDTH/16; - // adc interface - - input adc_clk; - input adc_rst; - input adc_valid_in; - input [(DATA_WIDTH-1):0] adc_data_in; - output adc_valid_out; - output [(DATA_WIDTH-1):0] adc_data_out; - input [(DATA_WIDTH-1):0] adc_data_iq_in; - output [(DATA_WIDTH-1):0] adc_data_iq_out; - output adc_enable; - - // channel interface - - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - // internal signals wire [(NUM_OF_SAMPLES-1):0] adc_dfmt_valid_s; diff --git a/library/axi_ad9371/axi_ad9371_rx_os.v b/library/axi_ad9371/axi_ad9371_rx_os.v index 81304a5c5..93e33752c 100644 --- a/library/axi_ad9371/axi_ad9371_rx_os.v +++ b/library/axi_ad9371/axi_ad9371_rx_os.v @@ -37,83 +37,48 @@ `timescale 1ns/100ps -module axi_ad9371_rx_os ( +module axi_ad9371_rx_os #( + + parameter DATAPATH_DISABLE = 0, + parameter ID = 0) ( // adc interface - adc_os_rst, - adc_os_clk, - adc_os_valid, - adc_os_data, + output adc_os_rst, + input adc_os_clk, + input adc_os_valid, + input [ 63:0] adc_os_data, // dma interface - adc_os_enable_i0, - adc_os_valid_i0, - adc_os_data_i0, - adc_os_enable_q0, - adc_os_valid_q0, - adc_os_data_q0, - adc_os_dovf, - adc_os_dunf, + output adc_os_enable_i0, + output adc_os_valid_i0, + output [ 31:0] adc_os_data_i0, + output adc_os_enable_q0, + output adc_os_valid_q0, + output [ 31:0] adc_os_data_q0, + input adc_os_dovf, + input adc_os_dunf, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output reg [ 31:0] up_rdata, + output reg up_rack); - // parameters - - parameter DATAPATH_DISABLE = 0; - parameter ID = 0; - - // adc interface - - output adc_os_rst; - input adc_os_clk; - input adc_os_valid; - input [ 63:0] adc_os_data; - - // dma interface - - output adc_os_enable_i0; - output adc_os_valid_i0; - output [ 31:0] adc_os_data_i0; - output adc_os_enable_q0; - output adc_os_valid_q0; - output [ 31:0] adc_os_data_q0; - input adc_os_dovf; - input adc_os_dunf; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [ 13:0] up_waddr; - input [ 31:0] up_wdata; - output up_wack; - input up_rreq; - input [ 13:0] up_raddr; - output [ 31:0] up_rdata; - output up_rack; // internal registers reg up_status_pn_err = 'd0; reg up_status_pn_oos = 'd0; reg up_status_or = 'd0; - reg up_wack = 'd0; - reg up_rack = 'd0; - reg [ 31:0] up_rdata = 'd0; // internal signals diff --git a/library/axi_ad9371/axi_ad9371_tx.v b/library/axi_ad9371/axi_ad9371_tx.v index ce64c0e6a..093c15d69 100644 --- a/library/axi_ad9371/axi_ad9371_tx.v +++ b/library/axi_ad9371/axi_ad9371_tx.v @@ -37,101 +37,58 @@ `timescale 1ns/100ps -module axi_ad9371_tx ( +module axi_ad9371_tx #( + + parameter DATAPATH_DISABLE = 0, + parameter ID = 0) ( // dac interface - dac_rst, - dac_clk, - dac_data, + output dac_rst, + input dac_clk, + output [127:0] dac_data, // master/slave - dac_sync_in, - dac_sync_out, + input dac_sync_in, + output dac_sync_out, // dma interface - dac_enable_i0, - dac_valid_i0, - dac_data_i0, - dac_enable_q0, - dac_valid_q0, - dac_data_q0, - dac_enable_i1, - dac_valid_i1, - dac_data_i1, - dac_enable_q1, - dac_valid_q1, - dac_data_q1, - dac_dovf, - dac_dunf, + output dac_enable_i0, + output dac_valid_i0, + input [ 31:0] dac_data_i0, + output dac_enable_q0, + output dac_valid_q0, + input [ 31:0] dac_data_q0, + output dac_enable_i1, + output dac_valid_i1, + input [ 31:0] dac_data_i1, + output dac_enable_q1, + output dac_valid_q1, + input [ 31:0] dac_data_q1, + input dac_dovf, + input dac_dunf, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output reg [ 31:0] up_rdata, + output reg up_rack); - // parameters - parameter DATAPATH_DISABLE = 0; - parameter ID = 0; - - // dac interface - - output dac_rst; - input dac_clk; - output [127:0] dac_data; - // master/slave - - input dac_sync_in; - output dac_sync_out; - - // dma interface - - output dac_enable_i0; - output dac_valid_i0; - input [ 31:0] dac_data_i0; - output dac_enable_q0; - output dac_valid_q0; - input [ 31:0] dac_data_q0; - output dac_enable_i1; - output dac_valid_i1; - input [ 31:0] dac_data_i1; - output dac_enable_q1; - output dac_valid_q1; - input [ 31:0] dac_data_q1; - input dac_dovf; - input dac_dunf; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [ 13:0] up_waddr; - input [ 31:0] up_wdata; - output up_wack; - input up_rreq; - input [ 13:0] up_raddr; - output [ 31:0] up_rdata; - output up_rack; // internal registers reg dac_data_sync = 'd0; - reg up_wack = 'd0; - reg up_rack = 'd0; - reg [ 31:0] up_rdata = 'd0; // internal signals diff --git a/library/axi_ad9371/axi_ad9371_tx_channel.v b/library/axi_ad9371/axi_ad9371_tx_channel.v index 6755ee133..64c7cce8b 100644 --- a/library/axi_ad9371/axi_ad9371_tx_channel.v +++ b/library/axi_ad9371/axi_ad9371_tx_channel.v @@ -37,74 +37,43 @@ `timescale 1ns/100ps -module axi_ad9371_tx_channel ( +module axi_ad9371_tx_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter Q_OR_I_N = 0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_clk, - dac_rst, - dac_data_in, - dac_data_out, - dac_data_iq_in, - dac_data_iq_out, + input dac_clk, + input dac_rst, + input [31:0] dac_data_in, + output [31:0] dac_data_out, + input [31:0] dac_data_iq_in, + output reg [31:0] dac_data_iq_out, // processor interface - dac_enable, - dac_data_sync, - dac_dds_format, + output reg dac_enable, + input dac_data_sync, + input dac_dds_format, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter CHANNEL_ID = 32'h0; - parameter Q_OR_I_N = 0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_clk; - input dac_rst; - input [31:0] dac_data_in; - output [31:0] dac_data_out; - input [31:0] dac_data_iq_in; - output [31:0] dac_data_iq_out; - - // processor interface - - output dac_enable; - input dac_data_sync; - input dac_dds_format; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg dac_enable = 'd0; - reg [31:0] dac_data_iq_out = 'd0; reg [31:0] dac_pat_data = 'd0; reg [15:0] dac_dds_phase_0_0 = 'd0; reg [15:0] dac_dds_phase_0_1 = 'd0; diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v index 83e32fa8c..0a9073ca5 100644 --- a/library/axi_ad9434/axi_ad9434.v +++ b/library/axi_ad9434/axi_ad9434.v @@ -40,99 +40,56 @@ `timescale 1ns/100ps -module axi_ad9434 ( +module axi_ad9434 #( + + parameter ID = 0, + parameter DEVICE_TYPE = SERIES7, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // physical interface - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [11:0] adc_data_in_p, + input [11:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // delay interface - delay_clk, + input delay_clk, // dma interface - adc_clk, - adc_enable, - adc_valid, - adc_data, - adc_dovf, + output adc_clk, + output adc_enable, + output adc_valid, + output [63:0] adc_data, + input adc_dovf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); - - // parameters localparam SERIES7 = 0; localparam SERIES6 = 1; - parameter ID = 0; - parameter DEVICE_TYPE = SERIES7; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // physical interface - input adc_clk_in_p; - input adc_clk_in_n; - input [11:0] adc_data_in_p; - input [11:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // delay interface - input delay_clk; - - // dma interface - output adc_clk; - output adc_valid; - output adc_enable; - output [63:0] adc_data; - input adc_dovf; - - // axi interface - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; - // internal clocks & resets wire adc_rst; @@ -163,7 +120,6 @@ module axi_ad9434 ( wire delay_rst; wire delay_locked_s; - wire up_drp_sel_s; wire up_drp_wr_s; wire [11:0] up_drp_addr_s; diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v index 84d6c2203..967c9df73 100644 --- a/library/axi_ad9434/axi_ad9434_core.v +++ b/library/axi_ad9434/axi_ad9434_core.v @@ -40,108 +40,62 @@ `timescale 1ns/100ps -module axi_ad9434_core ( +module axi_ad9434_core #( + + parameter ID = 0) ( // device interface - adc_clk, - adc_data, - adc_or, + input adc_clk, + input [47:0] adc_data, + input adc_or, // dma interface - dma_dvalid, - dma_data, - dma_dovf, + output dma_dvalid, + output [63:0] dma_data, + input dma_dovf, // drp interface - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked, + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, // delay interface - up_dld, - up_dwdata, - up_drdata, - delay_clk, - delay_rst, - delay_locked, + output [12:0] up_dld, + output [64:0] up_dwdata, + input [64:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack, + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack, // status and control signals - mmcm_rst, - adc_rst, - adc_status); + output mmcm_rst, + output adc_rst, + input adc_status); - // parameters - parameter ID = 0; - - // device interface - input adc_clk; - input [47:0] adc_data; - input adc_or; - - // dma interface - output dma_dvalid; - output [63:0] dma_data; - input dma_dovf; - - // drp interface - output up_drp_sel; - output up_drp_wr; - output [11:0] up_drp_addr; - output [31:0] up_drp_wdata; - input [31:0] up_drp_rdata; - input up_drp_ready; - input up_drp_locked; - - // delay interface - output [12:0] up_dld; - output [64:0] up_dwdata; - input [64:0] up_drdata; - input delay_clk; - output delay_rst; - input delay_locked; - - // processor interface - input up_clk; - input up_rstn; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - - output mmcm_rst; - output adc_rst; - input adc_status; // internal registers - reg up_wack; - reg [31:0] up_rdata; - reg up_rack; // internal signals wire up_status_pn_err_s; diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v index bb4da7915..df725d0fd 100644 --- a/library/axi_ad9434/axi_ad9434_if.v +++ b/library/axi_ad9434/axi_ad9434_if.v @@ -40,98 +40,55 @@ `timescale 1ns/100ps -module axi_ad9434_if ( +module axi_ad9434_if #( + + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // device interface - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [11:0] adc_data_in_p, + input [11:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // interface outputs - adc_data, - adc_or, + output [47:0] adc_data, + output adc_or, // internl reset and clocks - adc_clk, - adc_rst, - adc_status, + output adc_clk, + input adc_rst, + output reg adc_status, // delay interface (for IDELAY macros) - up_clk, - up_adc_dld, - up_adc_dwdata, - up_adc_drdata, - delay_clk, - delay_rst, - delay_locked, + input up_clk, + input [12:0] up_adc_dld, + input [64:0] up_adc_dwdata, + output [64:0] up_adc_drdata, + input delay_clk, + input delay_rst, + output delay_locked, // mmcm reset - mmcm_rst, + input mmcm_rst, // drp interface for MMCM_OR_BUFR_N - up_rstn, - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked); + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked); - // parameters - parameter DEVICE_TYPE = 0; // 0 - 7Series / 1 - 6Series - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - // buffer type based on the target device. localparam SDR = 0; - // adc interface (clk, data, over-range) - input adc_clk_in_p; - input adc_clk_in_n; - input [11:0] adc_data_in_p; - input [11:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // interface outputs - output [47:0] adc_data; - output adc_or; - - // internal reset and clocks - - output adc_clk; - input adc_rst; - output adc_status; - - // delay interface - - input up_clk; - input [12:0] up_adc_dld; - input [64:0] up_adc_dwdata; - output [64:0] up_adc_drdata; - input delay_clk; - input delay_rst; - output delay_locked; - - // mmcm reset - input mmcm_rst; - - // drp interface - input up_rstn; - input up_drp_sel; - input up_drp_wr; - input [11:0] up_drp_addr; - input [31:0] up_drp_wdata; - output [31:0] up_drp_rdata; - output up_drp_ready; - output up_drp_locked; - // internal registers - reg adc_status = 'd0; reg adc_status_m1 = 'd0; // internal signals diff --git a/library/axi_ad9434/axi_ad9434_pnmon.v b/library/axi_ad9434/axi_ad9434_pnmon.v index a29d7c4ed..19f573218 100644 --- a/library/axi_ad9434/axi_ad9434_pnmon.v +++ b/library/axi_ad9434/axi_ad9434_pnmon.v @@ -43,22 +43,13 @@ module axi_ad9434_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [47:0] adc_data, // pn interface - adc_pnseq_sel, - adc_pn_err, - adc_pn_oos); - - // adc interface - input adc_clk; - input [47:0] adc_data; - - // pn out sync and error - input [ 3:0] adc_pnseq_sel; - output adc_pn_err; - output adc_pn_oos; + input [ 3:0] adc_pnseq_sel, + output adc_pn_err, + output adc_pn_oos); // internal registers reg [47:0] adc_pn_data_pn = 'd0; diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v index 3d549a15c..d1a64272f 100644 --- a/library/axi_ad9467/axi_ad9467.v +++ b/library/axi_ad9467/axi_ad9467.v @@ -39,105 +39,57 @@ `timescale 1ns/100ps -module axi_ad9467( +module axi_ad9467#( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // physical interface - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [ 7:0] adc_data_in_p, + input [ 7:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // delay_clock - delay_clk, + input delay_clk, // dma interface - adc_clk, - adc_valid, - adc_enable, - adc_data, - adc_dovf, - adc_dunf, + output adc_clk, + output adc_valid, + output adc_enable, + output [15:0] adc_data, + input adc_dovf, + input adc_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready); - - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // physical interface - - input adc_clk_in_p; - input adc_clk_in_n; - input [ 7:0] adc_data_in_p; - input [ 7:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // delay clk - - input delay_clk; - - // dma interface - - output adc_clk; - output adc_valid; - output adc_enable; - output [15:0] adc_data; - input adc_dovf; - input adc_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready); // internal registers diff --git a/library/axi_ad9467/axi_ad9467_channel.v b/library/axi_ad9467/axi_ad9467_channel.v index 4ecb883f0..ded6649a5 100644 --- a/library/axi_ad9467/axi_ad9467_channel.v +++ b/library/axi_ad9467/axi_ad9467_channel.v @@ -37,67 +37,38 @@ `timescale 1ns/100ps -module axi_ad9467_channel( +module axi_ad9467_channel#( + + parameter CHANNEL_ID = 0) ( // adc interface - adc_clk, - adc_rst, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input [15:0] adc_data, + input adc_or, // channel interface - adc_dfmt_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [15:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter CHANNEL_ID = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input [15:0] adc_data; - input adc_or; - - // channel interface - - output [15:0] adc_dfmt_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad9467/axi_ad9467_if.v b/library/axi_ad9467/axi_ad9467_if.v index 0886dc693..429867511 100644 --- a/library/axi_ad9467/axi_ad9467_if.v +++ b/library/axi_ad9467/axi_ad9467_if.v @@ -41,70 +41,40 @@ `timescale 1ns/100ps -module axi_ad9467_if ( +module axi_ad9467_if #( + + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // adc interface (clk, data, over-range) - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [ 7:0] adc_data_in_p, + input [ 7:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // interface outputs - adc_clk, - adc_data, - adc_or, + output adc_clk, + output reg [15:0] adc_data, + output reg adc_or, // processor interface - adc_ddr_edgesel, + input adc_ddr_edgesel, // delay control signals - up_clk, - up_dld, - up_dwdata, - up_drdata, - delay_clk, - delay_rst, - delay_locked); + input up_clk, + input [ 8:0] up_dld, + input [44:0] up_dwdata, + output [44:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked); - // buffer type based on the target device. - - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // adc interface (clk, data, over-range) - - input adc_clk_in_p; - input adc_clk_in_n; - input [ 7:0] adc_data_in_p; - input [ 7:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // interface outputs - - output adc_clk; - output [15:0] adc_data; - output adc_or; - - // processor interface - - input adc_ddr_edgesel; - - // delay control signals - - input up_clk; - input [ 8:0] up_dld; - input [44:0] up_dwdata; - output [44:0] up_drdata; - input delay_clk; - input delay_rst; - output delay_locked; // internal registers @@ -113,10 +83,8 @@ module axi_ad9467_if ( reg [ 7:0] adc_data_p_d = 'd0; reg [ 7:0] adc_dmux_a = 'd0; reg [ 7:0] adc_dmux_b = 'd0; - reg [15:0] adc_data = 'd0; reg adc_or_p = 'd0; reg adc_or_n = 'd0; - reg adc_or = 'd0; // internal signals diff --git a/library/axi_ad9467/axi_ad9467_pnmon.v b/library/axi_ad9467/axi_ad9467_pnmon.v index 9cb9c99c6..6ec292672 100644 --- a/library/axi_ad9467/axi_ad9467_pnmon.v +++ b/library/axi_ad9467/axi_ad9467_pnmon.v @@ -44,25 +44,14 @@ module axi_ad9467_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [15:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [15:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - input [ 3:0] adc_pnseq_sel; + output adc_pn_oos, + output adc_pn_err, + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v index 59bdaa00b..e0a7fd1ae 100644 --- a/library/axi_ad9625/axi_ad9625.v +++ b/library/axi_ad9625/axi_ad9625.v @@ -37,103 +37,57 @@ `timescale 1ns/100ps -module axi_ad9625 ( +module axi_ad9625 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_valid, - rx_data, - rx_ready, + input rx_clk, + input [ 3:0] rx_sof, + input rx_valid, + input [255:0] rx_data, + output rx_ready, // dma interface - adc_clk, - adc_rst, - adc_valid, - adc_enable, - adc_data, - adc_dovf, - adc_dunf, - adc_sref, - adc_raddr_in, - adc_raddr_out, + output adc_clk, + output adc_rst, + output adc_valid, + output adc_enable, + output [255:0] adc_data, + input adc_dovf, + input adc_dunf, + output [ 15:0] adc_sref, + input [ 3:0] adc_raddr_in, + output [ 3:0] adc_raddr_out, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [ 3:0] rx_sof; - input rx_valid; - input [255:0] rx_data; - output rx_ready; - - // dma interface - - output adc_clk; - output adc_rst; - output adc_valid; - output adc_enable; - output [255:0] adc_data; - input adc_dovf; - input adc_dunf; - output [ 15:0] adc_sref; - input [ 3:0] adc_raddr_in; - output [ 3:0] adc_raddr_out; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [ 31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [ 31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal registers diff --git a/library/axi_ad9625/axi_ad9625_channel.v b/library/axi_ad9625/axi_ad9625_channel.v index e2f8460fc..cc71defdd 100644 --- a/library/axi_ad9625/axi_ad9625_channel.v +++ b/library/axi_ad9625/axi_ad9625_channel.v @@ -44,59 +44,31 @@ module axi_ad9625_channel ( // adc interface - adc_clk, - adc_rst, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input [191:0] adc_data, + input adc_or, // channel interface - adc_dfmt_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [255:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // adc interface - - input adc_clk; - input adc_rst; - input [191:0] adc_data; - input adc_or; - - // channel interface - - output [255:0] adc_dfmt_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); // internal signals diff --git a/library/axi_ad9625/axi_ad9625_if.v b/library/axi_ad9625/axi_ad9625_if.v index 2e0f78f18..204436174 100644 --- a/library/axi_ad9625/axi_ad9625_if.v +++ b/library/axi_ad9625/axi_ad9625_if.v @@ -37,59 +37,36 @@ `timescale 1ns/100ps -module axi_ad9625_if ( +module axi_ad9625_if #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0) ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_data, + input rx_clk, + input [ 3:0] rx_sof, + input [255:0] rx_data, // adc data output - adc_clk, - adc_rst, - adc_data, - adc_or, - adc_status, - adc_sref, - adc_raddr_in, - adc_raddr_out); + output adc_clk, + input adc_rst, + output reg [191:0] adc_data, + output adc_or, + output reg adc_status, + output reg [ 15:0] adc_sref, + input [ 3:0] adc_raddr_in, + output reg [ 3:0] adc_raddr_out); - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - - // jesd interface - // rx_clk is ref_clk/4 - - input rx_clk; - input [ 3:0] rx_sof; - input [255:0] rx_data; - - // adc data output - - output adc_clk; - input adc_rst; - output [191:0] adc_data; - output adc_or; - output adc_status; - output [ 15:0] adc_sref; - input [ 3:0] adc_raddr_in; - output [ 3:0] adc_raddr_out; // internal registers - reg [191:0] adc_data = 'd0; - reg [ 15:0] adc_sref = 'd0; reg [191:0] adc_data_cur = 'd0; reg [191:0] adc_data_prv = 'd0; reg [ 3:0] adc_waddr = 'd0; - reg [ 3:0] adc_raddr_out = 'd0; reg [191:0] adc_wdata = 'd0; - reg adc_status = 'd0; // internal signals diff --git a/library/axi_ad9625/axi_ad9625_pnmon.v b/library/axi_ad9625/axi_ad9625_pnmon.v index 15945966d..7049d057f 100644 --- a/library/axi_ad9625/axi_ad9625_pnmon.v +++ b/library/axi_ad9625/axi_ad9625_pnmon.v @@ -44,31 +44,17 @@ module axi_ad9625_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [191:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, + output adc_pn_oos, + output adc_pn_err, // processor interface PN9 (0x0), PN23 (0x1) - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [191:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - - // processor interface PN9 (0x0), PN23 (0x1) - - input [ 3:0] adc_pnseq_sel; + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9643/axi_ad9643.v b/library/axi_ad9643/axi_ad9643.v index 4fbb67a54..e17fdd4ef 100644 --- a/library/axi_ad9643/axi_ad9643.v +++ b/library/axi_ad9643/axi_ad9643.v @@ -37,118 +37,64 @@ `timescale 1ns/100ps -module axi_ad9643 ( +module axi_ad9643 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter ADC_DATAPATH_DISABLE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // adc interface (clk, data, over-range) - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [13:0] adc_data_in_p, + input [13:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // delay interface - delay_clk, + input delay_clk, // dma interface - adc_clk, - adc_valid_0, - adc_enable_0, - adc_data_0, - adc_valid_1, - adc_enable_1, - adc_data_1, - adc_dovf, - adc_dunf, - up_adc_gpio_in, - up_adc_gpio_out, - adc_rst, + output adc_clk, + output adc_valid_0, + output adc_enable_0, + output [15:0] adc_data_0, + output adc_valid_1, + output adc_enable_1, + output [15:0] adc_data_1, + input adc_dovf, + input adc_dunf, + input [31:0] up_adc_gpio_in, + output [31:0] up_adc_gpio_out, + output adc_rst, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter ADC_DATAPATH_DISABLE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // adc interface (clk, data, over-range) - - input adc_clk_in_p; - input adc_clk_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // delay interface - - input delay_clk; - - // dma interface - - output adc_clk; - output adc_valid_0; - output adc_enable_0; - output [15:0] adc_data_0; - output adc_valid_1; - output adc_enable_1; - output [15:0] adc_data_1; - input adc_dovf; - input adc_dunf; - input [31:0] up_adc_gpio_in; - output [31:0] up_adc_gpio_out; - output adc_rst; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal registers diff --git a/library/axi_ad9643/axi_ad9643_channel.v b/library/axi_ad9643/axi_ad9643_channel.v index 78072d2ad..17d84090f 100644 --- a/library/axi_ad9643/axi_ad9643_channel.v +++ b/library/axi_ad9643/axi_ad9643_channel.v @@ -38,73 +38,42 @@ `timescale 1ns/100ps -module axi_ad9643_channel ( +module axi_ad9643_channel #( + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0) ( // adc interface - adc_clk, - adc_rst, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input [13:0] adc_data, + input adc_or, // channel interface - adc_dcfilter_data_out, - adc_dcfilter_data_in, - adc_iqcor_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [15:0] adc_dcfilter_data_out, + input [15:0] adc_dcfilter_data_in, + output [15:0] adc_iqcor_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter Q_OR_I_N = 0; - parameter CHANNEL_ID = 0; - parameter DATAPATH_DISABLE = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input [13:0] adc_data; - input adc_or; - - // channel interface - - output [15:0] adc_dcfilter_data_out; - input [15:0] adc_dcfilter_data_in; - output [15:0] adc_iqcor_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad9643/axi_ad9643_if.v b/library/axi_ad9643/axi_ad9643_if.v index b46678775..5c08be7fd 100644 --- a/library/axi_ad9643/axi_ad9643_if.v +++ b/library/axi_ad9643/axi_ad9643_if.v @@ -42,82 +42,47 @@ `timescale 1ns/100ps -module axi_ad9643_if ( +module axi_ad9643_if #( + + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // adc interface (clk, data, over-range) - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [13:0] adc_data_in_p, + input [13:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // interface outputs - adc_clk, - adc_data_a, - adc_data_b, - adc_or_a, - adc_or_b, - adc_status, + output adc_clk, + output reg [13:0] adc_data_a, + output reg [13:0] adc_data_b, + output reg adc_or_a, + output reg adc_or_b, + output reg adc_status, // processor control signals - adc_ddr_edgesel, - adc_pin_mode, + input adc_ddr_edgesel, + input adc_pin_mode, // delay control signals - up_clk, - up_dld, - up_dwdata, - up_drdata, - delay_clk, - delay_rst, - delay_locked); + input up_clk, + input [14:0] up_dld, + input [74:0] up_dwdata, + output [74:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked); - // This parameter controls the buffer type based on the target device. - - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // adc interface (clk, data, over-range) - - input adc_clk_in_p; - input adc_clk_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // interface outputs - - output adc_clk; - output [13:0] adc_data_a; - output [13:0] adc_data_b; - output adc_or_a; - output adc_or_b; - output adc_status; - - // processor control signals - - input adc_ddr_edgesel; - input adc_pin_mode; - - // delay control signals - - input up_clk; - input [14:0] up_dld; - input [74:0] up_dwdata; - output [74:0] up_drdata; - input delay_clk; - input delay_rst; - output delay_locked; // internal registers - reg adc_status = 'd0; reg [13:0] adc_data_p = 'd0; reg [13:0] adc_data_n = 'd0; reg [13:0] adc_data_p_d = 'd0; @@ -128,10 +93,6 @@ module axi_ad9643_if ( reg [13:0] adc_data_mux_b = 'd0; reg adc_or_mux_a = 'd0; reg adc_or_mux_b = 'd0; - reg [13:0] adc_data_a = 'd0; - reg [13:0] adc_data_b = 'd0; - reg adc_or_a = 'd0; - reg adc_or_b = 'd0; // internal signals diff --git a/library/axi_ad9643/axi_ad9643_pnmon.v b/library/axi_ad9643/axi_ad9643_pnmon.v index 17849a87d..5256da423 100644 --- a/library/axi_ad9643/axi_ad9643_pnmon.v +++ b/library/axi_ad9643/axi_ad9643_pnmon.v @@ -44,25 +44,14 @@ module axi_ad9643_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [13:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [13:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - input [ 3:0] adc_pnseq_sel; + output adc_pn_oos, + output adc_pn_err, + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9652/axi_ad9652.v b/library/axi_ad9652/axi_ad9652.v index 4b51be6ea..d46b89ce4 100644 --- a/library/axi_ad9652/axi_ad9652.v +++ b/library/axi_ad9652/axi_ad9652.v @@ -37,118 +37,64 @@ `timescale 1ns/100ps -module axi_ad9652 ( +module axi_ad9652 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter ADC_DATAPATH_DISABLE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // adc interface (clk, data, over-range) - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [15:0] adc_data_in_p, + input [15:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // delay interface - delay_clk, + input delay_clk, // dma interface - adc_clk, - adc_rst, - adc_valid_0, - adc_enable_0, - adc_data_0, - adc_valid_1, - adc_enable_1, - adc_data_1, - adc_dovf, - adc_dunf, - up_adc_gpio_in, - up_adc_gpio_out, + output adc_clk, + output adc_rst, + output adc_valid_0, + output adc_enable_0, + output [15:0] adc_data_0, + output adc_valid_1, + output adc_enable_1, + output [15:0] adc_data_1, + input adc_dovf, + input adc_dunf, + input [31:0] up_adc_gpio_in, + output [31:0] up_adc_gpio_out, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter ADC_DATAPATH_DISABLE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // adc interface (clk, data, over-range) - - input adc_clk_in_p; - input adc_clk_in_n; - input [15:0] adc_data_in_p; - input [15:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // delay interface - - input delay_clk; - - // dma interface - - output adc_clk; - output adc_rst; - output adc_valid_0; - output adc_enable_0; - output [15:0] adc_data_0; - output adc_valid_1; - output adc_enable_1; - output [15:0] adc_data_1; - input adc_dovf; - input adc_dunf; - input [31:0] up_adc_gpio_in; - output [31:0] up_adc_gpio_out; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal registers diff --git a/library/axi_ad9652/axi_ad9652_channel.v b/library/axi_ad9652/axi_ad9652_channel.v index 63747b9de..596146b9c 100644 --- a/library/axi_ad9652/axi_ad9652_channel.v +++ b/library/axi_ad9652/axi_ad9652_channel.v @@ -40,73 +40,42 @@ `timescale 1ns/100ps -module axi_ad9652_channel ( +module axi_ad9652_channel #( + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0) ( // adc interface - adc_clk, - adc_rst, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input [15:0] adc_data, + input adc_or, // channel interface - adc_dcfilter_data_out, - adc_dcfilter_data_in, - adc_iqcor_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [15:0] adc_dcfilter_data_out, + input [15:0] adc_dcfilter_data_in, + output [15:0] adc_iqcor_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter Q_OR_I_N = 0; - parameter CHANNEL_ID = 0; - parameter DATAPATH_DISABLE = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input [15:0] adc_data; - input adc_or; - - // channel interface - - output [15:0] adc_dcfilter_data_out; - input [15:0] adc_dcfilter_data_in; - output [15:0] adc_iqcor_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad9652/axi_ad9652_if.v b/library/axi_ad9652/axi_ad9652_if.v index ad422c0d7..99c8061bc 100644 --- a/library/axi_ad9652/axi_ad9652_if.v +++ b/library/axi_ad9652/axi_ad9652_if.v @@ -42,90 +42,52 @@ `timescale 1ns/100ps -module axi_ad9652_if ( +module axi_ad9652_if #( + + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // adc interface (clk, data, over-range) - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_or_in_p, - adc_or_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [15:0] adc_data_in_p, + input [15:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, // interface outputs - adc_clk, - adc_data_a, - adc_data_b, - adc_or_a, - adc_or_b, - adc_status, + output adc_clk, + output reg [15:0] adc_data_a, + output reg [15:0] adc_data_b, + output reg adc_or_a, + output reg adc_or_b, + output reg adc_status, // processor control signals - adc_ddr_edgesel, + input adc_ddr_edgesel, // delay control signals - up_clk, - up_dld, - up_dwdata, - up_drdata, - delay_clk, - delay_rst, - delay_locked); + input up_clk, + input [16:0] up_dld, + input [84:0] up_dwdata, + output [84:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked); - // This parameter controls the buffer type based on the target device. - - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // adc interface (clk, data, over-range) - - input adc_clk_in_p; - input adc_clk_in_n; - input [15:0] adc_data_in_p; - input [15:0] adc_data_in_n; - input adc_or_in_p; - input adc_or_in_n; - - // interface outputs - - output adc_clk; - output [15:0] adc_data_a; - output [15:0] adc_data_b; - output adc_or_a; - output adc_or_b; - output adc_status; - - // processor control signals - - input adc_ddr_edgesel; - - // delay control signals - - input up_clk; - input [16:0] up_dld; - input [84:0] up_dwdata; - output [84:0] up_drdata; - input delay_clk; - input delay_rst; - output delay_locked; // internal registers - reg adc_status = 'd0; reg [15:0] adc_data_p = 'd0; reg [15:0] adc_data_n = 'd0; reg [15:0] adc_data_p_d = 'd0; reg adc_or_p = 'd0; reg adc_or_n = 'd0; reg adc_or_p_d = 'd0; - reg [15:0] adc_data_a = 'd0; - reg [15:0] adc_data_b = 'd0; - reg adc_or_a = 'd0; - reg adc_or_b = 'd0; // internal signals @@ -164,7 +126,6 @@ module axi_ad9652_if ( end end - // data interface generate diff --git a/library/axi_ad9652/axi_ad9652_pnmon.v b/library/axi_ad9652/axi_ad9652_pnmon.v index f514c4954..509602ae2 100644 --- a/library/axi_ad9652/axi_ad9652_pnmon.v +++ b/library/axi_ad9652/axi_ad9652_pnmon.v @@ -44,25 +44,14 @@ module axi_ad9652_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [15:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [15:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - input [ 3:0] adc_pnseq_sel; + output adc_pn_oos, + output adc_pn_err, + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index 442476e08..550165072 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -37,103 +37,58 @@ `timescale 1ns/100ps -module axi_ad9671 ( +module axi_ad9671 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter QUAD_OR_DUAL_N = 1) ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_valid, - rx_data, - rx_ready, + input rx_clk, + input [ 3:0] rx_sof, + input rx_valid, + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data, + output rx_ready, // dma interface - adc_clk, - adc_valid, - adc_enable, - adc_data, - adc_dovf, - adc_dunf, - adc_sync_in, - adc_sync_out, - adc_raddr_in, - adc_raddr_out, + output adc_clk, + output [ 7:0] adc_valid, + output [ 7:0] adc_enable, + output [127:0] adc_data, + input adc_dovf, + input adc_dunf, + input adc_sync_in, + output adc_sync_out, + input [ 3:0] adc_raddr_in, + output [ 3:0] adc_raddr_out, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready); + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [ 31:0] s_axi_rdata, + input s_axi_rready); - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter QUAD_OR_DUAL_N = 1; - - // jesd interface - // rx_clk is the jesd clock (ref_clk/2) - - input rx_clk; - input [ 3:0] rx_sof; - input rx_valid; - input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; - output rx_ready; - - // dma interface - - output adc_clk; - output [ 7:0] adc_valid; - output [ 7:0] adc_enable; - output [127:0] adc_data; - input adc_dovf; - input adc_dunf; - input adc_sync_in; - output adc_sync_out; - input [ 3:0] adc_raddr_in; - output [ 3:0] adc_raddr_out; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [ 31:0] s_axi_rdata; - input s_axi_rready; // internal registers diff --git a/library/axi_ad9671/axi_ad9671_channel.v b/library/axi_ad9671/axi_ad9671_channel.v index 68bd4778f..413218754 100644 --- a/library/axi_ad9671/axi_ad9671_channel.v +++ b/library/axi_ad9671/axi_ad9671_channel.v @@ -40,71 +40,40 @@ `timescale 1ns/100ps -module axi_ad9671_channel ( +module axi_ad9671_channel #( + + parameter CHANNEL_ID = 0) ( // adc interface - adc_clk, - adc_rst, - adc_valid, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input adc_valid, + input [15:0] adc_data, + input adc_or, // channel interface - adc_dfmt_valid, - adc_dfmt_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output adc_dfmt_valid, + output [15:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter CHANNEL_ID = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input adc_valid; - input [15:0] adc_data; - input adc_or; - - // channel interface - - output adc_dfmt_valid; - output [15:0] adc_dfmt_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v index 9b8eaabb6..24ebc2a38 100644 --- a/library/axi_ad9671/axi_ad9671_if.v +++ b/library/axi_ad9671/axi_ad9671_if.v @@ -37,87 +37,49 @@ `timescale 1ns/100ps -module axi_ad9671_if ( +module axi_ad9671_if #( + + parameter QUAD_OR_DUAL_N = 1, + parameter DEVICE_TYPE = 0, + parameter ID = 0) ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_data, + input rx_clk, + input [ 3:0] rx_sof, + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data, // adc data output - adc_clk, - adc_rst, - adc_valid, - adc_data_a, - adc_or_a, - adc_data_b, - adc_or_b, - adc_data_c, - adc_or_c, - adc_data_d, - adc_or_d, - adc_data_e, - adc_or_e, - adc_data_f, - adc_or_f, - adc_data_g, - adc_or_g, - adc_data_h, - adc_or_h, - adc_start_code, - adc_sync_in, - adc_sync_out, - adc_sync, - adc_sync_status, - adc_status, - adc_raddr_in, - adc_raddr_out); + output adc_clk, + input adc_rst, + output adc_valid, + output reg [ 15:0] adc_data_a, + output adc_or_a, + output reg [ 15:0] adc_data_b, + output adc_or_b, + output reg [ 15:0] adc_data_c, + output adc_or_c, + output reg [ 15:0] adc_data_d, + output adc_or_d, + output reg [ 15:0] adc_data_e, + output adc_or_e, + output reg [ 15:0] adc_data_f, + output adc_or_f, + output reg [ 15:0] adc_data_g, + output adc_or_g, + output reg [ 15:0] adc_data_h, + output adc_or_h, + input [ 31:0] adc_start_code, + input adc_sync_in, + output adc_sync_out, + input adc_sync, + output reg adc_sync_status, + output reg adc_status, + input [ 3:0] adc_raddr_in, + output reg [ 3:0] adc_raddr_out); - // parameters - - parameter QUAD_OR_DUAL_N = 1; - parameter DEVICE_TYPE = 0; - parameter ID = 0; - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [ 3:0] rx_sof; - input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; - - // adc data output - - output adc_clk; - input adc_rst; - output adc_valid; - output [ 15:0] adc_data_a; - output adc_or_a; - output [ 15:0] adc_data_b; - output adc_or_b; - output [ 15:0] adc_data_c; - output adc_or_c; - output [ 15:0] adc_data_d; - output adc_or_d; - output [ 15:0] adc_data_e; - output adc_or_e; - output [ 15:0] adc_data_f; - output adc_or_f; - output [ 15:0] adc_data_g; - output adc_or_g; - output [ 15:0] adc_data_h; - output adc_or_h; - input [ 31:0] adc_start_code; - input adc_sync_in; - output adc_sync_out; - input adc_sync; - output adc_sync_status; - output adc_status; - input [ 3:0] adc_raddr_in; - output [ 3:0] adc_raddr_out; // internal wires @@ -140,19 +102,8 @@ module axi_ad9671_if ( reg int_valid = 'd0; reg [127:0] int_data = 'd0; - reg adc_status = 'd0; - reg adc_sync_status = 'd0; reg rx_sof_d = 'd0; reg [ 3:0] adc_waddr = 'd0; - reg [ 3:0] adc_raddr_out = 'd0; - reg [ 15:0] adc_data_a = 'd0; - reg [ 15:0] adc_data_b = 'd0; - reg [ 15:0] adc_data_c = 'd0; - reg [ 15:0] adc_data_d = 'd0; - reg [ 15:0] adc_data_e = 'd0; - reg [ 15:0] adc_data_f = 'd0; - reg [ 15:0] adc_data_g = 'd0; - reg [ 15:0] adc_data_h = 'd0; // adc clock & valid diff --git a/library/axi_ad9671/axi_ad9671_pnmon.v b/library/axi_ad9671/axi_ad9671_pnmon.v index ee2d0b1b5..8c0f0efad 100644 --- a/library/axi_ad9671/axi_ad9671_pnmon.v +++ b/library/axi_ad9671/axi_ad9671_pnmon.v @@ -44,27 +44,15 @@ module axi_ad9671_pnmon ( // adc interface - adc_clk, - adc_valid, - adc_data, + input adc_clk, + input adc_valid, + input [15:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input adc_valid; - input [15:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - input [ 3:0] adc_pnseq_sel; + output adc_pn_oos, + output adc_pn_err, + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v index 0f404143c..4a76e31c9 100644 --- a/library/axi_ad9680/axi_ad9680.v +++ b/library/axi_ad9680/axi_ad9680.v @@ -37,101 +37,57 @@ `timescale 1ns/100ps -module axi_ad9680 ( +module axi_ad9680 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_valid, - rx_data, - rx_ready, + input rx_clk, + input [ 3:0] rx_sof, + input rx_valid, + input [127:0] rx_data, + output rx_ready, // dma interface - adc_clk, - adc_enable_0, - adc_valid_0, - adc_data_0, - adc_enable_1, - adc_valid_1, - adc_data_1, - adc_dovf, - adc_dunf, + output adc_clk, + output adc_enable_0, + output adc_valid_0, + output [63:0] adc_data_0, + output adc_enable_1, + output adc_valid_1, + output [63:0] adc_data_1, + input adc_dovf, + input adc_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready); + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready); - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [ 3:0] rx_sof; - input rx_valid; - input [127:0] rx_data; - output rx_ready; - - // dma interface - - output adc_clk; - output adc_enable_0; - output adc_valid_0; - output [63:0] adc_data_0; - output adc_enable_1; - output adc_valid_1; - output [63:0] adc_data_1; - input adc_dovf; - input adc_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; // internal registers diff --git a/library/axi_ad9680/axi_ad9680_channel.v b/library/axi_ad9680/axi_ad9680_channel.v index 56b2dbe18..977b47e9a 100644 --- a/library/axi_ad9680/axi_ad9680_channel.v +++ b/library/axi_ad9680/axi_ad9680_channel.v @@ -40,67 +40,38 @@ `timescale 1ns/100ps -module axi_ad9680_channel ( +module axi_ad9680_channel #( + + parameter CHANNEL_ID = 0) ( // adc interface - adc_clk, - adc_rst, - adc_data, - adc_or, + input adc_clk, + input adc_rst, + input [55:0] adc_data, + input adc_or, // channel interface - adc_dfmt_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [63:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter CHANNEL_ID = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input [55:0] adc_data; - input adc_or; - - // channel interface - - output [63:0] adc_dfmt_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad9680/axi_ad9680_if.v b/library/axi_ad9680/axi_ad9680_if.v index 14c71068e..d29a6d2a0 100644 --- a/library/axi_ad9680/axi_ad9680_if.v +++ b/library/axi_ad9680/axi_ad9680_if.v @@ -37,50 +37,30 @@ `timescale 1ns/100ps -module axi_ad9680_if ( +module axi_ad9680_if #( + + parameter DEVICE_TYPE = 0) ( // jesd interface // rx_clk is (line-rate/40) - rx_clk, - rx_sof, - rx_data, + input rx_clk, + input [ 3:0] rx_sof, + input [127:0] rx_data, // adc data output - adc_clk, - adc_rst, - adc_data_a, - adc_data_b, - adc_or_a, - adc_or_b, - adc_status); + output adc_clk, + input adc_rst, + output [55:0] adc_data_a, + output [55:0] adc_data_b, + output adc_or_a, + output adc_or_b, + output reg adc_status); - // parameters - - parameter DEVICE_TYPE = 0; - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk; - input [ 3:0] rx_sof; - input [127:0] rx_data; - - // adc data output - - output adc_clk; - input adc_rst; - output [55:0] adc_data_a; - output [55:0] adc_data_b; - output adc_or_a; - output adc_or_b; - output adc_status; // internal registers - reg adc_status = 'd0; - // internal signals wire [15:0] adc_data_a_s3_s; diff --git a/library/axi_ad9680/axi_ad9680_pnmon.v b/library/axi_ad9680/axi_ad9680_pnmon.v index 04cc55ab7..757e18fa8 100644 --- a/library/axi_ad9680/axi_ad9680_pnmon.v +++ b/library/axi_ad9680/axi_ad9680_pnmon.v @@ -44,31 +44,17 @@ module axi_ad9680_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [55:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, + output adc_pn_oos, + output adc_pn_err, // processor interface PN9 (0x0), PN23 (0x1) - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [55:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - - // processor interface PN9 (0x0), PN23 (0x1) - - input [ 3:0] adc_pnseq_sel; + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v index b878bec4d..1a60d6588 100644 --- a/library/axi_ad9684/axi_ad9684.v +++ b/library/axi_ad9684/axi_ad9684.v @@ -40,109 +40,62 @@ `timescale 1ns/100ps -module axi_ad9684 ( +module axi_ad9684 #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter OR_STATUS = 1) ( // device interface ports - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_data_or_p, - adc_data_or_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [13:0] adc_data_in_p, + input [13:0] adc_data_in_n, + input adc_data_or_p, + input adc_data_or_n, // dma interface ports - adc_clk, - adc_rst, - adc_valid_0, - adc_enable_0, - adc_data_0, - adc_valid_1, - adc_enable_1, - adc_data_1, - adc_dovf, - adc_dunf, + output adc_clk, + output adc_rst, + output adc_valid_0, + output adc_enable_0, + output [31:0] adc_data_0, + output adc_valid_1, + output adc_enable_1, + output [31:0] adc_data_1, + input adc_dovf, + input adc_dunf, // delay clock ports - delay_clk, + input delay_clk, // axi slave interface ports - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready -); - - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - parameter OR_STATUS = 1; - - // IO definitions - - input adc_clk_in_p; - input adc_clk_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - input adc_data_or_p; - input adc_data_or_n; - - output adc_clk; - output adc_rst; - output adc_valid_0; - output adc_enable_0; - output [31:0] adc_data_0; - output adc_valid_1; - output adc_enable_1; - output [31:0] adc_data_1; - input adc_dovf; - input adc_dunf; - - input delay_clk; - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready); // internal registers diff --git a/library/axi_ad9684/axi_ad9684_channel.v b/library/axi_ad9684/axi_ad9684_channel.v index 04b99873c..fb26e12c6 100644 --- a/library/axi_ad9684/axi_ad9684_channel.v +++ b/library/axi_ad9684/axi_ad9684_channel.v @@ -40,70 +40,42 @@ `timescale 1ns/100ps -module axi_ad9684_channel ( +module axi_ad9684_channel #( + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0) ( // adc data interface - adc_clk, - adc_rst, - adc_data, - adc_data_q, - adc_or, + input adc_clk, + input adc_rst, + input [27:0] adc_data, + input [27:0] adc_data_q, + input adc_or, // channel interface - adc_dfmt_data, - adc_valid, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, + output [31:0] adc_dfmt_data, + output adc_valid, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // up interface - up_clk, - up_rstn, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack -); + input up_clk, + input up_rstn, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter Q_OR_I_N = 0; - parameter CHANNEL_ID = 0; - parameter DATAPATH_DISABLE = 0; - - // IO definitions - - input adc_clk; - input adc_rst; - input [27:0] adc_data; - input [27:0] adc_data_q; - input adc_or; - - output [31:0] adc_dfmt_data; - output adc_enable; - output adc_valid; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; - - input up_clk; - input up_rstn; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v index 58e91058c..39282914b 100644 --- a/library/axi_ad9684/axi_ad9684_if.v +++ b/library/axi_ad9684/axi_ad9684_if.v @@ -40,95 +40,56 @@ `timescale 1ns/100ps -module axi_ad9684_if ( +module axi_ad9684_if #( + + parameter DEVICE_TYPE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter OR_STATUS = 0) ( // device interface - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, - adc_data_or_p, - adc_data_or_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [13:0] adc_data_in_p, + input [13:0] adc_data_in_n, + input adc_data_or_p, + input adc_data_or_n, // data interface - adc_clk, - adc_rst, - adc_data_a, - adc_or_a, - adc_data_b, - adc_or_b, - adc_status, + output adc_clk, + input adc_rst, + output [27:0] adc_data_a, + output adc_or_a, + output [27:0] adc_data_b, + output adc_or_b, + output reg adc_status, // delay interface - delay_clk, - delay_rst, - delay_dload, - delay_wdata, - delay_rdata, - delay_locked, + input delay_clk, + input delay_rst, + input [14:0] delay_dload, + input [74:0] delay_wdata, + output [74:0] delay_rdata, + output delay_locked, // reset - rst, + input rst, // drp interface - up_clk, - up_rstn, - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked -); + input up_clk, + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked); - // parameters - parameter DEVICE_TYPE = 0; // 0 - 7Series / 1 - 6Series - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - parameter OR_STATUS = 0; - // buffer type based on the target device localparam DDR_OR_SDR_N = 1; - // IO definitions - - input adc_clk_in_p; - input adc_clk_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - input adc_data_or_p; - input adc_data_or_n; - - output adc_clk; - input adc_rst; - output [27:0] adc_data_a; - output adc_or_a; - output [27:0] adc_data_b; - output adc_or_b; - output adc_status; - - input delay_clk; - input delay_rst; - input [14:0] delay_dload; - input [74:0] delay_wdata; - output [74:0] delay_rdata; - output delay_locked; - - input rst; - - input up_clk; - input up_rstn; - input up_drp_sel; - input up_drp_wr; - input [11:0] up_drp_addr; - input [31:0] up_drp_wdata; - output [31:0] up_drp_rdata; - output up_drp_ready; - output up_drp_locked; - // internal registers - reg adc_status = 'd0; reg adc_status_m1 = 'd0; // internal signals @@ -140,7 +101,6 @@ module axi_ad9684_if ( wire loaden_s; wire [ 7:0] phase_s; - genvar l_inst; // adc_clk is 1:2 of the sampling clock diff --git a/library/axi_ad9684/axi_ad9684_pnmon.v b/library/axi_ad9684/axi_ad9684_pnmon.v index e57102e9d..0a59b7e90 100644 --- a/library/axi_ad9684/axi_ad9684_pnmon.v +++ b/library/axi_ad9684/axi_ad9684_pnmon.v @@ -44,31 +44,17 @@ module axi_ad9684_pnmon ( // adc interface - adc_clk, - adc_data, + input adc_clk, + input [27:0] adc_data, // pn out of sync and error - adc_pn_oos, - adc_pn_err, + output adc_pn_oos, + output adc_pn_err, // processor interface PN9 (0x0), PN23 (0x1) - adc_pnseq_sel); - - // adc interface - - input adc_clk; - input [27:0] adc_data; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - - // processor interface PN9 (0x0), PN23 (0x1) - - input [ 3:0] adc_pnseq_sel; + input [ 3:0] adc_pnseq_sel); // internal registers diff --git a/library/axi_ad9739a/axi_ad9739a.v b/library/axi_ad9739a/axi_ad9739a.v index c7e2beead..6bd98ff41 100644 --- a/library/axi_ad9739a/axi_ad9739a.v +++ b/library/axi_ad9739a/axi_ad9739a.v @@ -39,104 +39,58 @@ `timescale 1ns/100ps -module axi_ad9739a ( +module axi_ad9739a #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter SERDES_OR_DDR_N = 1, + parameter MMCM_OR_BUFIO_N = 1, + parameter DAC_DATAPATH_DISABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // dac interface - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_data_out_a_p, - dac_data_out_a_n, - dac_data_out_b_p, - dac_data_out_b_n, + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output [ 13:0] dac_data_out_a_p, + output [ 13:0] dac_data_out_a_n, + output [ 13:0] dac_data_out_b_p, + output [ 13:0] dac_data_out_b_n, // dma interface - dac_div_clk, - dac_valid, - dac_enable, - dac_ddata, - dac_dovf, - dac_dunf, + output dac_div_clk, + output dac_valid, + output dac_enable, + input [255:0] dac_ddata, + input dac_dovf, + input dac_dunf, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter SERDES_OR_DDR_N = 1; - parameter MMCM_OR_BUFIO_N = 1; - parameter DAC_DATAPATH_DISABLE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // dac interface - - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output [ 13:0] dac_data_out_a_p; - output [ 13:0] dac_data_out_a_n; - output [ 13:0] dac_data_out_b_p; - output [ 13:0] dac_data_out_b_n; - - // dma interface - - output dac_div_clk; - output dac_valid; - output dac_enable; - input [255:0] dac_ddata; - input dac_dovf; - input dac_dunf; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal clocks and resets diff --git a/library/axi_ad9739a/axi_ad9739a_channel.v b/library/axi_ad9739a/axi_ad9739a_channel.v index 37b99bf45..5d80627b6 100644 --- a/library/axi_ad9739a/axi_ad9739a_channel.v +++ b/library/axi_ad9739a/axi_ad9739a_channel.v @@ -39,114 +39,55 @@ `timescale 1ns/100ps -module axi_ad9739a_channel ( +module axi_ad9739a_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_div_clk, - dac_rst, - dac_enable, - dac_data_00, - dac_data_01, - dac_data_02, - dac_data_03, - dac_data_04, - dac_data_05, - dac_data_06, - dac_data_07, - dac_data_08, - dac_data_09, - dac_data_10, - dac_data_11, - dac_data_12, - dac_data_13, - dac_data_14, - dac_data_15, - dma_data, + input dac_div_clk, + input dac_rst, + output reg dac_enable, + output reg [ 15:0] dac_data_00, + output reg [ 15:0] dac_data_01, + output reg [ 15:0] dac_data_02, + output reg [ 15:0] dac_data_03, + output reg [ 15:0] dac_data_04, + output reg [ 15:0] dac_data_05, + output reg [ 15:0] dac_data_06, + output reg [ 15:0] dac_data_07, + output reg [ 15:0] dac_data_08, + output reg [ 15:0] dac_data_09, + output reg [ 15:0] dac_data_10, + output reg [ 15:0] dac_data_11, + output reg [ 15:0] dac_data_12, + output reg [ 15:0] dac_data_13, + output reg [ 15:0] dac_data_14, + output reg [ 15:0] dac_data_15, + input [255:0] dma_data, // processor interface - dac_data_sync, - dac_dds_format, + input dac_data_sync, + input dac_dds_format, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output [ 31:0] up_rdata, + output up_rack); - // parameters - - parameter CHANNEL_ID = 32'h0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_div_clk; - input dac_rst; - output dac_enable; - output [ 15:0] dac_data_00; - output [ 15:0] dac_data_01; - output [ 15:0] dac_data_02; - output [ 15:0] dac_data_03; - output [ 15:0] dac_data_04; - output [ 15:0] dac_data_05; - output [ 15:0] dac_data_06; - output [ 15:0] dac_data_07; - output [ 15:0] dac_data_08; - output [ 15:0] dac_data_09; - output [ 15:0] dac_data_10; - output [ 15:0] dac_data_11; - output [ 15:0] dac_data_12; - output [ 15:0] dac_data_13; - output [ 15:0] dac_data_14; - output [ 15:0] dac_data_15; - input [255:0] dma_data; - - // processor interface - - input dac_data_sync; - input dac_dds_format; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [ 13:0] up_waddr; - input [ 31:0] up_wdata; - output up_wack; - input up_rreq; - input [ 13:0] up_raddr; - output [ 31:0] up_rdata; - output up_rack; // internal registers - reg dac_enable = 'd0; - reg [ 15:0] dac_data_00 = 'd0; - reg [ 15:0] dac_data_01 = 'd0; - reg [ 15:0] dac_data_02 = 'd0; - reg [ 15:0] dac_data_03 = 'd0; - reg [ 15:0] dac_data_04 = 'd0; - reg [ 15:0] dac_data_05 = 'd0; - reg [ 15:0] dac_data_06 = 'd0; - reg [ 15:0] dac_data_07 = 'd0; - reg [ 15:0] dac_data_08 = 'd0; - reg [ 15:0] dac_data_09 = 'd0; - reg [ 15:0] dac_data_10 = 'd0; - reg [ 15:0] dac_data_11 = 'd0; - reg [ 15:0] dac_data_12 = 'd0; - reg [ 15:0] dac_data_13 = 'd0; - reg [ 15:0] dac_data_14 = 'd0; - reg [ 15:0] dac_data_15 = 'd0; reg [ 15:0] dac_dds_phase_00_0 = 'd0; reg [ 15:0] dac_dds_phase_00_1 = 'd0; reg [ 15:0] dac_dds_phase_01_0 = 'd0; diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v index 0e8ed94f7..0b254b4a5 100644 --- a/library/axi_ad9739a/axi_ad9739a_core.v +++ b/library/axi_ad9739a/axi_ad9739a_core.v @@ -39,105 +39,57 @@ `timescale 1ns/100ps -module axi_ad9739a_core ( +module axi_ad9739a_core #( + + parameter ID = 0, + parameter DATAPATH_DISABLE = 0) ( // dac interface - dac_div_clk, - dac_rst, - dac_data_00, - dac_data_01, - dac_data_02, - dac_data_03, - dac_data_04, - dac_data_05, - dac_data_06, - dac_data_07, - dac_data_08, - dac_data_09, - dac_data_10, - dac_data_11, - dac_data_12, - dac_data_13, - dac_data_14, - dac_data_15, - dac_status, + input dac_div_clk, + output dac_rst, + output [ 15:0] dac_data_00, + output [ 15:0] dac_data_01, + output [ 15:0] dac_data_02, + output [ 15:0] dac_data_03, + output [ 15:0] dac_data_04, + output [ 15:0] dac_data_05, + output [ 15:0] dac_data_06, + output [ 15:0] dac_data_07, + output [ 15:0] dac_data_08, + output [ 15:0] dac_data_09, + output [ 15:0] dac_data_10, + output [ 15:0] dac_data_11, + output [ 15:0] dac_data_12, + output [ 15:0] dac_data_13, + output [ 15:0] dac_data_14, + output [ 15:0] dac_data_15, + input dac_status, // dma interface - dac_valid, - dac_enable, - dac_ddata, - dac_dovf, - dac_dunf, + output dac_valid, + output dac_enable, + input [255:0] dac_ddata, + input dac_dovf, + input dac_dunf, // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output reg [ 31:0] up_rdata, + output reg up_rack); - // parameters - - parameter ID = 0; - parameter DATAPATH_DISABLE = 0; - - // dac interface - - input dac_div_clk; - output dac_rst; - output [ 15:0] dac_data_00; - output [ 15:0] dac_data_01; - output [ 15:0] dac_data_02; - output [ 15:0] dac_data_03; - output [ 15:0] dac_data_04; - output [ 15:0] dac_data_05; - output [ 15:0] dac_data_06; - output [ 15:0] dac_data_07; - output [ 15:0] dac_data_08; - output [ 15:0] dac_data_09; - output [ 15:0] dac_data_10; - output [ 15:0] dac_data_11; - output [ 15:0] dac_data_12; - output [ 15:0] dac_data_13; - output [ 15:0] dac_data_14; - output [ 15:0] dac_data_15; - input dac_status; - - // dma interface - - output dac_valid; - output dac_enable; - input [255:0] dac_ddata; - input dac_dovf; - input dac_dunf; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [ 13:0] up_waddr; - input [ 31:0] up_wdata; - output up_wack; - input up_rreq; - input [ 13:0] up_raddr; - output [ 31:0] up_rdata; - output up_rack; // internal registers - reg [ 31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; - // internal signals wire dac_sync_s; diff --git a/library/axi_ad9739a/axi_ad9739a_if.v b/library/axi_ad9739a/axi_ad9739a_if.v index c333ca06f..ed810efac 100644 --- a/library/axi_ad9739a/axi_ad9739a_if.v +++ b/library/axi_ad9739a/axi_ad9739a_if.v @@ -41,90 +41,50 @@ `timescale 1ns/100ps -module axi_ad9739a_if ( +module axi_ad9739a_if #( + + parameter DEVICE_TYPE = 0) ( // dac interface - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_data_out_a_p, - dac_data_out_a_n, - dac_data_out_b_p, - dac_data_out_b_n, + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output [13:0] dac_data_out_a_p, + output [13:0] dac_data_out_a_n, + output [13:0] dac_data_out_b_p, + output [13:0] dac_data_out_b_n, // internal resets and clocks - dac_rst, - dac_clk, - dac_div_clk, - dac_status, + input dac_rst, + output dac_clk, + output dac_div_clk, + output reg dac_status, // data interface - dac_data_00, - dac_data_01, - dac_data_02, - dac_data_03, - dac_data_04, - dac_data_05, - dac_data_06, - dac_data_07, - dac_data_08, - dac_data_09, - dac_data_10, - dac_data_11, - dac_data_12, - dac_data_13, - dac_data_14, - dac_data_15); + input [15:0] dac_data_00, + input [15:0] dac_data_01, + input [15:0] dac_data_02, + input [15:0] dac_data_03, + input [15:0] dac_data_04, + input [15:0] dac_data_05, + input [15:0] dac_data_06, + input [15:0] dac_data_07, + input [15:0] dac_data_08, + input [15:0] dac_data_09, + input [15:0] dac_data_10, + input [15:0] dac_data_11, + input [15:0] dac_data_12, + input [15:0] dac_data_13, + input [15:0] dac_data_14, + input [15:0] dac_data_15); - // parameters - - parameter DEVICE_TYPE = 0; - - // dac interface - - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output [13:0] dac_data_out_a_p; - output [13:0] dac_data_out_a_n; - output [13:0] dac_data_out_b_p; - output [13:0] dac_data_out_b_n; - - // internal resets and clocks - - input dac_rst; - output dac_clk; - output dac_div_clk; - output dac_status; - - // data interface - - input [15:0] dac_data_00; - input [15:0] dac_data_01; - input [15:0] dac_data_02; - input [15:0] dac_data_03; - input [15:0] dac_data_04; - input [15:0] dac_data_05; - input [15:0] dac_data_06; - input [15:0] dac_data_07; - input [15:0] dac_data_08; - input [15:0] dac_data_09; - input [15:0] dac_data_10; - input [15:0] dac_data_11; - input [15:0] dac_data_12; - input [15:0] dac_data_13; - input [15:0] dac_data_14; - input [15:0] dac_data_15; // internal registers - reg dac_status = 'd0; - // internal signals wire dac_clk_in_s; diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v index 2a5586983..f5f66abf0 100644 --- a/library/axi_clkgen/axi_clkgen.v +++ b/library/axi_clkgen/axi_clkgen.v @@ -36,85 +36,51 @@ // *************************************************************************** // software programmable clock generator (still needs a reference input!) -module axi_clkgen ( +module axi_clkgen #( + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter CLKIN_PERIOD = 5.0, + parameter CLKIN2_PERIOD = 5.0, + parameter VCO_DIV = 11, + parameter VCO_MUL = 49, + parameter CLK0_DIV = 6, + parameter CLK0_PHASE = 0.000, + parameter CLK1_DIV = 6, + parameter CLK1_PHASE = 0.000, + parameter CLK2_DIV = 6, + parameter CLK2_PHASE = 0.000) ( // clocks - clk, - clk2, - clk_0, - clk_1, + input clk, + input clk2, + output clk_0, + output clk_1, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - // parameters - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter CLKIN_PERIOD = 5.0; - parameter CLKIN2_PERIOD = 5.0; - parameter VCO_DIV = 11; - parameter VCO_MUL = 49; - parameter CLK0_DIV = 6; - parameter CLK0_PHASE = 0.000; - parameter CLK1_DIV = 6; - parameter CLK1_PHASE = 0.000; - parameter CLK2_DIV = 6; - parameter CLK2_PHASE = 0.000; - - // clocks - - input clk; - input clk2; - output clk_0; - output clk_1; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; - + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // reset and clocks diff --git a/library/axi_gpreg/axi_gpreg_clock_mon.v b/library/axi_gpreg/axi_gpreg_clock_mon.v index 5549e704d..411d10d3b 100644 --- a/library/axi_gpreg/axi_gpreg_clock_mon.v +++ b/library/axi_gpreg/axi_gpreg_clock_mon.v @@ -37,54 +37,33 @@ `timescale 1ns/100ps -module axi_gpreg_clock_mon ( +module axi_gpreg_clock_mon #( + + parameter ID = 0, + parameter BUF_ENABLE = 0) ( // clock - d_clk, + input d_clk, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); - // parameters - - parameter ID = 0; - parameter BUF_ENABLE = 0; - - // clock - - input d_clk; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers reg up_d_preset = 'd0; - reg up_wack = 'd0; reg up_d_resetn = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; // internal signals diff --git a/library/axi_gpreg/axi_gpreg_io.v b/library/axi_gpreg/axi_gpreg_io.v index 956ee5033..0f03d3466 100644 --- a/library/axi_gpreg/axi_gpreg_io.v +++ b/library/axi_gpreg/axi_gpreg_io.v @@ -37,58 +37,32 @@ `timescale 1ns/100ps -module axi_gpreg_io ( +module axi_gpreg_io #( + + parameter ID = 0) ( // gpio - up_gp_ioenb, - up_gp_out, - up_gp_in, + output reg [31:0] up_gp_ioenb, + output reg [31:0] up_gp_out, + input [31:0] up_gp_in, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); - // parameters - - parameter ID = 0; - - // gpio - - output [31:0] up_gp_ioenb; - output [31:0] up_gp_out; - input [31:0] up_gp_in; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg up_wack = 'd0; - reg [31:0] up_gp_ioenb = 'd0; - reg [31:0] up_gp_out = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; - // internal signals wire up_wreq_s; diff --git a/library/axi_hdmi_rx/axi_hdmi_rx.v b/library/axi_hdmi_rx/axi_hdmi_rx.v index 3b6523f82..dc790ea75 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx.v @@ -37,87 +37,47 @@ // *************************************************************************** // *************************************************************************** -module axi_hdmi_rx ( +module axi_hdmi_rx #( + + parameter ID = 0) ( // hdmi interface - hdmi_rx_clk, - hdmi_rx_data, + input hdmi_rx_clk, + input [15:0] hdmi_rx_data, // dma interface - hdmi_clk, - hdmi_dma_sof, - hdmi_dma_de, - hdmi_dma_data, - hdmi_dma_ovf, - hdmi_dma_unf, + output hdmi_clk, + output hdmi_dma_sof, + output hdmi_dma_de, + output [63:0] hdmi_dma_data, + input hdmi_dma_ovf, + input hdmi_dma_unf, // processor interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - // parameters - - parameter ID = 0; - - // hdmi interface - - input hdmi_rx_clk; - input [15:0] hdmi_rx_data; - - // vdma interface - - output hdmi_clk; - output hdmi_dma_sof; - output hdmi_dma_de; - output [63:0] hdmi_dma_data; - input hdmi_dma_ovf; - input hdmi_dma_unf; - - // processor interface - - input s_axi_aresetn; - input s_axi_aclk; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal signals diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_core.v b/library/axi_hdmi_rx/axi_hdmi_rx_core.v index dc9e277cb..6fb227bf3 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_core.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_core.v @@ -40,60 +40,32 @@ module axi_hdmi_rx_core ( // hdmi interface - hdmi_clk, - hdmi_rst, - hdmi_data, - hdmi_edge_sel, - hdmi_bgr, - hdmi_packed, - hdmi_csc_bypass, - hdmi_vs_count, - hdmi_hs_count, - hdmi_tpm_oos, - hdmi_vs_oos, - hdmi_hs_oos, - hdmi_vs_mismatch, - hdmi_hs_mismatch, - hdmi_vs, - hdmi_hs, + input hdmi_clk, + input hdmi_rst, + input [15:0] hdmi_data, + input hdmi_edge_sel, + input hdmi_bgr, + input hdmi_packed, + input hdmi_csc_bypass, + input [15:0] hdmi_vs_count, + input [15:0] hdmi_hs_count, + output hdmi_tpm_oos, + output reg hdmi_vs_oos, + output reg hdmi_hs_oos, + output reg hdmi_vs_mismatch, + output reg hdmi_hs_mismatch, + output reg [15:0] hdmi_vs, + output reg [15:0] hdmi_hs, // dma interface - hdmi_dma_sof, - hdmi_dma_de, - hdmi_dma_data); - - // hdmi interface - - input hdmi_clk; - input hdmi_rst; - input [15:0] hdmi_data; - input hdmi_edge_sel; - input hdmi_bgr; - input hdmi_packed; - input hdmi_csc_bypass; - input [15:0] hdmi_vs_count; - input [15:0] hdmi_hs_count; - output hdmi_tpm_oos; - output hdmi_vs_oos; - output hdmi_hs_oos; - output hdmi_vs_mismatch; - output hdmi_hs_mismatch; - output [15:0] hdmi_vs; - output [15:0] hdmi_hs; - - // dma interface - - output hdmi_dma_sof; - output hdmi_dma_de; - output [63:0] hdmi_dma_data; + output reg hdmi_dma_sof, + output reg hdmi_dma_de, + output reg [63:0] hdmi_dma_data); // internal registers - reg hdmi_dma_sof = 'd0; - reg hdmi_dma_de = 'd0; reg hdmi_dma_de_cnt = 'd0; - reg [63:0] hdmi_dma_data = 'd0; reg hdmi_dma_sof_int = 'd0; reg hdmi_dma_de_int = 'd0; reg [31:0] hdmi_dma_data_int = 'd0; @@ -110,12 +82,6 @@ module axi_hdmi_rx_core ( reg hdmi_de_444_p = 'd0; reg [31:0] hdmi_data_444_p = 'd0; reg hdmi_dma_enable = 'd0; - reg [15:0] hdmi_vs = 'd0; - reg [15:0] hdmi_hs = 'd0; - reg hdmi_vs_oos = 'd0; - reg hdmi_hs_oos = 'd0; - reg hdmi_vs_mismatch = 'd0; - reg hdmi_hs_mismatch = 'd0; reg hdmi_hs_de_d = 'd0; reg hdmi_vs_de_d = 'd0; reg hdmi_sof = 'd0; diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_es.v b/library/axi_hdmi_rx/axi_hdmi_rx_es.v index 3c945f2c3..beb9da5b6 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_es.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_es.v @@ -36,32 +36,20 @@ // *************************************************************************** // Receive HDMI, hdmi embedded syncs data in, video dma data out. -module axi_hdmi_rx_es ( +module axi_hdmi_rx_es #( + + parameter DATA_WIDTH = 32) ( // hdmi interface - hdmi_clk, - hdmi_data, - hdmi_vs_de, - hdmi_hs_de, - hdmi_data_de); + input hdmi_clk, + input [(DATA_WIDTH-1):0] hdmi_data, + output reg hdmi_vs_de, + output reg hdmi_hs_de, + output reg [(DATA_WIDTH-1):0] hdmi_data_de); - // parameters - - parameter DATA_WIDTH = 32; localparam BYTE_WIDTH = DATA_WIDTH/8; - // hdmi interface - - input hdmi_clk; - input [(DATA_WIDTH-1):0] hdmi_data; - - // dma interface - - output hdmi_vs_de; - output hdmi_hs_de; - output [(DATA_WIDTH-1):0] hdmi_data_de; - // internal registers reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0; @@ -76,9 +64,6 @@ module axi_hdmi_rx_es ( reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0; reg hdmi_hs_de_rcv_4d = 'd0; reg hdmi_vs_de_rcv_4d = 'd0; - reg [(DATA_WIDTH-1):0] hdmi_data_de = 'd0; - reg hdmi_hs_de = 'd0; - reg hdmi_vs_de = 'd0; reg [ 1:0] hdmi_preamble_cnt = 'd0; reg hdmi_hs_de_rcv = 'd0; reg hdmi_vs_de_rcv = 'd0; diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v b/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v index b5d21b251..b415e195a 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v @@ -36,18 +36,12 @@ // *************************************************************************** module axi_hdmi_rx_tpm ( - hdmi_clk, - hdmi_sof, - hdmi_de, - hdmi_data, + input hdmi_clk, + input hdmi_sof, + input hdmi_de, + input [15:0] hdmi_data, - hdmi_tpm_oos); - - input hdmi_clk; - input hdmi_sof; - input hdmi_de; - input [15:0] hdmi_data; - output hdmi_tpm_oos; + output reg hdmi_tpm_oos); wire [15:0] hdmi_tpm_lr_data_s; wire hdmi_tpm_lr_mismatch_s; @@ -57,7 +51,6 @@ module axi_hdmi_rx_tpm ( reg [15:0] hdmi_tpm_data = 'd0; reg hdmi_tpm_lr_mismatch = 'd0; reg hdmi_tpm_fr_mismatch = 'd0; - reg hdmi_tpm_oos = 'd0; // Limited range assign hdmi_tpm_lr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h10) ? 8'h10 : diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index b0b08b758..5b9f4af30 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -35,141 +35,80 @@ // *************************************************************************** // *************************************************************************** -module axi_hdmi_tx ( +module axi_hdmi_tx #( + + parameter ID = 0, + parameter CR_CB_N = 0, + parameter DEVICE_TYPE = 0, + parameter EMBEDDED_SYNC = 0, + parameter OUT_CLK_POLARITY = 0) ( // hdmi interface - hdmi_clk, - hdmi_out_clk, + input hdmi_clk, + output hdmi_out_clk, // 16-bit interface - hdmi_16_hsync, - hdmi_16_vsync, - hdmi_16_data_e, - hdmi_16_data, - hdmi_16_es_data, + output hdmi_16_hsync, + output hdmi_16_vsync, + output hdmi_16_data_e, + output [15:0] hdmi_16_data, + output [15:0] hdmi_16_es_data, // 24-bit interface - hdmi_24_hsync, - hdmi_24_vsync, - hdmi_24_data_e, - hdmi_24_data, + output hdmi_24_hsync, + output hdmi_24_vsync, + output hdmi_24_data_e, + output [23:0] hdmi_24_data, // 36-bit interface - hdmi_36_hsync, - hdmi_36_vsync, - hdmi_36_data_e, - hdmi_36_data, + output hdmi_36_hsync, + output hdmi_36_vsync, + output hdmi_36_data_e, + output [35:0] hdmi_36_data, // vdma interface - vdma_clk, - vdma_fs, - vdma_fs_ret, - vdma_valid, - vdma_data, - vdma_ready, + input vdma_clk, + output vdma_fs, + input vdma_fs_ret, + input vdma_valid, + input [63:0] vdma_data, + output vdma_ready, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready); + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready); - // parameters - - parameter ID = 0; - parameter CR_CB_N = 0; - parameter DEVICE_TYPE = 0; - parameter EMBEDDED_SYNC = 0; /* 0 = Launch on rising edge, 1 = Launch on falling edge */ - parameter OUT_CLK_POLARITY = 0; localparam XILINX_7SERIES = 0; localparam XILINX_ULTRASCALE = 1; localparam ALTERA_5SERIES = 16; - // hdmi interface - - input hdmi_clk; - output hdmi_out_clk; - - // 16-bit interface - - output hdmi_16_hsync; - output hdmi_16_vsync; - output hdmi_16_data_e; - output [15:0] hdmi_16_data; - output [15:0] hdmi_16_es_data; - - // 24-bit interface - - output hdmi_24_hsync; - output hdmi_24_vsync; - output hdmi_24_data_e; - output [23:0] hdmi_24_data; - - // 36-bit interface - - output hdmi_36_hsync; - output hdmi_36_vsync; - output hdmi_36_data_e; - output [35:0] hdmi_36_data; - - // vdma interface - - input vdma_clk; - output vdma_fs; - input vdma_fs_ret; - input vdma_valid; - input [63:0] vdma_data; - output vdma_ready; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - // reset and clocks wire up_rstn; diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v index 6a3ff7bb9..d324c2e07 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v @@ -36,145 +36,80 @@ // *************************************************************************** // Transmit HDMI, video dma data in, hdmi separate syncs data out. -module axi_hdmi_tx_core ( +module axi_hdmi_tx_core #( + + parameter CR_CB_N = 0, + parameter EMBEDDED_SYNC = 0) ( // hdmi interface - hdmi_clk, - hdmi_rst, + input hdmi_clk, + input hdmi_rst, // 16-bit interface - hdmi_16_hsync, - hdmi_16_vsync, - hdmi_16_data_e, - hdmi_16_data, - hdmi_16_es_data, + output reg hdmi_16_hsync, + output reg hdmi_16_vsync, + output reg hdmi_16_data_e, + output reg [15:0] hdmi_16_data, + output reg [15:0] hdmi_16_es_data, // 24-bit interface - hdmi_24_hsync, - hdmi_24_vsync, - hdmi_24_data_e, - hdmi_24_data, + output reg hdmi_24_hsync, + output reg hdmi_24_vsync, + output reg hdmi_24_data_e, + output reg [23:0] hdmi_24_data, // 36-bit interface - hdmi_36_hsync, - hdmi_36_vsync, - hdmi_36_data_e, - hdmi_36_data, + output reg hdmi_36_hsync, + output reg hdmi_36_vsync, + output reg hdmi_36_data_e, + output reg [35:0] hdmi_36_data, // control signals - hdmi_fs_toggle, - hdmi_raddr_g, - hdmi_tpm_oos, - hdmi_status, + output reg hdmi_fs_toggle, + output reg [ 8:0] hdmi_raddr_g, + output reg hdmi_tpm_oos, + output reg hdmi_status, // vdma interface - vdma_clk, - vdma_wr, - vdma_waddr, - vdma_wdata, - vdma_fs_ret_toggle, - vdma_fs_waddr, + input vdma_clk, + input vdma_wr, + input [ 8:0] vdma_waddr, + input [47:0] vdma_wdata, + input vdma_fs_ret_toggle, + input [ 8:0] vdma_fs_waddr, // processor interface - hdmi_csc_bypass, - hdmi_ss_bypass, - hdmi_srcsel, - hdmi_const_rgb, - hdmi_hl_active, - hdmi_hl_width, - hdmi_hs_width, - hdmi_he_max, - hdmi_he_min, - hdmi_vf_active, - hdmi_vf_width, - hdmi_vs_width, - hdmi_ve_max, - hdmi_ve_min, - hdmi_clip_max, - hdmi_clip_min); + input hdmi_csc_bypass, + input hdmi_ss_bypass, + input [ 1:0] hdmi_srcsel, + input [23:0] hdmi_const_rgb, + input [15:0] hdmi_hl_active, + input [15:0] hdmi_hl_width, + input [15:0] hdmi_hs_width, + input [15:0] hdmi_he_max, + input [15:0] hdmi_he_min, + input [15:0] hdmi_vf_active, + input [15:0] hdmi_vf_width, + input [15:0] hdmi_vs_width, + input [15:0] hdmi_ve_max, + input [15:0] hdmi_ve_min, + input [23:0] hdmi_clip_max, + input [23:0] hdmi_clip_min); - // parameters - - parameter CR_CB_N = 0; - parameter EMBEDDED_SYNC = 0; - - // hdmi interface - - input hdmi_clk; - input hdmi_rst; - - // 16-bit interface - - output hdmi_16_hsync; - output hdmi_16_vsync; - output hdmi_16_data_e; - output [15:0] hdmi_16_data; - output [15:0] hdmi_16_es_data; - - // 24-bit interface - - output hdmi_24_hsync; - output hdmi_24_vsync; - output hdmi_24_data_e; - output [23:0] hdmi_24_data; - - // 36-bit interface - - output hdmi_36_hsync; - output hdmi_36_vsync; - output hdmi_36_data_e; - output [35:0] hdmi_36_data; - - // control signals - - output hdmi_fs_toggle; - output [ 8:0] hdmi_raddr_g; - output hdmi_tpm_oos; - output hdmi_status; - - // vdma interface - - input vdma_clk; - input vdma_wr; - input [ 8:0] vdma_waddr; - input [47:0] vdma_wdata; - input vdma_fs_ret_toggle; - input [ 8:0] vdma_fs_waddr; - - // processor interface - - input hdmi_csc_bypass; - input hdmi_ss_bypass; - input [ 1:0] hdmi_srcsel; - input [23:0] hdmi_const_rgb; - input [15:0] hdmi_hl_active; - input [15:0] hdmi_hl_width; - input [15:0] hdmi_hs_width; - input [15:0] hdmi_he_max; - input [15:0] hdmi_he_min; - input [15:0] hdmi_vf_active; - input [15:0] hdmi_vf_width; - input [15:0] hdmi_vs_width; - input [15:0] hdmi_ve_max; - input [15:0] hdmi_ve_min; - input [23:0] hdmi_clip_max; - input [23:0] hdmi_clip_min; // internal registers - reg hdmi_status = 'd0; reg hdmi_enable = 'd0; reg [15:0] hdmi_hs_count = 'd0; reg [15:0] hdmi_vs_count = 'd0; reg hdmi_fs = 'd0; - reg hdmi_fs_toggle = 'd0; reg hdmi_fs_ret_toggle_m1 = 'd0; reg hdmi_fs_ret_toggle_m2 = 'd0; reg hdmi_fs_ret_toggle_m3 = 'd0; @@ -185,7 +120,6 @@ module axi_hdmi_tx_core ( reg hdmi_hs_de = 'd0; reg hdmi_vs_de = 'd0; reg [ 9:0] hdmi_raddr = 'd0; - reg [ 8:0] hdmi_raddr_g = 'd0; reg hdmi_hs_d = 'd0; reg hdmi_vs_d = 'd0; reg hdmi_hs_de_d = 'd0; @@ -200,11 +134,6 @@ module axi_hdmi_tx_core ( reg hdmi_data_sel_2d = 'd0; reg [47:0] hdmi_data_2d = 'd0; reg [23:0] hdmi_tpm_data = 'd0; - reg hdmi_tpm_oos = 'd0; - reg hdmi_36_hsync = 'd0; - reg hdmi_36_vsync = 'd0; - reg hdmi_36_data_e = 'd0; - reg [35:0] hdmi_36_data = 'd0; reg hdmi_hsync = 'd0; reg hdmi_vsync = 'd0; reg hdmi_hsync_data_e = 'd0; @@ -217,14 +146,8 @@ module axi_hdmi_tx_core ( reg hdmi_24_csc_vsync_data_e = 'd0; reg hdmi_24_csc_data_e = 'd0; reg [23:0] hdmi_24_csc_data = 'd0; - reg hdmi_24_hsync = 'd0; - reg hdmi_24_vsync = 'd0; reg hdmi_24_hsync_data_e = 'd0; reg hdmi_24_vsync_data_e = 'd0; - reg hdmi_24_data_e = 'd0; - reg [23:0] hdmi_24_data = 'd0; - reg hdmi_16_hsync = 'd0; - reg hdmi_16_vsync = 'd0; reg hdmi_16_hsync_data_e = 'd0; reg hdmi_16_vsync_data_e = 'd0; reg hdmi_16_hsync_d = 'd0; @@ -233,12 +156,9 @@ module axi_hdmi_tx_core ( reg hdmi_16_vsync_data_e_d = 'd0; reg hdmi_16_data_e_d = 'd0; reg [15:0] hdmi_16_data_d = 'd0; - reg hdmi_16_data_e = 'd0; - reg [15:0] hdmi_16_data = 'd0; reg hdmi_es_hs_de = 'd0; reg hdmi_es_vs_de = 'd0; reg [15:0] hdmi_es_data = 'd0; - reg [15:0] hdmi_16_es_data = 'd0; reg [23:0] hdmi_clip_data = 'd0; reg hdmi_clip_hs_de_d = 'd0; reg hdmi_clip_vs_de_d = 'd0; @@ -272,7 +192,6 @@ module axi_hdmi_tx_core ( wire [15:0] hdmi_ss_data_s; wire [15:0] hdmi_es_data_s; - // binary to grey conversion function [8:0] b2g; diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_es.v b/library/axi_hdmi_tx/axi_hdmi_tx_es.v index 5ecef3aec..c85cb7ff0 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_es.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_es.v @@ -38,29 +38,20 @@ // *************************************************************************** // Transmit HDMI, video dma data in, hdmi separate syncs data out. -module axi_hdmi_tx_es ( +module axi_hdmi_tx_es #( + + parameter DATA_WIDTH = 32) ( // hdmi interface - hdmi_clk, - hdmi_hs_de, - hdmi_vs_de, - hdmi_data_de, - hdmi_data); + input hdmi_clk, + input hdmi_hs_de, + input hdmi_vs_de, + input [(DATA_WIDTH-1):0] hdmi_data_de, + output reg [(DATA_WIDTH-1):0] hdmi_data); - // parameters - - parameter DATA_WIDTH = 32; localparam BYTE_WIDTH = DATA_WIDTH/8; - // hdmi interface - - input hdmi_clk; - input hdmi_hs_de; - input hdmi_vs_de; - input [(DATA_WIDTH-1):0] hdmi_data_de; - output [(DATA_WIDTH-1):0] hdmi_data; - // internal registers reg hdmi_hs_de_d = 'd0; @@ -73,7 +64,6 @@ module axi_hdmi_tx_es ( reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0; reg hdmi_hs_de_5d = 'd0; reg [(DATA_WIDTH-1):0] hdmi_data_5d = 'd0; - reg [(DATA_WIDTH-1):0] hdmi_data = 'd0; // internal wires diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v b/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v index 24b9e449c..16714974c 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v @@ -40,79 +40,44 @@ module axi_hdmi_tx_vdma ( // hdmi interface - hdmi_fs_toggle, - hdmi_raddr_g, + input hdmi_fs_toggle, + input [ 8:0] hdmi_raddr_g, // vdma interface - vdma_clk, - vdma_rst, - vdma_fs, - vdma_fs_ret, - vdma_valid, - vdma_data, - vdma_ready, - vdma_wr, - vdma_waddr, - vdma_wdata, - vdma_fs_ret_toggle, - vdma_fs_waddr, - vdma_tpm_oos, - vdma_ovf, - vdma_unf); - - // parameters + input vdma_clk, + input vdma_rst, + output reg vdma_fs, + input vdma_fs_ret, + input vdma_valid, + input [63:0] vdma_data, + output reg vdma_ready, + output reg vdma_wr, + output reg [ 8:0] vdma_waddr, + output reg [47:0] vdma_wdata, + output reg vdma_fs_ret_toggle, + output reg [ 8:0] vdma_fs_waddr, + output reg vdma_tpm_oos, + output reg vdma_ovf, + output reg vdma_unf); localparam BUF_THRESHOLD_LO = 9'd3; localparam BUF_THRESHOLD_HI = 9'd509; localparam RDY_THRESHOLD_LO = 9'd450; localparam RDY_THRESHOLD_HI = 9'd500; - // hdmi interface - - input hdmi_fs_toggle; - input [ 8:0] hdmi_raddr_g; - - // vdma interface - - input vdma_clk; - input vdma_rst; - output vdma_fs; - input vdma_fs_ret; - input vdma_valid; - input [63:0] vdma_data; - output vdma_ready; - output vdma_wr; - output [ 8:0] vdma_waddr; - output [47:0] vdma_wdata; - output vdma_fs_ret_toggle; - output [ 8:0] vdma_fs_waddr; - output vdma_tpm_oos; - output vdma_ovf; - output vdma_unf; - // internal registers reg vdma_fs_toggle_m1 = 'd0; reg vdma_fs_toggle_m2 = 'd0; reg vdma_fs_toggle_m3 = 'd0; - reg vdma_fs = 'd0; - reg [ 8:0] vdma_fs_waddr = 'd0; - reg vdma_fs_ret_toggle = 'd0; - reg vdma_wr = 'd0; - reg [ 8:0] vdma_waddr = 'd0; - reg [47:0] vdma_wdata = 'd0; reg [22:0] vdma_tpm_data = 'd0; - reg vdma_tpm_oos = 'd0; reg [ 8:0] vdma_raddr_g_m1 = 'd0; reg [ 8:0] vdma_raddr_g_m2 = 'd0; reg [ 8:0] vdma_raddr = 'd0; reg [ 8:0] vdma_addr_diff = 'd0; - reg vdma_ready = 'd0; reg vdma_almost_full = 'd0; reg vdma_almost_empty = 'd0; - reg vdma_ovf = 'd0; - reg vdma_unf = 'd0; // internal wires diff --git a/library/axi_usb_fx3/axi_usb_fx3.v b/library/axi_usb_fx3/axi_usb_fx3.v index 4478990d2..afdd4c039 100644 --- a/library/axi_usb_fx3/axi_usb_fx3.v +++ b/library/axi_usb_fx3/axi_usb_fx3.v @@ -43,142 +43,72 @@ module axi_usb_fx3 ( // gpif ii - dma_rdy, - dma_wmk, + input dma_rdy, + input dma_wmk, - fifo_rdy, + input [ 3:0] fifo_rdy, - pclk, //output clk 100 Mhz and 180 phase shift + output pclk, - data, - addr, //output fifo address + inout [31:0] data, + output [ 1:0] addr, - slcs_n, //output chip select - slrd_n, //output read select - sloe_n, //output output enable select - slwr_n, //output write select - pktend_n, //output pkt end - epswitch_n, //output EP Switch + output slcs_n, + output slrd_n, + output sloe_n, + output slwr_n, + output pktend_n, + output epswitch_n, // irq - irq, + output irq, // DEBUG - debug_fx32dma, - debug_dma2fx3, - debug_status, + output [74:0] debug_fx32dma, + output [73:0] debug_dma2fx3, + output [14:0] debug_status, // s2mm - s_axis_tdata, - s_axis_tkeep, - s_axis_tlast, - s_axis_tvalid, - s_axis_tready, + input [31:0] s_axis_tdata, + input [ 3:0] s_axis_tkeep, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, // mm2s - m_axis_tready, - m_axis_tdata, - m_axis_tkeep, - m_axis_tlast, - m_axis_tvalid, + input m_axis_tready, + output [31:0] m_axis_tdata, + output [ 3:0] m_axis_tkeep, + output m_axis_tlast, + output m_axis_tvalid, // axi lite - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready); - - // gpif ii - - input dma_rdy; - input dma_wmk; - - input [ 3:0] fifo_rdy; - - output pclk; - - inout [31:0] data; - output [ 1:0] addr; - - output slcs_n; - output slrd_n; - output sloe_n; - output slwr_n; - output pktend_n; - output epswitch_n; - - // DEBUG - - output [74:0] debug_fx32dma; - output [73:0] debug_dma2fx3; - output [14:0] debug_status; - - // irq - - output irq; - - // s2mm - - input [31:0] s_axis_tdata; - input [ 3:0] s_axis_tkeep; - input s_axis_tlast; - input s_axis_tvalid; - output s_axis_tready; - - // mm2s - - input m_axis_tready; - output [31:0] m_axis_tdata; - output [ 3:0] m_axis_tkeep; - output m_axis_tlast; - output m_axis_tvalid; - - // axi lite - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready); // internal clocks & resets diff --git a/library/axi_usb_fx3/axi_usb_fx3_core.v b/library/axi_usb_fx3/axi_usb_fx3_core.v index 943354361..f4079c188 100644 --- a/library/axi_usb_fx3/axi_usb_fx3_core.v +++ b/library/axi_usb_fx3/axi_usb_fx3_core.v @@ -40,203 +40,104 @@ module axi_usb_fx3_core ( - clk, - reset, + input clk, + input reset, // s2mm - s_axis_tdata, - s_axis_tkeep, - s_axis_tlast, - s_axis_tready, - s_axis_tvalid, + input [31:0] s_axis_tdata, + input [ 3:0] s_axis_tkeep, + input s_axis_tlast, + output reg s_axis_tready, + input s_axis_tvalid, // mm2s - m_axis_tdata, - m_axis_tkeep, - m_axis_tlast, - m_axis_tready, - m_axis_tvalid, + output reg [31:0] m_axis_tdata, + output reg [ 3:0] m_axis_tkeep, + output reg m_axis_tlast, + input m_axis_tready, + output reg m_axis_tvalid, // configuration - fifo0_header_size, - fifo0_buffer_size, + input [ 7:0] fifo0_header_size, + input [15:0] fifo0_buffer_size, - fifo1_header_size, - fifo1_buffer_size, + input [ 7:0] fifo1_header_size, + input [15:0] fifo1_buffer_size, - fifo2_header_size, - fifo2_buffer_size, + input [ 7:0] fifo2_header_size, + input [15:0] fifo2_buffer_size, - fifo3_header_size, - fifo3_buffer_size, + input [ 7:0] fifo3_header_size, + input [15:0] fifo3_buffer_size, - fifo4_header_size, - fifo4_buffer_size, + input [ 7:0] fifo4_header_size, + input [15:0] fifo4_buffer_size, - fifo5_header_size, - fifo5_buffer_size, + input [ 7:0] fifo5_header_size, + input [15:0] fifo5_buffer_size, - fifo6_header_size, - fifo6_buffer_size, + input [ 7:0] fifo6_header_size, + input [15:0] fifo6_buffer_size, - fifo7_header_size, - fifo7_buffer_size, + input [ 7:0] fifo7_header_size, + input [15:0] fifo7_buffer_size, - fifo8_header_size, - fifo8_buffer_size, + input [ 7:0] fifo8_header_size, + input [15:0] fifo8_buffer_size, - fifo9_header_size, - fifo9_buffer_size, + input [ 7:0] fifo9_header_size, + input [15:0] fifo9_buffer_size, - fifoa_header_size, - fifoa_buffer_size, + input [ 7:0] fifoa_header_size, + input [15:0] fifoa_buffer_size, - fifob_header_size, - fifob_buffer_size, + input [ 7:0] fifob_header_size, + input [15:0] fifob_buffer_size, - fifoc_header_size, - fifoc_buffer_size, + input [ 7:0] fifoc_header_size, + input [15:0] fifoc_buffer_size, - fifod_header_size, - fifod_buffer_size, + input [ 7:0] fifod_header_size, + input [15:0] fifod_buffer_size, - fifoe_header_size, - fifoe_buffer_size, + input [ 7:0] fifoe_header_size, + input [15:0] fifoe_buffer_size, - fifof_header_size, - fifof_buffer_size, + input [ 7:0] fifof_header_size, + input [15:0] fifof_buffer_size, - length_fx32dma, - length_dma2fx3, + output reg [31:0] length_fx32dma, + output reg [31:0] length_dma2fx3, // fx3 interface // IN -> TO HOST / FX3 // OUT -> FROM HOST / FX3 - fx32dma_valid, - fx32dma_ready, - fx32dma_data, - fx32dma_sop, - fx32dma_eop, + input fx32dma_valid, + output fx32dma_ready, + input [31:0] fx32dma_data, + input fx32dma_sop, + output reg fx32dma_eop, - dma2fx3_ready, - dma2fx3_valid, - dma2fx3_data, - dma2fx3_eop, + input dma2fx3_ready, + output reg dma2fx3_valid, + output reg [31:0] dma2fx3_data, + output reg dma2fx3_eop, - error, - eot_fx32dma, - eot_dma2fx3, + output error, + output reg eot_fx32dma, + output reg eot_dma2fx3, - test_mode_tpm, - test_mode_tpg, - monitor_error, + input [ 2:0] test_mode_tpm, + input [ 2:0] test_mode_tpg, + output reg monitor_error, - zlp, + input zlp, - fifo_num); - - input clk; - input reset; - - // s2mm - - input m_axis_tready; - output [31:0] m_axis_tdata; - output [ 3:0] m_axis_tkeep; - output m_axis_tlast; - output m_axis_tvalid; - - // mm2s - - input [31:0] s_axis_tdata; - input [ 3:0] s_axis_tkeep; - input s_axis_tlast; - input s_axis_tvalid; - output s_axis_tready; - - // configuration - - input [ 7:0] fifo0_header_size; - input [15:0] fifo0_buffer_size; - - input [ 7:0] fifo1_header_size; - input [15:0] fifo1_buffer_size; - - input [ 7:0] fifo2_header_size; - input [15:0] fifo2_buffer_size; - - input [ 7:0] fifo3_header_size; - input [15:0] fifo3_buffer_size; - - input [ 7:0] fifo4_header_size; - input [15:0] fifo4_buffer_size; - - input [ 7:0] fifo5_header_size; - input [15:0] fifo5_buffer_size; - - input [ 7:0] fifo6_header_size; - input [15:0] fifo6_buffer_size; - - input [ 7:0] fifo7_header_size; - input [15:0] fifo7_buffer_size; - - input [ 7:0] fifo8_header_size; - input [15:0] fifo8_buffer_size; - - input [ 7:0] fifo9_header_size; - input [15:0] fifo9_buffer_size; - - input [ 7:0] fifoa_header_size; - input [15:0] fifoa_buffer_size; - - input [ 7:0] fifob_header_size; - input [15:0] fifob_buffer_size; - - input [ 7:0] fifoc_header_size; - input [15:0] fifoc_buffer_size; - - input [ 7:0] fifod_header_size; - input [15:0] fifod_buffer_size; - - input [ 7:0] fifoe_header_size; - input [15:0] fifoe_buffer_size; - - input [ 7:0] fifof_header_size; - input [15:0] fifof_buffer_size; - - output [31:0] length_fx32dma; - output [31:0] length_dma2fx3; - - // FX3 interface - // IN -> ZYNQ TO HOST / FX3 - // OUT -> ZYNQ FROM HOST / FX3 - - input fx32dma_valid; - output fx32dma_ready; - input [31:0] fx32dma_data; - input fx32dma_sop; - output fx32dma_eop; - - input dma2fx3_ready; - output dma2fx3_valid; - output [31:0] dma2fx3_data; - output dma2fx3_eop; - - output error; - output eot_fx32dma; - output eot_dma2fx3; - - input [ 2:0] test_mode_tpm; - input [ 2:0] test_mode_tpg; - output monitor_error; - - input zlp; - - input [ 4:0] fifo_num; + input [ 4:0] fifo_num); // internal parameters @@ -256,14 +157,6 @@ module axi_usb_fx3_core ( reg [15:0] buffer_size_current = 16'h0; reg [ 7:0] header_size_current = 8'h0; - reg [31:0] m_axis_tdata = 32'h0; - reg [ 3:0] m_axis_tkeep = 4'h0; - reg m_axis_tlast = 1'b0; - reg m_axis_tvalid = 1'b0; - - reg eot_fx32dma = 1'b0; - reg eot_dma2fx3 = 1'b0; - reg error_fx32dma = 1'b0; reg error_dma2fx3 = 1'b0; @@ -279,21 +172,11 @@ module axi_usb_fx3_core ( reg [31:0] dma2fx3_counter = 32'h0; reg [ 7:0] footer_pointer = 8'h0; - reg s_axis_tready = 1'b0; - reg dma2fx3_valid = 1'b0; - reg [31:0] dma2fx3_data = 32'h0; reg [31:0] dma2fx3_data_reg = 32'h0; - reg dma2fx3_eop = 1'b0; reg [31:0] expected_data = 32'h0; - reg monitor_error = 1'b0; reg first_transfer = 1'b0; - reg [31:0] length_fx32dma = 0; - reg [31:0] length_dma2fx3 = 0; - - reg fx32dma_eop = 1'b0; - function [31:0] pn23; input [31:0] din; reg [31:0] dout; diff --git a/library/axi_usb_fx3/axi_usb_fx3_if.v b/library/axi_usb_fx3/axi_usb_fx3_if.v index 2a0a387ba..3938d48cb 100644 --- a/library/axi_usb_fx3/axi_usb_fx3_if.v +++ b/library/axi_usb_fx3/axi_usb_fx3_if.v @@ -39,105 +39,56 @@ module axi_usb_fx3_if ( - dma_rdy, - dma_wmk, + input dma_rdy, + input dma_wmk, - fifo_rdy, + input [ 3:0] fifo_rdy, - pclk, //output clk 100 Mhz and 180 phase shift - reset_n, + input pclk, + input reset_n, - data, - addr, //output fifo address + inout [31:0] data, + output reg [ 1:0] addr, - slcs_n, //output chip select - slrd_n, //output read select - sloe_n, //output output enable select - slwr_n, //output write select - pktend_n, //output pkt end - epswitch_n, //output pkt end + output reg slcs_n, + output reg slrd_n, + output reg sloe_n, + output reg slwr_n, + output reg pktend_n, + output epswitch_n, - fifo_num, - fifo_direction, - trig, - fifo_ready, + input [ 4:0] fifo_num, + input [10:0] fifo_direction, + input trig, + output reg [10:0] fifo_ready, - fx32dma_valid, - fx32dma_ready, - fx32dma_data, - fx32dma_sop, - fx32dma_eop, - eot_fx32dma, + output reg fx32dma_valid, + input fx32dma_ready, + output reg [31:0] fx32dma_data, + output reg fx32dma_sop, + input fx32dma_eop, + input eot_fx32dma, - dma2fx3_ready, - dma2fx3_valid, - dma2fx3_data, - dma2fx3_eop); - - input pclk; - input reset_n; - - input dma_rdy; - input dma_wmk; - - input [ 3:0] fifo_rdy; - - inout [31:0] data; - output [ 1:0] addr; - - output slcs_n; - output slrd_n; - output sloe_n; - output slwr_n; - output pktend_n; - output epswitch_n; - - output [10:0] fifo_ready; - - input [ 4:0] fifo_num; - input [10:0] fifo_direction; - input trig; - - output fx32dma_valid; - input fx32dma_ready; - output [31:0] fx32dma_data; - output fx32dma_sop; - input fx32dma_eop; - input eot_fx32dma; - - input dma2fx3_valid; - output dma2fx3_ready; - input [31:0] dma2fx3_data; - input dma2fx3_eop; + output reg dma2fx3_ready, + input dma2fx3_valid, + input [31:0] dma2fx3_data, + input dma2fx3_eop); // internal registers - reg [10:0] fifo_ready = 0; - - reg [31:0] fx32dma_data = 0; - reg [ 3:0] state_gpif_ii = 4'h0; reg [ 3:0] next_state_gpif_ii = 4'h0; reg current_direction = 0; reg current_fifo = 0; - reg slcs_n = 0; reg slcs_n_d1 = 0; reg slcs_n_d2 = 0; reg slcs_n_d3 = 0; reg slcs_n_d4 = 0; - reg slrd_n = 0; reg slrd_n_d1 = 0; reg slrd_n_d2 = 0; reg slrd_n_d3 = 0; - reg sloe_n = 0; - reg [ 1:0] addr = 0; reg sloe_n_d1 = 0; - reg slwr_n = 0; - reg fx32dma_valid = 0; - reg dma2fx3_ready = 0; - reg fx32dma_sop = 0; - reg pktend_n = 0; reg pip = 0; localparam IDLE = 4'b0001; diff --git a/library/axi_usb_fx3/axi_usb_fx3_reg.v b/library/axi_usb_fx3/axi_usb_fx3_reg.v index 2bf33d20a..9b03f5e29 100644 --- a/library/axi_usb_fx3/axi_usb_fx3_reg.v +++ b/library/axi_usb_fx3/axi_usb_fx3_reg.v @@ -43,159 +43,81 @@ module axi_usb_fx3_reg ( // gpif ii - fifo_rdy, + input [10:0] fifo_rdy, - eot_fx32dma, - eot_dma2fx3, - trig, - zlp, - fifo_num, + input eot_fx32dma, + input eot_dma2fx3, + output trig, + output zlp, + output [ 4:0] fifo_num, - error, + input error, - test_mode_tpm, - test_mode_tpg, - monitor_error, + output [ 2:0] test_mode_tpm, + output [ 2:0] test_mode_tpg, + input monitor_error, - irq, + output irq, - fifo0_direction, - fifo0_header_size, - fifo0_buffer_size, + output fifo0_direction, + output [ 7:0] fifo0_header_size, + output [15:0] fifo0_buffer_size, - fifo1_direction, - fifo1_header_size, - fifo1_buffer_size, + output fifo1_direction, + output [ 7:0] fifo1_header_size, + output [15:0] fifo1_buffer_size, - fifo2_direction, - fifo2_header_size, - fifo2_buffer_size, + output fifo2_direction, + output [ 7:0] fifo2_header_size, + output [15:0] fifo2_buffer_size, - fifo3_direction, - fifo3_header_size, - fifo3_buffer_size, + output fifo3_direction, + output [ 7:0] fifo3_header_size, + output [15:0] fifo3_buffer_size, - fifo4_direction, - fifo4_header_size, - fifo4_buffer_size, + output fifo4_direction, + output [ 7:0] fifo4_header_size, + output [15:0] fifo4_buffer_size, - fifo5_direction, - fifo5_header_size, - fifo5_buffer_size, + output fifo5_direction, + output [ 7:0] fifo5_header_size, + output [15:0] fifo5_buffer_size, - fifo6_direction, - fifo6_header_size, - fifo6_buffer_size, + output fifo6_direction, + output [ 7:0] fifo6_header_size, + output [15:0] fifo6_buffer_size, - fifo7_direction, - fifo7_header_size, - fifo7_buffer_size, + output fifo7_direction, + output [ 7:0] fifo7_header_size, + output [15:0] fifo7_buffer_size, - fifo8_direction, - fifo8_header_size, - fifo8_buffer_size, + output fifo8_direction, + output [ 7:0] fifo8_header_size, + output [15:0] fifo8_buffer_size, - fifo9_direction, - fifo9_header_size, - fifo9_buffer_size, + output fifo9_direction, + output [ 7:0] fifo9_header_size, + output [15:0] fifo9_buffer_size, - fifoa_direction, - fifoa_header_size, - fifoa_buffer_size, + output fifoa_direction, + output [ 7:0] fifoa_header_size, + output [15:0] fifoa_buffer_size, - length_fx32dma, - length_dma2fx3, + input [31:0] length_fx32dma, + input [31:0] length_dma2fx3, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // GPIF II - - input [10:0] fifo_rdy; - - input eot_fx32dma; - input eot_dma2fx3; - output trig; - output zlp; - output [ 4:0] fifo_num; - - input error; - - input monitor_error; - output [ 2:0] test_mode_tpm; - output [ 2:0] test_mode_tpg; - - output irq; - - output fifo0_direction; - output [ 7:0] fifo0_header_size; - output [15:0] fifo0_buffer_size; - - output fifo1_direction; - output [ 7:0] fifo1_header_size; - output [15:0] fifo1_buffer_size; - - output fifo2_direction; - output [ 7:0] fifo2_header_size; - output [15:0] fifo2_buffer_size; - - output fifo3_direction; - output [ 7:0] fifo3_header_size; - output [15:0] fifo3_buffer_size; - - output fifo4_direction; - output [ 7:0] fifo4_header_size; - output [15:0] fifo4_buffer_size; - - output fifo5_direction; - output [ 7:0] fifo5_header_size; - output [15:0] fifo5_buffer_size; - - output fifo6_direction; - output [ 7:0] fifo6_header_size; - output [15:0] fifo6_buffer_size; - - output fifo7_direction; - output [ 7:0] fifo7_header_size; - output [15:0] fifo7_buffer_size; - - output fifo8_direction; - output [ 7:0] fifo8_header_size; - output [15:0] fifo8_buffer_size; - - output fifo9_direction; - output [ 7:0] fifo9_header_size; - output [15:0] fifo9_buffer_size; - - output fifoa_direction; - output [ 7:0] fifoa_header_size; - output [15:0] fifoa_buffer_size; - - input [31:0] length_fx32dma; - input [31:0] length_dma2fx3; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); // internal signals @@ -215,10 +137,6 @@ module axi_usb_fx3_reg ( // internal registers - reg [31:0] up_rdata = 32'h0; - reg up_rack = 1'b0; - reg up_wack = 1'b0; - reg [31:0] fifo0_config = 32'h0; reg [31:0] fifo1_config = 32'h0; reg [31:0] fifo2_config = 32'h0; diff --git a/library/common/ad_addsub.v b/library/common/ad_addsub.v index 86d5530e5..f6f7875d6 100644 --- a/library/common/ad_addsub.v +++ b/library/common/ad_addsub.v @@ -43,34 +43,23 @@ `timescale 1ns/1ps -module ad_addsub ( - clk, - A, - Amax, - out, - CE -); +module ad_addsub #( - // parameters + parameter A_DATA_WIDTH = 32, + parameter B_DATA_VALUE = 32'h1, + parameter ADD_OR_SUB_N = 0) ( + input clk, + input [(A_DATA_WIDTH-1):0] A, + input [(A_DATA_WIDTH-1):0] Amax, + output reg [(A_DATA_WIDTH-1):0] out, + input CE); - parameter A_DATA_WIDTH = 32; - parameter B_DATA_VALUE = 32'h1; - parameter ADD_OR_SUB_N = 0; localparam ADDER = 1; localparam SUBSTRACTER = 0; - // I/O definitions - - input clk; - input [(A_DATA_WIDTH-1):0] A; - input [(A_DATA_WIDTH-1):0] Amax; - output [(A_DATA_WIDTH-1):0] out; - input CE; - // registers - reg [(A_DATA_WIDTH-1):0] out = 'b0; reg [A_DATA_WIDTH:0] out_d = 'b0; reg [A_DATA_WIDTH:0] out_d2 = 'b0; reg [(A_DATA_WIDTH-1):0] A_d = 'b0; diff --git a/library/common/ad_axis_inf_rx.v b/library/common/ad_axis_inf_rx.v index d61a4b683..14afbd3a5 100644 --- a/library/common/ad_axis_inf_rx.v +++ b/library/common/ad_axis_inf_rx.v @@ -42,43 +42,27 @@ `timescale 1ns/100ps -module ad_axis_inf_rx ( +module ad_axis_inf_rx #( + + parameter DATA_WIDTH = 16) ( // adi interface - clk, - rst, - valid, - last, - data, + input clk, + input rst, + input valid, + input last, + input [DW:0] data, // xilinx interface - inf_valid, - inf_last, - inf_data, - inf_ready); + output reg inf_valid, + output reg inf_last, + output reg [DW:0] inf_data, + input inf_ready); - // parameter for data width - - parameter DATA_WIDTH = 16; localparam DW = DATA_WIDTH - 1; - // adi interface - - input clk; - input rst; - input valid; - input last; - input [DW:0] data; - - // xil interface - - output inf_valid; - output inf_last; - output [DW:0] inf_data; - input inf_ready; - // internal registers reg [ 2:0] wcnt = 'd0; @@ -99,9 +83,6 @@ module ad_axis_inf_rx ( reg wlast_7 = 'd0; reg [DW:0] wdata_7 = 'd0; reg [ 2:0] rcnt = 'd0; - reg inf_valid = 'd0; - reg inf_last = 'd0; - reg [DW:0] inf_data = 'd0; // internal signals diff --git a/library/common/ad_csc_1.v b/library/common/ad_csc_1.v index 7c141df5e..823e1cb3b 100644 --- a/library/common/ad_csc_1.v +++ b/library/common/ad_csc_1.v @@ -38,49 +38,30 @@ // *************************************************************************** // csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4; -module ad_csc_1 ( +module ad_csc_1 #( + + parameter DELAY_DATA_WIDTH = 16) ( // data - clk, - sync, - data, + input clk, + input [DW:0] sync, + input [23:0] data, // constants - C1, - C2, - C3, - C4, + input [16:0] C1, + input [16:0] C2, + input [16:0] C3, + input [24:0] C4, // sync is delay matched - csc_sync_1, - csc_data_1); + output [DW:0] csc_sync_1, + output [ 7:0] csc_data_1); - // parameters - - parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; - // data - - input clk; - input [DW:0] sync; - input [23:0] data; - - // constants - - input [16:0] C1; - input [16:0] C2; - input [16:0] C3; - input [24:0] C4; - - // sync is delay matched - - output [DW:0] csc_sync_1; - output [ 7:0] csc_data_1; - // internal wires wire [24:0] data_1_m_s; diff --git a/library/common/ad_csc_1_add.v b/library/common/ad_csc_1_add.v index f457cb360..8ec6eb4fc 100644 --- a/library/common/ad_csc_1_add.v +++ b/library/common/ad_csc_1_add.v @@ -42,41 +42,26 @@ `timescale 1ps/1ps -module ad_csc_1_add ( +module ad_csc_1_add #( + + parameter DELAY_DATA_WIDTH = 16) ( // all signed - clk, - data_1, - data_2, - data_3, - data_4, - data_p, + input clk, + input [24:0] data_1, + input [24:0] data_2, + input [24:0] data_3, + input [24:0] data_4, + output reg [ 7:0] data_p, // delay match - ddata_in, - ddata_out); + input [DW:0] ddata_in, + output reg [DW:0] ddata_out); - // parameters - - parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; - // all signed - - input clk; - input [24:0] data_1; - input [24:0] data_2; - input [24:0] data_3; - input [24:0] data_4; - output [ 7:0] data_p; - - // delay match - - input [DW:0] ddata_in; - output [DW:0] ddata_out; - // internal registers reg [DW:0] p1_ddata = 'd0; @@ -89,8 +74,6 @@ module ad_csc_1_add ( reg [24:0] p2_data_1 = 'd0; reg [DW:0] p3_ddata = 'd0; reg [24:0] p3_data = 'd0; - reg [DW:0] ddata_out = 'd0; - reg [ 7:0] data_p = 'd0; // internal signals diff --git a/library/common/ad_csc_1_mul.v b/library/common/ad_csc_1_mul.v index e92641a26..5384b08f7 100644 --- a/library/common/ad_csc_1_mul.v +++ b/library/common/ad_csc_1_mul.v @@ -41,42 +41,28 @@ `timescale 1ps/1ps -module ad_csc_1_mul ( +module ad_csc_1_mul #( + + parameter DELAY_DATA_WIDTH = 16) ( // data_a is signed - clk, - data_a, - data_b, - data_p, + input clk, + input [16:0] data_a, + input [ 7:0] data_b, + output [24:0] data_p, // delay match - ddata_in, - ddata_out); + input [DW:0] ddata_in, + output reg [DW:0] ddata_out); - // parameters - - parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; - // data_a is signed - - input clk; - input [16:0] data_a; - input [ 7:0] data_b; - output [24:0] data_p; - - // delay match - - input [DW:0] ddata_in; - output [DW:0] ddata_out; - // internal registers reg [DW:0] p1_ddata = 'd0; reg [DW:0] p2_ddata = 'd0; - reg [DW:0] ddata_out = 'd0; reg p1_sign = 'd0; reg p2_sign = 'd0; reg sign_p = 'd0; diff --git a/library/common/ad_csc_CrYCb2RGB.v b/library/common/ad_csc_CrYCb2RGB.v index 9b0219501..1cc4c71a5 100644 --- a/library/common/ad_csc_CrYCb2RGB.v +++ b/library/common/ad_csc_CrYCb2RGB.v @@ -43,35 +43,23 @@ // G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576); // B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836); -module ad_csc_CrYCb2RGB ( +module ad_csc_CrYCb2RGB #( + + parameter DELAY_DATA_WIDTH = 16) ( // Cr-Y-Cb inputs - clk, - CrYCb_sync, - CrYCb_data, + input clk, + input [DW:0] CrYCb_sync, + input [23:0] CrYCb_data, // R-G-B outputs - RGB_sync, - RGB_data); + output [DW:0] RGB_sync, + output [23:0] RGB_data); - // parameters - - parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; - // Cr-Y-Cb inputs - - input clk; - input [DW:0] CrYCb_sync; - input [23:0] CrYCb_data; - - // R-G-B outputs - - output [DW:0] RGB_sync; - output [23:0] RGB_data; - // red ad_csc_1 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_csc_1_R ( diff --git a/library/common/ad_csc_RGB2CrYCb.v b/library/common/ad_csc_RGB2CrYCb.v index d9018871e..646f96f15 100644 --- a/library/common/ad_csc_RGB2CrYCb.v +++ b/library/common/ad_csc_RGB2CrYCb.v @@ -43,35 +43,23 @@ // Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16; // Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128; -module ad_csc_RGB2CrYCb ( +module ad_csc_RGB2CrYCb #( + + parameter DELAY_DATA_WIDTH = 16) ( // R-G-B inputs - clk, - RGB_sync, - RGB_data, + input clk, + input [DW:0] RGB_sync, + input [23:0] RGB_data, // Cr-Y-Cb outputs - CrYCb_sync, - CrYCb_data); + output [DW:0] CrYCb_sync, + output [23:0] CrYCb_data); - // parameters - - parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; - // R-G-B inputs - - input clk; - input [DW:0] RGB_sync; - input [23:0] RGB_data; - - // Cr-Y-Cb outputs - - output [DW:0] CrYCb_sync; - output [23:0] CrYCb_data; - // Cr (red-diff) ad_csc_1 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_csc_1_Cr ( diff --git a/library/common/ad_dds_1.v b/library/common/ad_dds_1.v index bbce09f3d..8c77fd3f7 100644 --- a/library/common/ad_dds_1.v +++ b/library/common/ad_dds_1.v @@ -43,22 +43,13 @@ module ad_dds_1 ( // interface - clk, - angle, - scale, - dds_data); - - // interface - - input clk; - input [15:0] angle; - input [15:0] scale; - output [15:0] dds_data; + input clk, + input [15:0] angle, + input [15:0] scale, + output reg [15:0] dds_data); // internal registers - reg [15:0] dds_data = 'd0; - // internal signals wire [15:0] sine_s; diff --git a/library/common/ad_dds_sine.v b/library/common/ad_dds_sine.v index 2c8f7cca4..92969af4d 100644 --- a/library/common/ad_dds_sine.v +++ b/library/common/ad_dds_sine.v @@ -41,29 +41,20 @@ `timescale 1ns/100ps -module ad_dds_sine ( +module ad_dds_sine #( + + parameter DELAY_DATA_WIDTH = 16) ( // sine = sin(angle) - clk, - angle, - sine, - ddata_in, - ddata_out); + input clk, + input [ 15:0] angle, + output reg [ 15:0] sine, + input [ DW:0] ddata_in, + output reg [ DW:0] ddata_out); - // parameters - - parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; - // sine = sin(angle) - - input clk; - input [ 15:0] angle; - output [ 15:0] sine; - input [ DW:0] ddata_in; - output [ DW:0] ddata_out; - // internal registers reg [ 33:0] s1_data_p = 'd0; @@ -89,8 +80,6 @@ module ad_dds_sine ( reg [ DW:0] s6_ddata = 'd0; reg [ 33:0] s7_data = 'd0; reg [ DW:0] s7_ddata = 'd0; - reg [ 15:0] sine = 'd0; - reg [ DW:0] ddata_out = 'd0; // internal signals diff --git a/library/common/ad_edge_detect.v b/library/common/ad_edge_detect.v index 6c15454b4..be4be0340 100644 --- a/library/common/ad_edge_detect.v +++ b/library/common/ad_edge_detect.v @@ -41,32 +41,24 @@ `timescale 1ns/100ps -module ad_edge_detect ( +module ad_edge_detect #( - clk, - rst, + parameter EDGE = 0) ( - in, - out -); + input clk, + input rst, + + input in, + output reg out); - parameter EDGE = 0; localparam POS_EDGE = 0; localparam NEG_EDGE = 1; localparam ANY_EDGE = 2; - input clk; - input rst; - - input in; - output out; - reg ff_m1 = 0; reg ff_m2 = 0; - reg out = 0; - always @(posedge clk) begin if (rst == 1) begin ff_m1 <= 0; diff --git a/library/common/ad_gt_channel.v b/library/common/ad_gt_channel.v index fb25593b9..d59aca637 100644 --- a/library/common/ad_gt_channel.v +++ b/library/common/ad_gt_channel.v @@ -37,146 +37,82 @@ `timescale 1ns/1ps -module ad_gt_channel ( +module ad_gt_channel #( + + parameter integer GTH_OR_GTX_N = 0, + parameter [31:0] PMA_RSV = 32'h00018480, + parameter integer CPLL_FBDIV = 2, + parameter integer RX_OUT_DIV = 1, + parameter integer RX_CLK25_DIV = 10, + parameter integer RX_CLKBUF_ENABLE = 0, + parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020, + parameter integer TX_OUT_DIV = 1, + parameter integer TX_CLK25_DIV = 10, + parameter integer TX_CLKBUF_ENABLE = 0) ( // rst and clocks - lpm_dfe_n, - cpll_ref_clk_in, - cpll_pd, - cpll_rst, - qpll_clk, - qpll_ref_clk, - qpll_locked, + input lpm_dfe_n, + input cpll_ref_clk_in, + input cpll_pd, + input cpll_rst, + input qpll_clk, + input qpll_ref_clk, + input qpll_locked, // receive - rx_gt_rst_m, - rx_p, - rx_n, + input rx_gt_rst_m, + input rx_p, + input rx_n, - rx_sys_clk_sel, - rx_out_clk_sel, - rx_out_clk, - rx_rst_done, - rx_pll_locked, - rx_user_ready_m, + input [ 1:0] rx_sys_clk_sel, + input [ 2:0] rx_out_clk_sel, + output rx_out_clk, + output rx_rst_done, + output rx_pll_locked, + input rx_user_ready_m, - rx_clk, - rx_gt_charisk, - rx_gt_disperr, - rx_gt_notintable, - rx_gt_data, - rx_gt_comma_align_enb, - rx_gt_ilas_f, - rx_gt_ilas_q, - rx_gt_ilas_a, - rx_gt_ilas_r, - rx_gt_cgs_k, + input rx_clk, + output [ 3:0] rx_gt_charisk, + output [ 3:0] rx_gt_disperr, + output [ 3:0] rx_gt_notintable, + output [31:0] rx_gt_data, + input rx_gt_comma_align_enb, + output [ 3:0] rx_gt_ilas_f, + output [ 3:0] rx_gt_ilas_q, + output [ 3:0] rx_gt_ilas_a, + output [ 3:0] rx_gt_ilas_r, + output [ 3:0] rx_gt_cgs_k, // transmit - tx_gt_rst_m, - tx_p, - tx_n, + input tx_gt_rst_m, + output tx_p, + output tx_n, - tx_sys_clk_sel, - tx_out_clk_sel, - tx_out_clk, - tx_rst_done, - tx_pll_locked, - tx_user_ready_m, + input [ 1:0] tx_sys_clk_sel, + input [ 2:0] tx_out_clk_sel, + output tx_out_clk, + output tx_rst_done, + output tx_pll_locked, + input tx_user_ready_m, - tx_clk, - tx_gt_charisk, - tx_gt_data, + input tx_clk, + input [ 3:0] tx_gt_charisk, + input [31:0] tx_gt_data, // drp interface - up_clk, - up_drp_sel, - up_drp_addr, - up_drp_wr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_rxrate); + input up_clk, + input up_drp_sel, + input [11:0] up_drp_addr, + input up_drp_wr, + input [15:0] up_drp_wdata, + output [15:0] up_drp_rdata, + output up_drp_ready, + output [ 7:0] up_drp_rxrate); - // parameters - - parameter integer GTH_OR_GTX_N = 0; - parameter [31:0] PMA_RSV = 32'h00018480; - parameter integer CPLL_FBDIV = 2; - parameter integer RX_OUT_DIV = 1; - parameter integer RX_CLK25_DIV = 10; - parameter integer RX_CLKBUF_ENABLE = 0; - parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020; - parameter integer TX_OUT_DIV = 1; - parameter integer TX_CLK25_DIV = 10; - parameter integer TX_CLKBUF_ENABLE = 0; - - // rst and clocks - - input lpm_dfe_n; - input cpll_ref_clk_in; - input cpll_pd; - input cpll_rst; - input qpll_clk; - input qpll_ref_clk; - input qpll_locked; - - // receive - - input rx_gt_rst_m; - input rx_p; - input rx_n; - - input [ 1:0] rx_sys_clk_sel; - input [ 2:0] rx_out_clk_sel; - output rx_out_clk; - output rx_rst_done; - output rx_pll_locked; - input rx_user_ready_m; - - input rx_clk; - output [ 3:0] rx_gt_charisk; - output [ 3:0] rx_gt_disperr; - output [ 3:0] rx_gt_notintable; - output [31:0] rx_gt_data; - input rx_gt_comma_align_enb; - output [ 3:0] rx_gt_ilas_f; - output [ 3:0] rx_gt_ilas_q; - output [ 3:0] rx_gt_ilas_a; - output [ 3:0] rx_gt_ilas_r; - output [ 3:0] rx_gt_cgs_k; - - // transmit - - input tx_gt_rst_m; - output tx_p; - output tx_n; - - input [ 1:0] tx_sys_clk_sel; - input [ 2:0] tx_out_clk_sel; - output tx_out_clk; - output tx_rst_done; - output tx_pll_locked; - input tx_user_ready_m; - - input tx_clk; - input [ 3:0] tx_gt_charisk; - input [31:0] tx_gt_data; - - // drp interface - - input up_clk; - input up_drp_sel; - input [11:0] up_drp_addr; - input up_drp_wr; - input [15:0] up_drp_wdata; - output [15:0] up_drp_rdata; - output up_drp_ready; - output [ 7:0] up_drp_rxrate; // internal signals diff --git a/library/common/ad_gt_channel_1.v b/library/common/ad_gt_channel_1.v index fb6bcd0b6..8cb60977b 100644 --- a/library/common/ad_gt_channel_1.v +++ b/library/common/ad_gt_channel_1.v @@ -37,231 +37,125 @@ `timescale 1ns/1ps -module ad_gt_channel_1 ( +module ad_gt_channel_1 #( + + parameter integer ID = 0, + parameter integer GTH_OR_GTX_N = 0, + parameter [31:0] PMA_RSV = 32'h00018480, + parameter integer CPLL_FBDIV = 2, + parameter integer RX_OUT_DIV = 1, + parameter integer RX_CLK25_DIV = 10, + parameter integer RX_CLKBUF_ENABLE = 0, + parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020, + parameter integer TX_OUT_DIV = 1, + parameter integer TX_CLK25_DIV = 10, + parameter integer TX_CLKBUF_ENABLE = 0) ( // channel interface (pll) - cpll_rst_m, - cpll_ref_clk_in, - qpll_ref_clk, - qpll_locked, - qpll_clk, + input cpll_rst_m, + input cpll_ref_clk_in, + input qpll_ref_clk, + input qpll_locked, + input qpll_clk, // channel interface (rx) - rx_p, - rx_n, + input rx_p, + input rx_n, - rx_out_clk, - rx_clk, - rx_rst, - rx_rst_m, - rx_sof, - rx_data, - rx_sysref, - rx_sync, + output rx_out_clk, + input rx_clk, + output rx_rst, + input rx_rst_m, + output rx_sof, + output [31:0] rx_data, + input rx_sysref, + output rx_sync, - rx_pll_rst, - rx_gt_rst, - rx_gt_rst_m, - rx_gt_charisk, - rx_gt_disperr, - rx_gt_notintable, - rx_gt_data, - rx_gt_comma_align_enb, - rx_gt_ilas_f, - rx_gt_ilas_q, - rx_gt_ilas_a, - rx_gt_ilas_r, - rx_gt_cgs_k, + output rx_pll_rst, + output rx_gt_rst, + input rx_gt_rst_m, + output [ 3:0] rx_gt_charisk, + output [ 3:0] rx_gt_disperr, + output [ 3:0] rx_gt_notintable, + output [31:0] rx_gt_data, + input rx_gt_comma_align_enb, + output [ 3:0] rx_gt_ilas_f, + output [ 3:0] rx_gt_ilas_q, + output [ 3:0] rx_gt_ilas_a, + output [ 3:0] rx_gt_ilas_r, + output [ 3:0] rx_gt_cgs_k, - rx_ip_rst, - rx_ip_sof, - rx_ip_data, - rx_ip_sysref, - rx_ip_sync, - rx_ip_rst_done, + output rx_ip_rst, + input [ 3:0] rx_ip_sof, + input [31:0] rx_ip_data, + output rx_ip_sysref, + input rx_ip_sync, + output rx_ip_rst_done, - rx_pll_locked, - rx_user_ready, - rx_rst_done, + output rx_pll_locked, + output rx_user_ready, + output rx_rst_done, - rx_pll_locked_m, - rx_user_ready_m, - rx_rst_done_m, + input rx_pll_locked_m, + input rx_user_ready_m, + input rx_rst_done_m, // channel interface (tx) - tx_p, - tx_n, + output tx_p, + output tx_n, - tx_out_clk, - tx_clk, - tx_rst, - tx_rst_m, - tx_data, - tx_sysref, - tx_sync, + output tx_out_clk, + input tx_clk, + output tx_rst, + input tx_rst_m, + input [31:0] tx_data, + input tx_sysref, + input tx_sync, - tx_pll_rst, - tx_gt_rst, - tx_gt_rst_m, - tx_gt_charisk, - tx_gt_data, + output tx_pll_rst, + output tx_gt_rst, + input tx_gt_rst_m, + input [ 3:0] tx_gt_charisk, + input [31:0] tx_gt_data, - tx_ip_rst, - tx_ip_data, - tx_ip_sysref, - tx_ip_sync, - tx_ip_rst_done, + output tx_ip_rst, + output [31:0] tx_ip_data, + output tx_ip_sysref, + output tx_ip_sync, + output tx_ip_rst_done, - tx_pll_locked, - tx_user_ready, - tx_rst_done, + output tx_pll_locked, + output tx_user_ready, + output tx_rst_done, - tx_pll_locked_m, - tx_user_ready_m, - tx_rst_done_m, + input tx_pll_locked_m, + input tx_user_ready_m, + input tx_rst_done_m, // dma interface - up_es_dma_req, - up_es_dma_addr, - up_es_dma_data, - up_es_dma_ack, - up_es_dma_err, + output up_es_dma_req, + output [31:0] up_es_dma_addr, + output [31:0] up_es_dma_data, + input up_es_dma_ack, + input up_es_dma_err, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter integer ID = 0; - parameter integer GTH_OR_GTX_N = 0; - parameter [31:0] PMA_RSV = 32'h00018480; - parameter integer CPLL_FBDIV = 2; - parameter integer RX_OUT_DIV = 1; - parameter integer RX_CLK25_DIV = 10; - parameter integer RX_CLKBUF_ENABLE = 0; - parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020; - parameter integer TX_OUT_DIV = 1; - parameter integer TX_CLK25_DIV = 10; - parameter integer TX_CLKBUF_ENABLE = 0; - - // channel interface (pll) - - input cpll_rst_m; - input cpll_ref_clk_in; - input qpll_ref_clk; - input qpll_locked; - input qpll_clk; - - // channel interface (rx) - - input rx_p; - input rx_n; - - output rx_out_clk; - input rx_clk; - output rx_rst; - input rx_rst_m; - output rx_sof; - output [31:0] rx_data; - input rx_sysref; - output rx_sync; - - output rx_pll_rst; - output rx_gt_rst; - input rx_gt_rst_m; - output [ 3:0] rx_gt_charisk; - output [ 3:0] rx_gt_disperr; - output [ 3:0] rx_gt_notintable; - output [31:0] rx_gt_data; - input rx_gt_comma_align_enb; - output [ 3:0] rx_gt_ilas_f; - output [ 3:0] rx_gt_ilas_q; - output [ 3:0] rx_gt_ilas_a; - output [ 3:0] rx_gt_ilas_r; - output [ 3:0] rx_gt_cgs_k; - - output rx_ip_rst; - input [ 3:0] rx_ip_sof; - input [31:0] rx_ip_data; - output rx_ip_sysref; - input rx_ip_sync; - output rx_ip_rst_done; - - output rx_pll_locked; - output rx_user_ready; - output rx_rst_done; - - input rx_pll_locked_m; - input rx_user_ready_m; - input rx_rst_done_m; - - // channel interface (tx) - - output tx_p; - output tx_n; - - output tx_out_clk; - input tx_clk; - output tx_rst; - input tx_rst_m; - input [31:0] tx_data; - input tx_sysref; - input tx_sync; - - output tx_pll_rst; - output tx_gt_rst; - input tx_gt_rst_m; - input [ 3:0] tx_gt_charisk; - input [31:0] tx_gt_data; - - output tx_ip_rst; - output [31:0] tx_ip_data; - output tx_ip_sysref; - output tx_ip_sync; - output tx_ip_rst_done; - - output tx_pll_locked; - output tx_user_ready; - output tx_rst_done; - - input tx_pll_locked_m; - input tx_user_ready_m; - input tx_rst_done_m; - - // dma interface - - output up_es_dma_req; - output [31:0] up_es_dma_addr; - output [31:0] up_es_dma_data; - input up_es_dma_ack; - input up_es_dma_err; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/common/ad_gt_common.v b/library/common/ad_gt_common.v index a01f2afbe..f8349ccea 100644 --- a/library/common/ad_gt_common.v +++ b/library/common/ad_gt_common.v @@ -37,52 +37,33 @@ `timescale 1ns/1ps -module ad_gt_common ( +module ad_gt_common #( + + parameter integer GTH_OR_GTX_N = 0, + parameter integer QPLL_ENABLE = 1, + parameter integer QPLL_REFCLK_DIV = 2, + parameter [26:0] QPLL_CFG = 27'h06801C1, + parameter integer QPLL_FBDIV_RATIO = 1'b1, + parameter [ 9:0] QPLL_FBDIV = 10'b0000110000) ( // reset and clocks - qpll_ref_clk_in, - qpll_rst, - qpll_clk, - qpll_ref_clk, - qpll_locked, + input qpll_ref_clk_in, + input qpll_rst, + output qpll_clk, + output qpll_ref_clk, + output qpll_locked, // drp interface - up_clk, - up_drp_sel, - up_drp_addr, - up_drp_wr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready); + input up_clk, + input up_drp_sel, + input [11:0] up_drp_addr, + input up_drp_wr, + input [15:0] up_drp_wdata, + output [15:0] up_drp_rdata, + output up_drp_ready); - // parameters - - parameter integer GTH_OR_GTX_N = 0; - parameter integer QPLL_ENABLE = 1; - parameter integer QPLL_REFCLK_DIV = 2; - parameter [26:0] QPLL_CFG = 27'h06801C1; - parameter integer QPLL_FBDIV_RATIO = 1'b1; - parameter [ 9:0] QPLL_FBDIV = 10'b0000110000; - - // reset and clocks - - input qpll_ref_clk_in; - input qpll_rst; - output qpll_clk; - output qpll_ref_clk; - output qpll_locked; - - // drp interface - - input up_clk; - input up_drp_sel; - input [11:0] up_drp_addr; - input up_drp_wr; - input [15:0] up_drp_wdata; - output [15:0] up_drp_rdata; - output up_drp_ready; // instantiations diff --git a/library/common/ad_gt_common_1.v b/library/common/ad_gt_common_1.v index ae123af78..5cf08b5fe 100644 --- a/library/common/ad_gt_common_1.v +++ b/library/common/ad_gt_common_1.v @@ -37,70 +37,45 @@ `timescale 1ns/1ps -module ad_gt_common_1 ( +module ad_gt_common_1 #( + + parameter integer ID = 0, + parameter integer GTH_OR_GTX_N = 0, + parameter integer QPLL0_ENABLE = 1, + parameter integer QPLL0_REFCLK_DIV = 2, + parameter [26:0] QPLL0_CFG = 27'h06801C1, + parameter integer QPLL0_FBDIV_RATIO = 1'b1, + parameter [ 9:0] QPLL0_FBDIV = 10'b0000110000, + parameter integer QPLL1_ENABLE = 1, + parameter integer QPLL1_REFCLK_DIV = 2, + parameter [26:0] QPLL1_CFG = 27'h06801C1, + parameter integer QPLL1_FBDIV_RATIO = 1'b1, + parameter [ 9:0] QPLL1_FBDIV = 10'b0000110000) ( // reset and clocks - qpll0_rst, - qpll0_ref_clk_in, - qpll1_rst, - qpll1_ref_clk_in, + input qpll0_rst, + input qpll0_ref_clk_in, + input qpll1_rst, + input qpll1_ref_clk_in, - qpll_clk, - qpll_ref_clk, - qpll_locked, + output [ 7:0] qpll_clk, + output [ 7:0] qpll_ref_clk, + output [ 7:0] qpll_locked, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); - // parameters - - parameter integer ID = 0; - parameter integer GTH_OR_GTX_N = 0; - parameter integer QPLL0_ENABLE = 1; - parameter integer QPLL0_REFCLK_DIV = 2; - parameter [26:0] QPLL0_CFG = 27'h06801C1; - parameter integer QPLL0_FBDIV_RATIO = 1'b1; - parameter [ 9:0] QPLL0_FBDIV = 10'b0000110000; - parameter integer QPLL1_ENABLE = 1; - parameter integer QPLL1_REFCLK_DIV = 2; - parameter [26:0] QPLL1_CFG = 27'h06801C1; - parameter integer QPLL1_FBDIV_RATIO = 1'b1; - parameter [ 9:0] QPLL1_FBDIV = 10'b0000110000; - - // reset and clocks - - input qpll0_rst; - input qpll0_ref_clk_in; - input qpll1_rst; - input qpll1_ref_clk_in; - - output [ 7:0] qpll_clk; - output [ 7:0] qpll_ref_clk; - output [ 7:0] qpll_locked; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal signals diff --git a/library/common/ad_gt_es.v b/library/common/ad_gt_es.v index a8ecc4d09..340727fcb 100644 --- a/library/common/ad_gt_es.v +++ b/library/common/ad_gt_es.v @@ -37,59 +37,56 @@ `timescale 1ns/100ps -module ad_gt_es ( +module ad_gt_es #( - lpm_dfe_n, + parameter integer GTH_OR_GTX_N = 0) ( + + input lpm_dfe_n, // drp interface - up_rstn, - up_clk, - up_es_drp_sel, - up_es_drp_wr, - up_es_drp_addr, - up_es_drp_wdata, - up_es_drp_rdata, - up_es_drp_ready, + input up_rstn, + input up_clk, + output reg up_es_drp_sel, + output reg up_es_drp_wr, + output reg [11:0] up_es_drp_addr, + output reg [15:0] up_es_drp_wdata, + input [15:0] up_es_drp_rdata, + input up_es_drp_ready, // dma interface - up_es_dma_req, - up_es_dma_addr, - up_es_dma_data, - up_es_dma_ack, + output reg up_es_dma_req, + output reg [31:0] up_es_dma_addr, + output reg [31:0] up_es_dma_data, + input up_es_dma_ack, // processor interface - up_es_start, - up_es_stop, - up_es_init, - up_es_sdata0, - up_es_sdata1, - up_es_sdata2, - up_es_sdata3, - up_es_sdata4, - up_es_qdata0, - up_es_qdata1, - up_es_qdata2, - up_es_qdata3, - up_es_qdata4, - up_es_prescale, - up_es_hoffset_min, - up_es_hoffset_max, - up_es_hoffset_step, - up_es_voffset_min, - up_es_voffset_max, - up_es_voffset_step, - up_es_voffset_range, - up_es_start_addr, - up_es_status); + input up_es_start, + input up_es_stop, + input up_es_init, + input [15:0] up_es_sdata0, + input [15:0] up_es_sdata1, + input [15:0] up_es_sdata2, + input [15:0] up_es_sdata3, + input [15:0] up_es_sdata4, + input [15:0] up_es_qdata0, + input [15:0] up_es_qdata1, + input [15:0] up_es_qdata2, + input [15:0] up_es_qdata3, + input [15:0] up_es_qdata4, + input [ 4:0] up_es_prescale, + input [11:0] up_es_hoffset_min, + input [11:0] up_es_hoffset_max, + input [11:0] up_es_hoffset_step, + input [ 7:0] up_es_voffset_min, + input [ 7:0] up_es_voffset_max, + input [ 7:0] up_es_voffset_step, + input [ 1:0] up_es_voffset_range, + input [31:0] up_es_start_addr, + output reg up_es_status); - // parameters - - parameter integer GTH_OR_GTX_N = 0; - - // gt address localparam [11:0] ES_DRP_CTRL_ADDR = (GTH_OR_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d localparam [11:0] ES_DRP_SDATA0_ADDR = (GTH_OR_GTX_N == 1) ? 12'h049 : 12'h036; // GTH-7 12'h036 @@ -108,8 +105,6 @@ module ad_gt_es ( localparam [11:0] ES_DRP_SCNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152 localparam [11:0] ES_DRP_ECNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151 - // state machine - localparam [ 5:0] ES_FSM_IDLE = 6'h00; localparam [ 5:0] ES_FSM_STATUS = 6'h01; localparam [ 5:0] ES_FSM_INIT = 6'h02; @@ -163,58 +158,8 @@ module ad_gt_es ( localparam [ 5:0] ES_FSM_DMA_READY = 6'h32; localparam [ 5:0] ES_FSM_UPDATE = 6'h33; - input lpm_dfe_n; - - // drp interface - - input up_rstn; - input up_clk; - output up_es_drp_sel; - output up_es_drp_wr; - output [11:0] up_es_drp_addr; - output [15:0] up_es_drp_wdata; - input [15:0] up_es_drp_rdata; - input up_es_drp_ready; - - // dma interface - - output up_es_dma_req; - output [31:0] up_es_dma_addr; - output [31:0] up_es_dma_data; - input up_es_dma_ack; - - // processor interface - - input up_es_start; - input up_es_stop; - input up_es_init; - input [15:0] up_es_sdata0; - input [15:0] up_es_sdata1; - input [15:0] up_es_sdata2; - input [15:0] up_es_sdata3; - input [15:0] up_es_sdata4; - input [15:0] up_es_qdata0; - input [15:0] up_es_qdata1; - input [15:0] up_es_qdata2; - input [15:0] up_es_qdata3; - input [15:0] up_es_qdata4; - input [ 4:0] up_es_prescale; - input [11:0] up_es_hoffset_min; - input [11:0] up_es_hoffset_max; - input [11:0] up_es_hoffset_step; - input [ 7:0] up_es_voffset_min; - input [ 7:0] up_es_voffset_max; - input [ 7:0] up_es_voffset_step; - input [ 1:0] up_es_voffset_range; - input [31:0] up_es_start_addr; - output up_es_status; - // internal registers - reg up_es_dma_req = 'd0; - reg [31:0] up_es_dma_addr = 'd0; - reg [31:0] up_es_dma_data = 'd0; - reg up_es_status = 'd0; reg up_es_ut = 'd0; reg [31:0] up_es_addr = 'd0; reg [11:0] up_es_hoffset = 'd0; @@ -225,10 +170,6 @@ module ad_gt_es ( reg [15:0] up_es_scnt_rdata = 'd0; reg [15:0] up_es_ecnt_rdata = 'd0; reg [ 5:0] up_es_fsm = 'd0; - reg up_es_drp_sel = 'd0; - reg up_es_drp_wr = 'd0; - reg [11:0] up_es_drp_addr = 'd0; - reg [15:0] up_es_drp_wdata = 'd0; // internal signals diff --git a/library/common/ad_gt_es_axi.v b/library/common/ad_gt_es_axi.v index 0fb54acc4..9230c4fab 100644 --- a/library/common/ad_gt_es_axi.v +++ b/library/common/ad_gt_es_axi.v @@ -41,72 +41,70 @@ module ad_gt_es_axi ( // es interface - up_rstn, - up_clk, - up_es_dma_req_0, - up_es_dma_addr_0, - up_es_dma_data_0, - up_es_dma_ack_0, - up_es_dma_err_0, - up_es_dma_req_1, - up_es_dma_addr_1, - up_es_dma_data_1, - up_es_dma_ack_1, - up_es_dma_err_1, - up_es_dma_req_2, - up_es_dma_addr_2, - up_es_dma_data_2, - up_es_dma_ack_2, - up_es_dma_err_2, - up_es_dma_req_3, - up_es_dma_addr_3, - up_es_dma_data_3, - up_es_dma_ack_3, - up_es_dma_err_3, - up_es_dma_req_4, - up_es_dma_addr_4, - up_es_dma_data_4, - up_es_dma_ack_4, - up_es_dma_err_4, - up_es_dma_req_5, - up_es_dma_addr_5, - up_es_dma_data_5, - up_es_dma_ack_5, - up_es_dma_err_5, - up_es_dma_req_6, - up_es_dma_addr_6, - up_es_dma_data_6, - up_es_dma_ack_6, - up_es_dma_err_6, - up_es_dma_req_7, - up_es_dma_addr_7, - up_es_dma_data_7, - up_es_dma_ack_7, - up_es_dma_err_7, + input up_rstn, + input up_clk, + input up_es_dma_req_0, + input [31:0] up_es_dma_addr_0, + input [31:0] up_es_dma_data_0, + output reg up_es_dma_ack_0, + output reg up_es_dma_err_0, + input up_es_dma_req_1, + input [31:0] up_es_dma_addr_1, + input [31:0] up_es_dma_data_1, + output reg up_es_dma_ack_1, + output reg up_es_dma_err_1, + input up_es_dma_req_2, + input [31:0] up_es_dma_addr_2, + input [31:0] up_es_dma_data_2, + output reg up_es_dma_ack_2, + output reg up_es_dma_err_2, + input up_es_dma_req_3, + input [31:0] up_es_dma_addr_3, + input [31:0] up_es_dma_data_3, + output reg up_es_dma_ack_3, + output reg up_es_dma_err_3, + input up_es_dma_req_4, + input [31:0] up_es_dma_addr_4, + input [31:0] up_es_dma_data_4, + output reg up_es_dma_ack_4, + output reg up_es_dma_err_4, + input up_es_dma_req_5, + input [31:0] up_es_dma_addr_5, + input [31:0] up_es_dma_data_5, + output reg up_es_dma_ack_5, + output reg up_es_dma_err_5, + input up_es_dma_req_6, + input [31:0] up_es_dma_addr_6, + input [31:0] up_es_dma_data_6, + output reg up_es_dma_ack_6, + output reg up_es_dma_err_6, + input up_es_dma_req_7, + input [31:0] up_es_dma_addr_7, + input [31:0] up_es_dma_data_7, + output reg up_es_dma_ack_7, + output reg up_es_dma_err_7, // axi4 interface - axi_awvalid, - axi_awaddr, - axi_awprot, - axi_awready, - axi_wvalid, - axi_wdata, - axi_wstrb, - axi_wready, - axi_bvalid, - axi_bresp, - axi_bready, - axi_arvalid, - axi_araddr, - axi_arprot, - axi_arready, - axi_rvalid, - axi_rresp, - axi_rdata, - axi_rready); - - // state machine (fair RR?) + output reg axi_awvalid, + output reg [31:0] axi_awaddr, + output [ 2:0] axi_awprot, + input axi_awready, + output reg axi_wvalid, + output reg [31:0] axi_wdata, + output [ 3:0] axi_wstrb, + input axi_wready, + input axi_bvalid, + input [ 1:0] axi_bresp, + output axi_bready, + output axi_arvalid, + output [31:0] axi_araddr, + output [ 2:0] axi_arprot, + input axi_arready, + input axi_rvalid, + input [ 1:0] axi_rresp, + input [31:0] axi_rdata, + output axi_rready); localparam [ 3:0] AXI_FSM_SCAN_0 = 4'h0; localparam [ 3:0] AXI_FSM_SCAN_1 = 4'h1; @@ -120,95 +118,8 @@ module ad_gt_es_axi ( localparam [ 3:0] AXI_FSM_WAIT = 4'h9; localparam [ 3:0] AXI_FSM_ACK = 4'ha; - // es interface - - input up_rstn; - input up_clk; - input up_es_dma_req_0; - input [31:0] up_es_dma_addr_0; - input [31:0] up_es_dma_data_0; - output up_es_dma_ack_0; - output up_es_dma_err_0; - input up_es_dma_req_1; - input [31:0] up_es_dma_addr_1; - input [31:0] up_es_dma_data_1; - output up_es_dma_ack_1; - output up_es_dma_err_1; - input up_es_dma_req_2; - input [31:0] up_es_dma_addr_2; - input [31:0] up_es_dma_data_2; - output up_es_dma_ack_2; - output up_es_dma_err_2; - input up_es_dma_req_3; - input [31:0] up_es_dma_addr_3; - input [31:0] up_es_dma_data_3; - output up_es_dma_ack_3; - output up_es_dma_err_3; - input up_es_dma_req_4; - input [31:0] up_es_dma_addr_4; - input [31:0] up_es_dma_data_4; - output up_es_dma_ack_4; - output up_es_dma_err_4; - input up_es_dma_req_5; - input [31:0] up_es_dma_addr_5; - input [31:0] up_es_dma_data_5; - output up_es_dma_ack_5; - output up_es_dma_err_5; - input up_es_dma_req_6; - input [31:0] up_es_dma_addr_6; - input [31:0] up_es_dma_data_6; - output up_es_dma_ack_6; - output up_es_dma_err_6; - input up_es_dma_req_7; - input [31:0] up_es_dma_addr_7; - input [31:0] up_es_dma_data_7; - output up_es_dma_ack_7; - output up_es_dma_err_7; - - // axi4 interface - - output axi_awvalid; - output [31:0] axi_awaddr; - output [ 2:0] axi_awprot; - input axi_awready; - output axi_wvalid; - output [31:0] axi_wdata; - output [ 3:0] axi_wstrb; - input axi_wready; - input axi_bvalid; - input [ 1:0] axi_bresp; - output axi_bready; - output axi_arvalid; - output [31:0] axi_araddr; - output [ 2:0] axi_arprot; - input axi_arready; - input axi_rvalid; - input [31:0] axi_rdata; - input [ 1:0] axi_rresp; - output axi_rready; - // internal registers - reg up_es_dma_ack_0 = 'd0; - reg up_es_dma_err_0 = 'd0; - reg up_es_dma_ack_1 = 'd0; - reg up_es_dma_err_1 = 'd0; - reg up_es_dma_ack_2 = 'd0; - reg up_es_dma_err_2 = 'd0; - reg up_es_dma_ack_3 = 'd0; - reg up_es_dma_err_3 = 'd0; - reg up_es_dma_ack_4 = 'd0; - reg up_es_dma_err_4 = 'd0; - reg up_es_dma_ack_5 = 'd0; - reg up_es_dma_err_5 = 'd0; - reg up_es_dma_ack_6 = 'd0; - reg up_es_dma_err_6 = 'd0; - reg up_es_dma_ack_7 = 'd0; - reg up_es_dma_err_7 = 'd0; - reg axi_awvalid = 'd0; - reg [31:0] axi_awaddr = 'd0; - reg axi_wvalid = 'd0; - reg [31:0] axi_wdata = 'd0; reg axi_error = 'd0; reg [ 2:0] axi_sel = 'd0; reg [ 3:0] axi_fsm = 'd0; diff --git a/library/common/ad_jesd_align.v b/library/common/ad_jesd_align.v index 1505880e1..acf770ecf 100644 --- a/library/common/ad_jesd_align.v +++ b/library/common/ad_jesd_align.v @@ -41,30 +41,17 @@ module ad_jesd_align ( // jesd interface - rx_clk, - rx_ip_sof, - rx_ip_data, - rx_sof, - rx_data); - - // jesd interface - - input rx_clk; - input [ 3:0] rx_ip_sof; - input [31:0] rx_ip_data; - - // aligned data - - output rx_sof; - output [31:0] rx_data; + input rx_clk, + input [ 3:0] rx_ip_sof, + input [31:0] rx_ip_data, + output reg rx_sof, + output reg [31:0] rx_data); // internal registers reg [31:0] rx_ip_data_d = 'd0; reg [ 3:0] rx_ip_sof_hold = 'd0; - reg rx_sof = 'd0; reg rx_ip_sof_d = 'd0; - reg [31:0] rx_data = 'd0; // dword may contain more than one frame per clock diff --git a/library/common/ad_mem.v b/library/common/ad_mem.v index a06be19b3..5ea95dd54 100644 --- a/library/common/ad_mem.v +++ b/library/common/ad_mem.v @@ -39,34 +39,25 @@ `timescale 1ns/100ps -module ad_mem ( +module ad_mem #( - clka, - wea, - addra, - dina, + parameter DATA_WIDTH = 16, + parameter ADDRESS_WIDTH = 5) ( - clkb, - addrb, - doutb); + input clka, + input wea, + input [AW:0] addra, + input [DW:0] dina, + + input clkb, + input [AW:0] addrb, + output reg [DW:0] doutb); - parameter DATA_WIDTH = 16; - parameter ADDRESS_WIDTH = 5; localparam DW = DATA_WIDTH - 1; localparam AW = ADDRESS_WIDTH - 1; - input clka; - input wea; - input [AW:0] addra; - input [DW:0] dina; - - input clkb; - input [AW:0] addrb; - output [DW:0] doutb; - (* ram_style = "block" *) reg [DW:0] m_ram[0:((2**ADDRESS_WIDTH)-1)]; - reg [DW:0] doutb; always @(posedge clka) begin if (wea == 1'b1) begin diff --git a/library/common/ad_mem_asym.v b/library/common/ad_mem_asym.v index eb86ab21c..1a62bf952 100644 --- a/library/common/ad_mem_asym.v +++ b/library/common/ad_mem_asym.v @@ -42,46 +42,32 @@ `timescale 1ns/100ps -module ad_mem_asym ( +module ad_mem_asym #( - clka, - wea, - addra, - dina, + parameter A_ADDRESS_WIDTH = 8, + parameter A_DATA_WIDTH = 256, + parameter B_ADDRESS_WIDTH = 10, + parameter B_DATA_WIDTH = 64) ( - clkb, - addrb, - doutb); + input clka, + input wea, + input [A_ADDRESS_WIDTH-1:0] addra, + input [A_DATA_WIDTH-1:0] dina, + + input clkb, + input [B_ADDRESS_WIDTH-1:0] addrb, + output reg [B_DATA_WIDTH-1:0] doutb); - parameter A_ADDRESS_WIDTH = 8; - parameter A_DATA_WIDTH = 256; - parameter B_ADDRESS_WIDTH = 10; - parameter B_DATA_WIDTH = 64; localparam MEM_ADDRESS_WIDTH = (A_ADDRESS_WIDTH > B_ADDRESS_WIDTH) ? A_ADDRESS_WIDTH : B_ADDRESS_WIDTH; localparam MEM_DATA_WIDTH = (A_DATA_WIDTH > B_DATA_WIDTH) ? B_DATA_WIDTH : A_DATA_WIDTH; localparam MEM_SIZE = 2 ** MEM_ADDRESS_WIDTH; - // suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1 localparam MEM_RATIO = (A_DATA_WIDTH > B_DATA_WIDTH) ? A_DATA_WIDTH/B_DATA_WIDTH : B_DATA_WIDTH/A_DATA_WIDTH; localparam MEM_IO_COMP = (A_DATA_WIDTH > B_DATA_WIDTH) ? 1'b1 : 1'b0; - // write interface - - input clka; - input wea; - input [A_ADDRESS_WIDTH-1:0] addra; - input [A_DATA_WIDTH-1:0] dina; - - // read interface - - input clkb; - input [B_ADDRESS_WIDTH-1:0] addrb; - output [B_DATA_WIDTH-1:0] doutb; - // internal registers reg [MEM_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1]; - reg [B_DATA_WIDTH-1:0] doutb; // write interface options diff --git a/library/common/ad_pnmon.v b/library/common/ad_pnmon.v index 0614c7e6d..ad4415aa7 100644 --- a/library/common/ad_pnmon.v +++ b/library/common/ad_pnmon.v @@ -40,44 +40,29 @@ `timescale 1ns/100ps -module ad_pnmon ( +module ad_pnmon #( + + parameter DATA_WIDTH = 16) ( // adc interface - adc_clk, - adc_valid_in, - adc_data_in, - adc_data_pn, + input adc_clk, + input adc_valid_in, + input [DW:0] adc_data_in, + input [DW:0] adc_data_pn, // pn out of sync and error - adc_pn_oos, - adc_pn_err); + output reg adc_pn_oos, + output reg adc_pn_err); - // parameters - - parameter DATA_WIDTH = 16; localparam DW = DATA_WIDTH - 1; - // adc interface - - input adc_clk; - input adc_valid_in; - input [DW:0] adc_data_in; - input [DW:0] adc_data_pn; - - // pn out of sync and error - - output adc_pn_oos; - output adc_pn_err; - // internal registers reg adc_valid_d = 'd0; reg adc_pn_match_d = 'd0; reg adc_pn_match_z = 'd0; - reg adc_pn_err = 'd0; - reg adc_pn_oos = 'd0; reg [ 3:0] adc_pn_oos_count = 'd0; // internal signals diff --git a/library/common/ad_rst.v b/library/common/ad_rst.v index 1d9196331..a6c97ca21 100644 --- a/library/common/ad_rst.v +++ b/library/common/ad_rst.v @@ -41,21 +41,14 @@ module ad_rst ( // clock reset - preset, - clk, - rst); - - // clock reset - - input preset; - input clk; - output rst; + input preset, + input clk, + output reg rst); // internal registers reg ad_rst_sync_m1 = 'd0 /* synthesis preserve */; reg ad_rst_sync = 'd0 /* synthesis preserve */; - reg rst = 'd0; // simple reset gen diff --git a/library/common/ad_ss_422to444.v b/library/common/ad_ss_422to444.v index fbfdd2c6f..c6673c1bd 100644 --- a/library/common/ad_ss_422to444.v +++ b/library/common/ad_ss_422to444.v @@ -38,38 +38,25 @@ // *************************************************************************** // Input must be RGB or CrYCb in that order, output is CrY/CbY -module ad_ss_422to444 ( +module ad_ss_422to444 #( + + parameter CR_CB_N = 0, + parameter DELAY_DATA_WIDTH = 16) ( // 422 inputs - clk, - s422_de, - s422_sync, - s422_data, + input clk, + input s422_de, + input [DW:0] s422_sync, + input [15:0] s422_data, // 444 outputs - s444_sync, - s444_data); + output reg [DW:0] s444_sync, + output reg [23:0] s444_data); - // parameters - - parameter CR_CB_N = 0; - parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; - // 422 inputs - - input clk; - input s422_de; - input [DW:0] s422_sync; - input [15:0] s422_data; - - // 444 inputs - - output [DW:0] s444_sync; - output [23:0] s444_data; - // internal registers reg cr_cb_sel = 'd0; @@ -79,8 +66,6 @@ module ad_ss_422to444 ( reg [7:0] s422_Y_d; reg [7:0] s422_CbCr_d; reg [7:0] s422_CbCr_2d; - reg [DW:0] s444_sync = 'd0; - reg [23:0] s444_data = 'd0; reg [ 8:0] s422_CbCr_avg; // internal wires @@ -100,7 +85,6 @@ module ad_ss_422to444 ( assign s422_Y = s422_data[7:0]; assign s422_CbCr = s422_data[15:8]; - // first data on de assertion is cb (0x0), then cr (0x1). // previous data is held when not current diff --git a/library/common/ad_ss_444to422.v b/library/common/ad_ss_444to422.v index 3618cbcba..895a7b001 100644 --- a/library/common/ad_ss_444to422.v +++ b/library/common/ad_ss_444to422.v @@ -38,38 +38,25 @@ // *************************************************************************** // Input must be RGB or CrYCb in that order, output is CrY/CbY -module ad_ss_444to422 ( +module ad_ss_444to422 #( + + parameter CR_CB_N = 0, + parameter DELAY_DATA_WIDTH = 16) ( // 444 inputs - clk, - s444_de, - s444_sync, - s444_data, + input clk, + input s444_de, + input [DW:0] s444_sync, + input [23:0] s444_data, // 422 outputs - s422_sync, - s422_data); + output reg [DW:0] s422_sync, + output reg [15:0] s422_data); - // parameters - - parameter CR_CB_N = 0; - parameter DELAY_DATA_WIDTH = 16; localparam DW = DELAY_DATA_WIDTH - 1; - // 444 inputs - - input clk; - input s444_de; - input [DW:0] s444_sync; - input [23:0] s444_data; - - // 422 outputs - - output [DW:0] s422_sync; - output [15:0] s422_data; - // internal registers reg s444_de_d = 'd0; @@ -84,8 +71,6 @@ module ad_ss_444to422 ( reg [ 7:0] cr = 'd0; reg [ 7:0] cb = 'd0; reg cr_cb_sel = 'd0; - reg [DW:0] s422_sync = 'd0; - reg [15:0] s422_data = 'd0; // internal wires diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v index 151a3edeb..321dad83c 100644 --- a/library/common/ad_tdd_control.v +++ b/library/common/ad_tdd_control.v @@ -39,124 +39,68 @@ `timescale 1ns/1ps -module ad_tdd_control( +module ad_tdd_control#( + + parameter integer TX_DATA_PATH_DELAY = 0, + parameter integer CONTROL_PATH_DELAY = 0) ( // clock and reset - clk, - rst, + input clk, + input rst, // TDD timming signals - tdd_enable, - tdd_secondary, - tdd_tx_only, - tdd_rx_only, - tdd_burst_count, - tdd_counter_init, - tdd_frame_length, - tdd_vco_rx_on_1, - tdd_vco_rx_off_1, - tdd_vco_tx_on_1, - tdd_vco_tx_off_1, - tdd_rx_on_1, - tdd_rx_off_1, - tdd_rx_dp_on_1, - tdd_rx_dp_off_1, - tdd_tx_on_1, - tdd_tx_off_1, - tdd_tx_dp_on_1, - tdd_tx_dp_off_1, - tdd_vco_rx_on_2, - tdd_vco_rx_off_2, - tdd_vco_tx_on_2, - tdd_vco_tx_off_2, - tdd_rx_on_2, - tdd_rx_off_2, - tdd_rx_dp_on_2, - tdd_rx_dp_off_2, - tdd_tx_on_2, - tdd_tx_off_2, - tdd_tx_dp_on_2, - tdd_tx_dp_off_2, - tdd_sync, + input tdd_enable, + input tdd_secondary, + input tdd_tx_only, + input tdd_rx_only, + input [ 7:0] tdd_burst_count, + input [23:0] tdd_counter_init, + input [23:0] tdd_frame_length, + input [23:0] tdd_vco_rx_on_1, + input [23:0] tdd_vco_rx_off_1, + input [23:0] tdd_vco_tx_on_1, + input [23:0] tdd_vco_tx_off_1, + input [23:0] tdd_rx_on_1, + input [23:0] tdd_rx_off_1, + input [23:0] tdd_rx_dp_on_1, + input [23:0] tdd_rx_dp_off_1, + input [23:0] tdd_tx_on_1, + input [23:0] tdd_tx_off_1, + input [23:0] tdd_tx_dp_on_1, + input [23:0] tdd_tx_dp_off_1, + input [23:0] tdd_vco_rx_on_2, + input [23:0] tdd_vco_rx_off_2, + input [23:0] tdd_vco_tx_on_2, + input [23:0] tdd_vco_tx_off_2, + input [23:0] tdd_rx_on_2, + input [23:0] tdd_rx_off_2, + input [23:0] tdd_rx_dp_on_2, + input [23:0] tdd_rx_dp_off_2, + input [23:0] tdd_tx_on_2, + input [23:0] tdd_tx_off_2, + input [23:0] tdd_tx_dp_on_2, + input [23:0] tdd_tx_dp_off_2, + input tdd_sync, // TDD control signals - tdd_tx_dp_en, - tdd_rx_dp_en, - tdd_rx_vco_en, - tdd_tx_vco_en, - tdd_rx_rf_en, - tdd_tx_rf_en, + output reg tdd_tx_dp_en, + output reg tdd_rx_dp_en, + output reg tdd_rx_vco_en, + output reg tdd_tx_vco_en, + output reg tdd_rx_rf_en, + output reg tdd_tx_rf_en, - tdd_counter_status); + output [23:0] tdd_counter_status); - // parameters - - parameter integer TX_DATA_PATH_DELAY = 0; // internally eliminate the delay introduced by the TX data path - parameter integer CONTROL_PATH_DELAY = 0; // internally eliminate the delay introduced by the control path localparam ON = 1; localparam OFF = 0; - // input/output signals - - input clk; - input rst; - - input tdd_enable; - input tdd_secondary; - input tdd_tx_only; - input tdd_rx_only; - input [ 7:0] tdd_burst_count; - input [23:0] tdd_counter_init; - input [23:0] tdd_frame_length; - input [23:0] tdd_vco_rx_on_1; - input [23:0] tdd_vco_rx_off_1; - input [23:0] tdd_vco_tx_on_1; - input [23:0] tdd_vco_tx_off_1; - input [23:0] tdd_rx_on_1; - input [23:0] tdd_rx_off_1; - input [23:0] tdd_rx_dp_on_1; - input [23:0] tdd_rx_dp_off_1; - input [23:0] tdd_tx_on_1; - input [23:0] tdd_tx_off_1; - input [23:0] tdd_tx_dp_on_1; - input [23:0] tdd_tx_dp_off_1; - input [23:0] tdd_vco_rx_on_2; - input [23:0] tdd_vco_rx_off_2; - input [23:0] tdd_vco_tx_on_2; - input [23:0] tdd_vco_tx_off_2; - input [23:0] tdd_rx_on_2; - input [23:0] tdd_rx_off_2; - input [23:0] tdd_rx_dp_on_2; - input [23:0] tdd_rx_dp_off_2; - input [23:0] tdd_tx_on_2; - input [23:0] tdd_tx_off_2; - input [23:0] tdd_tx_dp_on_2; - input [23:0] tdd_tx_dp_off_2; - - input tdd_sync; - - output tdd_rx_vco_en; // initiate vco tx2rx switch - output tdd_tx_vco_en; // initiate vco rx2tx switch - output tdd_rx_rf_en; // power up RF Rx - output tdd_tx_rf_en; // power up RF Tx - output tdd_tx_dp_en; // enable Tx datapath - output tdd_rx_dp_en; // enable Rx datapath - - output [23:0] tdd_counter_status; - // tdd control related - reg tdd_tx_dp_en = 1'b0; - reg tdd_rx_dp_en = 1'b0; - reg tdd_rx_vco_en = 1'b0; - reg tdd_tx_vco_en = 1'b0; - reg tdd_rx_rf_en = 1'b0; - reg tdd_tx_rf_en = 1'b0; - // tdd counter related reg [23:0] tdd_counter = 24'h0; @@ -555,7 +499,6 @@ module ad_tdd_control( end end - // control-path delay compensation ad_addsub #( diff --git a/library/common/ad_xcvr_rx_if.v b/library/common/ad_xcvr_rx_if.v index a53052706..e9198b32a 100644 --- a/library/common/ad_xcvr_rx_if.v +++ b/library/common/ad_xcvr_rx_if.v @@ -37,38 +37,24 @@ `timescale 1ns/100ps -module ad_xcvr_rx_if ( +module ad_xcvr_rx_if #( + + parameter DEVICE_TYPE = 0) ( // jesd interface - rx_clk, - rx_ip_sof, - rx_ip_data, - rx_sof, - rx_data); + input rx_clk, + input [ 3:0] rx_ip_sof, + input [31:0] rx_ip_data, + output reg rx_sof, + output reg [31:0] rx_data); - // parameter - - parameter DEVICE_TYPE = 0; - - // jesd interface - - input rx_clk; - input [ 3:0] rx_ip_sof; - input [31:0] rx_ip_data; - - // aligned data - - output rx_sof; - output [31:0] rx_data; // internal registers reg [31:0] rx_ip_data_d = 'd0; reg [ 3:0] rx_ip_sof_hold = 'd0; - reg rx_sof = 'd0; reg rx_ip_sof_d = 'd0; - reg [31:0] rx_data = 'd0; // internal signals diff --git a/library/common/up_axi.v b/library/common/up_axi.v index db62e659a..ef878f393 100644 --- a/library/common/up_axi.v +++ b/library/common/up_axi.v @@ -37,104 +37,56 @@ `timescale 1ns/100ps -module up_axi ( +module up_axi #( + + parameter ADDRESS_WIDTH = 14) ( // reset and clocks - up_rstn, - up_clk, + input up_rstn, + input up_clk, // axi4 interface - up_axi_awvalid, - up_axi_awaddr, - up_axi_awready, - up_axi_wvalid, - up_axi_wdata, - up_axi_wstrb, - up_axi_wready, - up_axi_bvalid, - up_axi_bresp, - up_axi_bready, - up_axi_arvalid, - up_axi_araddr, - up_axi_arready, - up_axi_rvalid, - up_axi_rresp, - up_axi_rdata, - up_axi_rready, + input up_axi_awvalid, + input [31:0] up_axi_awaddr, + output reg up_axi_awready, + input up_axi_wvalid, + input [31:0] up_axi_wdata, + input [ 3:0] up_axi_wstrb, + output reg up_axi_wready, + output reg up_axi_bvalid, + output [ 1:0] up_axi_bresp, + input up_axi_bready, + input up_axi_arvalid, + input [31:0] up_axi_araddr, + output reg up_axi_arready, + output reg up_axi_rvalid, + output [ 1:0] up_axi_rresp, + output reg [31:0] up_axi_rdata, + input up_axi_rready, // pcore interface - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + output reg up_wreq, + output reg [AW:0] up_waddr, + output reg [31:0] up_wdata, + input up_wack, + output reg up_rreq, + output reg [AW:0] up_raddr, + input [31:0] up_rdata, + input up_rack); - // parameters - - parameter ADDRESS_WIDTH = 14; localparam AW = ADDRESS_WIDTH - 1; - // reset and clocks - - input up_rstn; - input up_clk; - - // axi4 interface - - input up_axi_awvalid; - input [31:0] up_axi_awaddr; - output up_axi_awready; - input up_axi_wvalid; - input [31:0] up_axi_wdata; - input [ 3:0] up_axi_wstrb; - output up_axi_wready; - output up_axi_bvalid; - output [ 1:0] up_axi_bresp; - input up_axi_bready; - input up_axi_arvalid; - input [31:0] up_axi_araddr; - output up_axi_arready; - output up_axi_rvalid; - output [ 1:0] up_axi_rresp; - output [31:0] up_axi_rdata; - input up_axi_rready; - - // pcore interface - - output up_wreq; - output [AW:0] up_waddr; - output [31:0] up_wdata; - input up_wack; - output up_rreq; - output [AW:0] up_raddr; - input [31:0] up_rdata; - input up_rack; - // internal registers - reg up_axi_awready = 'd0; - reg up_axi_wready = 'd0; - reg up_axi_bvalid = 'd0; reg up_wack_d = 'd0; reg up_wsel = 'd0; - reg up_wreq = 'd0; - reg [AW:0] up_waddr = 'd0; - reg [31:0] up_wdata = 'd0; reg [ 4:0] up_wcount = 'd0; - reg up_axi_arready = 'd0; - reg up_axi_rvalid = 'd0; - reg [31:0] up_axi_rdata = 'd0; reg up_rack_d = 'd0; reg [31:0] up_rdata_d = 'd0; reg up_rsel = 'd0; - reg up_rreq = 'd0; - reg [AW:0] up_raddr = 'd0; reg [ 4:0] up_rcount = 'd0; // internal signals diff --git a/library/common/up_clkgen.v b/library/common/up_clkgen.v index 5cd6619b7..629b513f1 100644 --- a/library/common/up_clkgen.v +++ b/library/common/up_clkgen.v @@ -37,92 +37,52 @@ `timescale 1ns/100ps -module up_clkgen ( +module up_clkgen #( + + parameter ID = 0) ( // mmcm reset - mmcm_rst, + output mmcm_rst, // clock selection - clk_sel, + output clk_sel, // drp interface - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked, + output reg up_drp_sel, + output reg up_drp_wr, + output reg [11:0] up_drp_addr, + output reg [15:0] up_drp_wdata, + input [15:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); localparam PCORE_VERSION = 32'h00040063; - parameter ID = 0; - - // mmcm reset - - output mmcm_rst; - - // clock selection - - output clk_sel; - - // drp interface - - output up_drp_sel; - output up_drp_wr; - output [11:0] up_drp_addr; - output [15:0] up_drp_wdata; - input [15:0] up_drp_rdata; - input up_drp_ready; - input up_drp_locked; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - // internal registers reg up_mmcm_preset = 'd0; - reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_mmcm_resetn = 'd0; reg up_resetn = 'd0; - reg up_drp_sel = 'd0; - reg up_drp_wr = 'd0; reg up_drp_status = 'd0; reg up_drp_rwn = 'd0; - reg [11:0] up_drp_addr = 'd0; - reg [15:0] up_drp_wdata = 'd0; reg [15:0] up_drp_rdata_hold = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; reg up_clk_sel = 'd0; // internal signals diff --git a/library/common/up_clock_mon.v b/library/common/up_clock_mon.v index ef5ad4abb..57807b096 100644 --- a/library/common/up_clock_mon.v +++ b/library/common/up_clock_mon.v @@ -41,25 +41,14 @@ module up_clock_mon ( // processor interface - up_rstn, - up_clk, - up_d_count, + input up_rstn, + input up_clk, + output reg [31:0] up_d_count, // device interface - d_rst, - d_clk); - - // processor interface - - input up_rstn; - input up_clk; - output [31:0] up_d_count; - - // device interface - - input d_rst; - input d_clk; + input d_rst, + input d_clk); // internal registers @@ -68,7 +57,6 @@ module up_clock_mon ( reg up_count_toggle_m1 = 'd0; reg up_count_toggle_m2 = 'd0; reg up_count_toggle_m3 = 'd0; - reg [31:0] up_d_count = 'd0; reg d_count_toggle_m1 = 'd0; reg d_count_toggle_m2 = 'd0; reg d_count_toggle_m3 = 'd0; diff --git a/library/common/up_gt.v b/library/common/up_gt.v index 8bc9dc31b..ffc8b1504 100644 --- a/library/common/up_gt.v +++ b/library/common/up_gt.v @@ -37,87 +37,47 @@ `timescale 1ns/100ps -module up_gt ( +module up_gt #( + + parameter integer GTH_OR_GTX_N = 0) ( // drp interface - up_drp_qpll0_sel, - up_drp_qpll0_wr, - up_drp_qpll0_addr, - up_drp_qpll0_wdata, - up_drp_qpll0_rdata, - up_drp_qpll0_ready, - up_drp_qpll1_sel, - up_drp_qpll1_wr, - up_drp_qpll1_addr, - up_drp_qpll1_wdata, - up_drp_qpll1_rdata, - up_drp_qpll1_ready, + output reg up_drp_qpll0_sel, + output reg up_drp_qpll0_wr, + output reg [11:0] up_drp_qpll0_addr, + output reg [15:0] up_drp_qpll0_wdata, + input [15:0] up_drp_qpll0_rdata, + input up_drp_qpll0_ready, + output reg up_drp_qpll1_sel, + output reg up_drp_qpll1_wr, + output reg [11:0] up_drp_qpll1_addr, + output reg [15:0] up_drp_qpll1_wdata, + input [15:0] up_drp_qpll1_rdata, + input up_drp_qpll1_ready, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); - // parameters - - parameter integer GTH_OR_GTX_N = 0; - - // drp interface - - output up_drp_qpll0_sel; - output up_drp_qpll0_wr; - output [11:0] up_drp_qpll0_addr; - output [15:0] up_drp_qpll0_wdata; - input [15:0] up_drp_qpll0_rdata; - input up_drp_qpll0_ready; - output up_drp_qpll1_sel; - output up_drp_qpll1_wr; - output [11:0] up_drp_qpll1_addr; - output [15:0] up_drp_qpll1_wdata; - input [15:0] up_drp_qpll1_rdata; - input up_drp_qpll1_ready; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg up_wack = 'd0; - reg up_drp_qpll0_sel = 'd0; - reg up_drp_qpll0_wr = 'd0; reg up_drp_qpll0_status = 'd0; reg up_drp_qpll0_rwn = 'd0; - reg [11:0] up_drp_qpll0_addr = 'd0; - reg [15:0] up_drp_qpll0_wdata = 'd0; reg [15:0] up_drp_qpll0_rdata_hold = 'd0; - reg up_drp_qpll1_sel = 'd0; - reg up_drp_qpll1_wr = 'd0; reg up_drp_qpll1_status = 'd0; reg up_drp_qpll1_rwn = 'd0; - reg [11:0] up_drp_qpll1_addr = 'd0; - reg [15:0] up_drp_qpll1_wdata = 'd0; reg [15:0] up_drp_qpll1_rdata_hold = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; // internal signals diff --git a/library/common/up_gt_channel.v b/library/common/up_gt_channel.v index 692cb986d..eae243032 100644 --- a/library/common/up_gt_channel.v +++ b/library/common/up_gt_channel.v @@ -37,218 +37,114 @@ `timescale 1ns/100ps -module up_gt_channel ( +module up_gt_channel #( + + parameter integer ID = 0) ( // gt interface - lpm_dfe_n, - cpll_pd, + output lpm_dfe_n, + output cpll_pd, // receive interface - rx_pll_rst, - rx_sys_clk_sel, - rx_out_clk_sel, - rx_clk, - rx_gt_rst, - rx_rst, - rx_rst_m, - rx_ip_rst, - rx_sysref, - rx_ip_sysref, - rx_ip_sync, - rx_sync, - rx_rst_done, - rx_rst_done_m, - rx_pll_locked, - rx_pll_locked_m, - rx_user_ready, - rx_ip_rst_done, + output rx_pll_rst, + output [ 1:0] rx_sys_clk_sel, + output [ 2:0] rx_out_clk_sel, + input rx_clk, + output rx_gt_rst, + output rx_rst, + input rx_rst_m, + output rx_ip_rst, + input rx_sysref, + output reg rx_ip_sysref, + input rx_ip_sync, + output reg rx_sync, + input rx_rst_done, + input rx_rst_done_m, + input rx_pll_locked, + input rx_pll_locked_m, + output rx_user_ready, + output rx_ip_rst_done, // transmit interface - tx_pll_rst, - tx_sys_clk_sel, - tx_out_clk_sel, - tx_clk, - tx_gt_rst, - tx_rst, - tx_rst_m, - tx_ip_rst, - tx_sysref, - tx_ip_sysref, - tx_sync, - tx_ip_sync, - tx_rst_done, - tx_rst_done_m, - tx_pll_locked, - tx_pll_locked_m, - tx_user_ready, - tx_ip_rst_done, + output tx_pll_rst, + output [ 1:0] tx_sys_clk_sel, + output [ 2:0] tx_out_clk_sel, + input tx_clk, + output tx_gt_rst, + output tx_rst, + input tx_rst_m, + output tx_ip_rst, + input tx_sysref, + output reg tx_ip_sysref, + input tx_sync, + output reg tx_ip_sync, + input tx_rst_done, + input tx_rst_done_m, + input tx_pll_locked, + input tx_pll_locked_m, + output tx_user_ready, + output tx_ip_rst_done, // drp interface - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_rxrate, + output reg up_drp_sel, + output reg up_drp_wr, + output reg [11:0] up_drp_addr, + output reg [15:0] up_drp_wdata, + input [15:0] up_drp_rdata, + input up_drp_ready, + input [ 7:0] up_drp_rxrate, // es interface - up_es_drp_sel, - up_es_drp_wr, - up_es_drp_addr, - up_es_drp_wdata, - up_es_drp_rdata, - up_es_drp_ready, - up_es_start, - up_es_stop, - up_es_init, - up_es_prescale, - up_es_voffset_range, - up_es_voffset_step, - up_es_voffset_max, - up_es_voffset_min, - up_es_hoffset_max, - up_es_hoffset_min, - up_es_hoffset_step, - up_es_start_addr, - up_es_sdata0, - up_es_sdata1, - up_es_sdata2, - up_es_sdata3, - up_es_sdata4, - up_es_qdata0, - up_es_qdata1, - up_es_qdata2, - up_es_qdata3, - up_es_qdata4, - up_es_dma_err, - up_es_status, + input up_es_drp_sel, + input up_es_drp_wr, + input [11:0] up_es_drp_addr, + input [15:0] up_es_drp_wdata, + output reg [15:0] up_es_drp_rdata, + output reg up_es_drp_ready, + output reg up_es_start, + output reg up_es_stop, + output reg up_es_init, + output reg [ 4:0] up_es_prescale, + output reg [ 1:0] up_es_voffset_range, + output reg [ 7:0] up_es_voffset_step, + output reg [ 7:0] up_es_voffset_max, + output reg [ 7:0] up_es_voffset_min, + output reg [11:0] up_es_hoffset_max, + output reg [11:0] up_es_hoffset_min, + output reg [11:0] up_es_hoffset_step, + output reg [31:0] up_es_start_addr, + output reg [15:0] up_es_sdata0, + output reg [15:0] up_es_sdata1, + output reg [15:0] up_es_sdata2, + output reg [15:0] up_es_sdata3, + output reg [15:0] up_es_sdata4, + output reg [15:0] up_es_qdata0, + output reg [15:0] up_es_qdata1, + output reg [15:0] up_es_qdata2, + output reg [15:0] up_es_qdata3, + output reg [15:0] up_es_qdata4, + input up_es_dma_err, + input up_es_status, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); localparam [31:0] VERSION = 32'h00070161; - parameter integer ID = 0; - - // gt interface - - output lpm_dfe_n; - output cpll_pd; - - // receive interface - - output rx_pll_rst; - output [ 1:0] rx_sys_clk_sel; - output [ 2:0] rx_out_clk_sel; - input rx_clk; - output rx_gt_rst; - output rx_rst; - input rx_rst_m; - output rx_ip_rst; - input rx_sysref; - output rx_ip_sysref; - input rx_ip_sync; - output rx_sync; - input rx_rst_done; - input rx_rst_done_m; - input rx_pll_locked; - input rx_pll_locked_m; - output rx_user_ready; - output rx_ip_rst_done; - - // transmit interface - - output tx_pll_rst; - output [ 1:0] tx_sys_clk_sel; - output [ 2:0] tx_out_clk_sel; - input tx_clk; - output tx_gt_rst; - output tx_rst; - input tx_rst_m; - output tx_ip_rst; - input tx_sysref; - output tx_ip_sysref; - input tx_sync; - output tx_ip_sync; - input tx_rst_done; - input tx_rst_done_m; - input tx_pll_locked; - input tx_pll_locked_m; - output tx_user_ready; - output tx_ip_rst_done; - - // drp interface - - output up_drp_sel; - output up_drp_wr; - output [11:0] up_drp_addr; - output [15:0] up_drp_wdata; - input [15:0] up_drp_rdata; - input up_drp_ready; - input [ 7:0] up_drp_rxrate; - - // es interface - - input up_es_drp_sel; - input up_es_drp_wr; - input [11:0] up_es_drp_addr; - input [15:0] up_es_drp_wdata; - output [15:0] up_es_drp_rdata; - output up_es_drp_ready; - output up_es_start; - output up_es_stop; - output up_es_init; - output [ 4:0] up_es_prescale; - output [ 1:0] up_es_voffset_range; - output [ 7:0] up_es_voffset_step; - output [ 7:0] up_es_voffset_max; - output [ 7:0] up_es_voffset_min; - output [11:0] up_es_hoffset_max; - output [11:0] up_es_hoffset_min; - output [11:0] up_es_hoffset_step; - output [31:0] up_es_start_addr; - output [15:0] up_es_sdata0; - output [15:0] up_es_sdata1; - output [15:0] up_es_sdata2; - output [15:0] up_es_sdata3; - output [15:0] up_es_sdata4; - output [15:0] up_es_qdata0; - output [15:0] up_es_qdata1; - output [15:0] up_es_qdata2; - output [15:0] up_es_qdata3; - output [15:0] up_es_qdata4; - input up_es_dma_err; - input up_es_status; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers @@ -258,7 +154,6 @@ module up_gt_channel ( reg up_tx_pll_preset = 'd1; reg up_tx_gt_preset = 'd1; reg up_tx_preset = 'd1; - reg up_wack = 'd0; reg up_lpm_dfe_n = 'd0; reg up_cpll_pd = 'd0; reg up_drp_resetn = 'd0; @@ -287,33 +182,9 @@ module up_gt_channel ( reg [11:0] up_drp_addr_int = 'd0; reg [15:0] up_drp_wdata_int = 'd0; reg [15:0] up_drp_rdata_hold = 'd0; - reg up_es_init = 'd0; - reg up_es_stop = 'd0; reg up_es_stop_hold = 'd0; - reg up_es_start = 'd0; reg up_es_start_hold = 'd0; - reg [ 4:0] up_es_prescale = 'd0; - reg [ 1:0] up_es_voffset_range = 'd0; - reg [ 7:0] up_es_voffset_step = 'd0; - reg [ 7:0] up_es_voffset_max = 'd0; - reg [ 7:0] up_es_voffset_min = 'd0; - reg [11:0] up_es_hoffset_max = 'd0; - reg [11:0] up_es_hoffset_min = 'd0; - reg [11:0] up_es_hoffset_step = 'd0; - reg [31:0] up_es_start_addr = 'd0; - reg [15:0] up_es_sdata1 = 'd0; - reg [15:0] up_es_sdata0 = 'd0; - reg [15:0] up_es_sdata3 = 'd0; - reg [15:0] up_es_sdata2 = 'd0; - reg [15:0] up_es_sdata4 = 'd0; - reg [15:0] up_es_qdata1 = 'd0; - reg [15:0] up_es_qdata0 = 'd0; - reg [15:0] up_es_qdata3 = 'd0; - reg [15:0] up_es_qdata2 = 'd0; - reg [15:0] up_es_qdata4 = 'd0; reg up_es_dma_err_hold = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; reg up_rx_rst_done_m1 = 'd0; reg up_rx_rst_done = 'd0; reg up_rx_rst_done_m_m1 = 'd0; @@ -334,30 +205,20 @@ module up_gt_channel ( reg up_tx_pll_locked_m = 'd0; reg up_tx_status_m1 = 'd0; reg up_tx_status = 'd0; - reg up_drp_sel = 'd0; - reg up_drp_wr = 'd0; - reg [11:0] up_drp_addr = 'd0; - reg [15:0] up_drp_wdata = 'd0; - reg [15:0] up_es_drp_rdata = 'd0; - reg up_es_drp_ready = 'd0; reg [15:0] up_drp_rdata_int = 'd0; reg up_drp_ready_int = 'd0; reg rx_sysref_sel_m1 = 'd0; reg rx_sysref_sel = 'd0; reg rx_up_sysref_m1 = 'd0; reg rx_up_sysref = 'd0; - reg rx_ip_sysref = 'd0; reg rx_up_sync_m1 = 'd0; reg rx_up_sync = 'd0; - reg rx_sync = 'd0; reg tx_sysref_sel_m1 = 'd0; reg tx_sysref_sel = 'd0; reg tx_up_sysref_m1 = 'd0; reg tx_up_sysref = 'd0; - reg tx_ip_sysref = 'd0; reg tx_up_sync_m1 = 'd0; reg tx_up_sync = 'd0; - reg tx_ip_sync = 'd0; reg [31:0] up_scratch = 'd0; // internal signals diff --git a/library/common/up_hdmi_rx.v b/library/common/up_hdmi_rx.v index cfe9e1216..4a80df1bb 100644 --- a/library/common/up_hdmi_rx.v +++ b/library/common/up_hdmi_rx.v @@ -35,86 +35,50 @@ // *************************************************************************** // *************************************************************************** -module up_hdmi_rx ( +module up_hdmi_rx #( + + parameter ID = 0) ( // hdmi interface - hdmi_clk, - hdmi_rst, - hdmi_edge_sel, - hdmi_bgr, - hdmi_packed, - hdmi_csc_bypass, - hdmi_vs_count, - hdmi_hs_count, - hdmi_dma_ovf, - hdmi_dma_unf, - hdmi_tpm_oos, - hdmi_vs_oos, - hdmi_hs_oos, - hdmi_vs_mismatch, - hdmi_hs_mismatch, - hdmi_vs, - hdmi_hs, - hdmi_clk_ratio, + input hdmi_clk, + output hdmi_rst, + output hdmi_edge_sel, + output hdmi_bgr, + output hdmi_packed, + output hdmi_csc_bypass, + output [15:0] hdmi_vs_count, + output [15:0] hdmi_hs_count, + input hdmi_dma_ovf, + input hdmi_dma_unf, + input hdmi_tpm_oos, + input hdmi_vs_oos, + input hdmi_hs_oos, + input hdmi_vs_mismatch, + input hdmi_hs_mismatch, + input [15:0] hdmi_vs, + input [15:0] hdmi_hs, + input [31:0] hdmi_clk_ratio, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); localparam PCORE_VERSION = 32'h00040063; - parameter ID = 0; - - // hdmi interface - - input hdmi_clk; - output hdmi_rst; - output hdmi_edge_sel; - output hdmi_bgr; - output hdmi_packed; - output hdmi_csc_bypass; - output [15:0] hdmi_vs_count; - output [15:0] hdmi_hs_count; - input hdmi_dma_ovf; - input hdmi_dma_unf; - input hdmi_tpm_oos; - input hdmi_vs_oos; - input hdmi_hs_oos; - input hdmi_vs_mismatch; - input hdmi_hs_mismatch; - input [15:0] hdmi_vs; - input [15:0] hdmi_hs; - input [31:0] hdmi_clk_ratio; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers reg up_core_preset = 'd0; reg up_resetn = 'd0; - reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_edge_sel = 'd0; reg up_bgr = 'd0; @@ -129,8 +93,6 @@ module up_hdmi_rx ( reg up_hs_mismatch = 'd0; reg [15:0] up_vs_count = 'd0; reg [15:0] up_hs_count = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; // internal signals diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v index bbef0119e..457d9e0e8 100644 --- a/library/common/up_hdmi_tx.v +++ b/library/common/up_hdmi_tx.v @@ -37,107 +37,60 @@ `timescale 1ns/100ps -module up_hdmi_tx ( +module up_hdmi_tx #( + + parameter ID = 0) ( // hdmi interface - hdmi_clk, - hdmi_rst, - hdmi_csc_bypass, - hdmi_ss_bypass, - hdmi_srcsel, - hdmi_const_rgb, - hdmi_hl_active, - hdmi_hl_width, - hdmi_hs_width, - hdmi_he_max, - hdmi_he_min, - hdmi_vf_active, - hdmi_vf_width, - hdmi_vs_width, - hdmi_ve_max, - hdmi_ve_min, - hdmi_clip_max, - hdmi_clip_min, - hdmi_status, - hdmi_tpm_oos, - hdmi_clk_ratio, + input hdmi_clk, + output hdmi_rst, + output hdmi_csc_bypass, + output hdmi_ss_bypass, + output [ 1:0] hdmi_srcsel, + output [23:0] hdmi_const_rgb, + output [15:0] hdmi_hl_active, + output [15:0] hdmi_hl_width, + output [15:0] hdmi_hs_width, + output [15:0] hdmi_he_max, + output [15:0] hdmi_he_min, + output [15:0] hdmi_vf_active, + output [15:0] hdmi_vf_width, + output [15:0] hdmi_vs_width, + output [15:0] hdmi_ve_max, + output [15:0] hdmi_ve_min, + output [23:0] hdmi_clip_max, + output [23:0] hdmi_clip_min, + input hdmi_status, + input hdmi_tpm_oos, + input [31:0] hdmi_clk_ratio, // vdma interface - vdma_clk, - vdma_rst, - vdma_ovf, - vdma_unf, - vdma_tpm_oos, + input vdma_clk, + output vdma_rst, + input vdma_ovf, + input vdma_unf, + input vdma_tpm_oos, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); localparam PCORE_VERSION = 32'h00040063; - parameter ID = 0; - - // hdmi interface - - input hdmi_clk; - output hdmi_rst; - output hdmi_csc_bypass; - output hdmi_ss_bypass; - output [ 1:0] hdmi_srcsel; - output [23:0] hdmi_const_rgb; - output [15:0] hdmi_hl_active; - output [15:0] hdmi_hl_width; - output [15:0] hdmi_hs_width; - output [15:0] hdmi_he_max; - output [15:0] hdmi_he_min; - output [15:0] hdmi_vf_active; - output [15:0] hdmi_vf_width; - output [15:0] hdmi_vs_width; - output [15:0] hdmi_ve_max; - output [15:0] hdmi_ve_min; - output [23:0] hdmi_clip_max; - output [23:0] hdmi_clip_min; - input hdmi_status; - input hdmi_tpm_oos; - input [31:0] hdmi_clk_ratio; - - // vdma interface - - input vdma_clk; - output vdma_rst; - input vdma_ovf; - input vdma_unf; - input vdma_tpm_oos; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers reg up_core_preset = 'd0; - reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_resetn = 'd0; reg up_csc_bypass = 'd0; @@ -160,8 +113,6 @@ module up_hdmi_tx ( reg [15:0] up_ve_min = 'd0; reg [23:0] up_clip_max = 'd0; reg [23:0] up_clip_min = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; // internal signals diff --git a/library/common/up_pmod.v b/library/common/up_pmod.v index 2e1c14590..3745b64b6 100644 --- a/library/common/up_pmod.v +++ b/library/common/up_pmod.v @@ -39,54 +39,33 @@ `timescale 1ns/100ps -module up_pmod ( +module up_pmod #( - pmod_clk, - pmod_rst, - pmod_signal_freq, + parameter ID = 0) ( + + input pmod_clk, + output pmod_rst, + input [31:0] pmod_signal_freq, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); localparam PCORE_VERSION = 32'h00010001; - parameter ID = 0; - - input pmod_clk; - output pmod_rst; - input [31:0] pmod_signal_freq; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_resetn = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; // internal signals diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index 71c7ce4e8..7784055ce 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -38,127 +38,70 @@ // *************************************************************************** `timescale 1ns/100ps -module up_tdd_cntrl ( +module up_tdd_cntrl #( - clk, - rst, + parameter ID = 0) ( + + input clk, + input rst, //rf tdd interface control - tdd_enable, - tdd_secondary, - tdd_rx_only, - tdd_tx_only, - tdd_gated_rx_dmapath, - tdd_gated_tx_dmapath, - tdd_burst_count, - tdd_counter_init, - tdd_frame_length, - tdd_terminal_type, - tdd_vco_rx_on_1, - tdd_vco_rx_off_1, - tdd_vco_tx_on_1, - tdd_vco_tx_off_1, - tdd_rx_on_1, - tdd_rx_off_1, - tdd_rx_dp_on_1, - tdd_rx_dp_off_1, - tdd_tx_on_1, - tdd_tx_off_1, - tdd_tx_dp_on_1, - tdd_tx_dp_off_1, - tdd_vco_rx_on_2, - tdd_vco_rx_off_2, - tdd_vco_tx_on_2, - tdd_vco_tx_off_2, - tdd_rx_on_2, - tdd_rx_off_2, - tdd_rx_dp_on_2, - tdd_rx_dp_off_2, - tdd_tx_on_2, - tdd_tx_off_2, - tdd_tx_dp_on_2, - tdd_tx_dp_off_2, + output tdd_enable, + output tdd_secondary, + output tdd_rx_only, + output tdd_tx_only, + output tdd_gated_rx_dmapath, + output tdd_gated_tx_dmapath, + output [ 7:0] tdd_burst_count, + output [23:0] tdd_counter_init, + output [23:0] tdd_frame_length, + output tdd_terminal_type, + output [23:0] tdd_vco_rx_on_1, + output [23:0] tdd_vco_rx_off_1, + output [23:0] tdd_vco_tx_on_1, + output [23:0] tdd_vco_tx_off_1, + output [23:0] tdd_rx_on_1, + output [23:0] tdd_rx_off_1, + output [23:0] tdd_rx_dp_on_1, + output [23:0] tdd_rx_dp_off_1, + output [23:0] tdd_tx_on_1, + output [23:0] tdd_tx_off_1, + output [23:0] tdd_tx_dp_on_1, + output [23:0] tdd_tx_dp_off_1, + output [23:0] tdd_vco_rx_on_2, + output [23:0] tdd_vco_rx_off_2, + output [23:0] tdd_vco_tx_on_2, + output [23:0] tdd_vco_tx_off_2, + output [23:0] tdd_rx_on_2, + output [23:0] tdd_rx_off_2, + output [23:0] tdd_rx_dp_on_2, + output [23:0] tdd_rx_dp_off_2, + output [23:0] tdd_tx_on_2, + output [23:0] tdd_tx_off_2, + output [23:0] tdd_tx_dp_on_2, + output [23:0] tdd_tx_dp_off_2, - tdd_status, + input [ 7:0] tdd_status, // bus interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); localparam PCORE_VERSION = 32'h00010061; - parameter ID = 0; - - input clk; - input rst; - - output tdd_enable; - output tdd_secondary; - output tdd_rx_only; - output tdd_tx_only; - output tdd_gated_rx_dmapath; - output tdd_gated_tx_dmapath; - output [ 7:0] tdd_burst_count; - output [23:0] tdd_counter_init; - output [23:0] tdd_frame_length; - output tdd_terminal_type; - output [23:0] tdd_vco_rx_on_1; - output [23:0] tdd_vco_rx_off_1; - output [23:0] tdd_vco_tx_on_1; - output [23:0] tdd_vco_tx_off_1; - output [23:0] tdd_rx_on_1; - output [23:0] tdd_rx_off_1; - output [23:0] tdd_rx_dp_on_1; - output [23:0] tdd_rx_dp_off_1; - output [23:0] tdd_tx_on_1; - output [23:0] tdd_tx_off_1; - output [23:0] tdd_tx_dp_on_1; - output [23:0] tdd_tx_dp_off_1; - output [23:0] tdd_vco_rx_on_2; - output [23:0] tdd_vco_rx_off_2; - output [23:0] tdd_vco_tx_on_2; - output [23:0] tdd_vco_tx_off_2; - output [23:0] tdd_rx_on_2; - output [23:0] tdd_rx_off_2; - output [23:0] tdd_rx_dp_on_2; - output [23:0] tdd_rx_dp_off_2; - output [23:0] tdd_tx_on_2; - output [23:0] tdd_tx_off_2; - output [23:0] tdd_tx_dp_on_2; - output [23:0] tdd_tx_dp_off_2; - - input [ 7:0] tdd_status; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; // internal registers - reg up_wack = 1'h0; reg [31:0] up_scratch = 32'h0; - reg up_rack = 1'h0; - reg [31:0] up_rdata = 32'h0; reg up_tdd_enable = 1'h0; reg up_tdd_secondary = 1'h0; @@ -491,7 +434,6 @@ module up_tdd_cntrl ( tdd_tx_dp_off_2 })); - up_xfer_status #(.DATA_WIDTH(8)) i_xfer_tdd_status ( .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/common/up_xfer_cntrl.v b/library/common/up_xfer_cntrl.v index 20faabaa7..e801aca76 100644 --- a/library/common/up_xfer_cntrl.v +++ b/library/common/up_xfer_cntrl.v @@ -37,53 +37,37 @@ `timescale 1ns/100ps -module up_xfer_cntrl ( +module up_xfer_cntrl #( + + parameter DATA_WIDTH = 8) ( // up interface - up_rstn, - up_clk, - up_data_cntrl, - up_xfer_done, + input up_rstn, + input up_clk, + input [DW:0] up_data_cntrl, + output reg up_xfer_done, // device interface - d_rst, - d_clk, - d_data_cntrl); + input d_rst, + input d_clk, + output reg [DW:0] d_data_cntrl); - // parameters - - parameter DATA_WIDTH = 8; localparam DW = DATA_WIDTH - 1; - // up interface - - input up_rstn; - input up_clk; - input [DW:0] up_data_cntrl; - output up_xfer_done; - - // device interface - - input d_rst; - input d_clk; - output [DW:0] d_data_cntrl; - // internal registers reg up_xfer_state_m1 = 'd0; reg up_xfer_state_m2 = 'd0; reg up_xfer_state = 'd0; reg [ 5:0] up_xfer_count = 'd0; - reg up_xfer_done = 'd0; reg up_xfer_toggle = 'd0; reg [DW:0] up_xfer_data = 'd0; reg d_xfer_toggle_m1 = 'd0; reg d_xfer_toggle_m2 = 'd0; reg d_xfer_toggle_m3 = 'd0; reg d_xfer_toggle = 'd0; - reg [DW:0] d_data_cntrl = 'd0; // internal signals diff --git a/library/common/up_xfer_status.v b/library/common/up_xfer_status.v index bcbf1a607..4ede772f5 100644 --- a/library/common/up_xfer_status.v +++ b/library/common/up_xfer_status.v @@ -37,37 +37,24 @@ `timescale 1ns/100ps -module up_xfer_status ( +module up_xfer_status #( + + parameter DATA_WIDTH = 8) ( // up interface - up_rstn, - up_clk, - up_data_status, + input up_rstn, + input up_clk, + output reg [DW:0] up_data_status, // device interface - d_rst, - d_clk, - d_data_status); + input d_rst, + input d_clk, + input [DW:0] d_data_status); - // parameters - - parameter DATA_WIDTH = 8; localparam DW = DATA_WIDTH - 1; - // up interface - - input up_rstn; - input up_clk; - output [DW:0] up_data_status; - - // device interface - - input d_rst; - input d_clk; - input [DW:0] d_data_status; - // internal registers reg d_xfer_state_m1 = 'd0; @@ -81,7 +68,6 @@ module up_xfer_status ( reg up_xfer_toggle_m2 = 'd0; reg up_xfer_toggle_m3 = 'd0; reg up_xfer_toggle = 'd0; - reg [DW:0] up_data_status = 'd0; // internal signals diff --git a/library/common/util_pulse_gen.v b/library/common/util_pulse_gen.v index b9803ba18..b421a2c52 100644 --- a/library/common/util_pulse_gen.v +++ b/library/common/util_pulse_gen.v @@ -38,26 +38,21 @@ // *************************************************************************** `timescale 1ns/1ps -module util_pulse_gen ( +module util_pulse_gen #( - clk, - rstn, + parameter PULSE_WIDTH = 7, + parameter PULSE_PERIOD = 100000000) ( - pulse -); + input clk, + input rstn, - parameter PULSE_WIDTH = 7; - parameter PULSE_PERIOD = 100000000; // t_period * clk_freq + output reg pulse); - input clk; - input rstn; - output pulse; // internal registers reg [(PULSE_WIDTH-1):0] pulse_width_cnt = {PULSE_WIDTH{1'b1}}; reg [31:0] pulse_period_cnt = 32'h0; - reg pulse = 1'b0; wire end_of_period_s; diff --git a/library/prcfg/bist/prcfg_adc.v b/library/prcfg/bist/prcfg_adc.v index 19562d547..043c92464 100644 --- a/library/prcfg/bist/prcfg_adc.v +++ b/library/prcfg/bist/prcfg_adc.v @@ -40,44 +40,26 @@ `timescale 1ns/1ns -module prcfg_adc ( - clk, +module prcfg_adc #( + + parameter CHANNEL_ID = 0) ( + input clk, // control ports - control, - status, + input [31:0] control, + output reg [31:0] status, // FIFO interface - src_adc_enable, - src_adc_valid, - src_adc_data, + input src_adc_enable, + input src_adc_valid, + input [15:0] src_adc_data, - dst_adc_enable, - dst_adc_valid, - dst_adc_data -); + output reg dst_adc_enable, + output reg dst_adc_valid, + output reg [15:0] dst_adc_data); localparam RP_ID = 8'hA1; - parameter CHANNEL_ID = 0; - input clk; - - input [31:0] control; - output [31:0] status; - - input src_adc_enable; - input src_adc_valid; - input [15:0] src_adc_data; - - output dst_adc_enable; - output dst_adc_valid; - output [15:0] dst_adc_data; - - reg dst_adc_enable; - reg dst_adc_valid; - reg [15:0] dst_adc_data; - - reg [31:0] status = 0; reg [15:0] adc_pn_data = 0; reg [ 3:0] mode; @@ -88,7 +70,6 @@ module prcfg_adc ( wire adc_pn_oos_s; wire adc_pn_err_s; - // prbs function function [15:0] pn; diff --git a/library/prcfg/bist/prcfg_dac.v b/library/prcfg/bist/prcfg_dac.v index 2f4637b9d..524182ca0 100644 --- a/library/prcfg/bist/prcfg_dac.v +++ b/library/prcfg/bist/prcfg_dac.v @@ -40,46 +40,28 @@ `timescale 1ns/1ns -module prcfg_dac( +module prcfg_dac#( - clk, + parameter CHANNEL_ID = 0) ( + + input clk, // control ports - control, - status, + input [31:0] control, + output reg [31:0] status, // FIFO interface - src_dac_enable, - src_dac_data, - src_dac_valid, + output reg src_dac_enable, + input [15:0] src_dac_data, + output reg src_dac_valid, - dst_dac_enable, - dst_dac_data, - dst_dac_valid -); + input dst_dac_enable, + output reg [15:0] dst_dac_data, + input dst_dac_valid); localparam RP_ID = 8'hA1; - parameter CHANNEL_ID = 0; - - input clk; - - input [31:0] control; - output [31:0] status; - - output src_dac_enable; - input [15:0] src_dac_data; - output src_dac_valid; - - input dst_dac_enable; - output [15:0] dst_dac_data; - input dst_dac_valid; - - reg [15:0] dst_dac_data = 0; - reg src_dac_valid = 0; - reg src_dac_enable = 0; reg [15:0] dac_prbs = 32'hA2F19C; - reg [31:0] status = 0; reg [ 2:0] counter = 0; reg pattern = 0; diff --git a/library/prcfg/common/prcfg_top.v b/library/prcfg/common/prcfg_top.v index ec38768dc..a96f232a2 100644 --- a/library/prcfg/common/prcfg_top.v +++ b/library/prcfg/common/prcfg_top.v @@ -40,140 +40,80 @@ `timescale 1ns/1ns -module prcfg_top( +module prcfg_top#( - clk, + parameter NUM_CHANNEL = 4, + parameter ADC_EN = 1, + parameter DAC_EN = 1) ( + + input clk, // gpio - dac_gpio_input, - dac_gpio_output, - adc_gpio_input, - adc_gpio_output, + input [31:0] dac_gpio_input, + output [31:0] dac_gpio_output, + input [31:0] adc_gpio_input, + output [31:0] adc_gpio_output, // TX side - dma_dac_0_enable, - dma_dac_0_data, - dma_dac_0_valid, - dma_dac_1_enable, - dma_dac_1_data, - dma_dac_1_valid, - dma_dac_2_enable, - dma_dac_2_data, - dma_dac_2_valid, - dma_dac_3_enable, - dma_dac_3_data, - dma_dac_3_valid, + input dma_dac_0_enable, + output [(DBUS_WIDTH-1):0] dma_dac_0_data, + input dma_dac_0_valid, + input dma_dac_1_enable, + output [(DBUS_WIDTH-1):0] dma_dac_1_data, + input dma_dac_1_valid, + input dma_dac_2_enable, + output [(DBUS_WIDTH-1):0] dma_dac_2_data, + input dma_dac_2_valid, + input dma_dac_3_enable, + output [(DBUS_WIDTH-1):0] dma_dac_3_data, + input dma_dac_3_valid, - core_dac_0_enable, - core_dac_0_data, - core_dac_0_valid, - core_dac_1_enable, - core_dac_1_data, - core_dac_1_valid, - core_dac_2_enable, - core_dac_2_data, - core_dac_2_valid, - core_dac_3_enable, - core_dac_3_data, - core_dac_3_valid, + output core_dac_0_enable, + input [(DBUS_WIDTH-1):0] core_dac_0_data, + output core_dac_0_valid, + output core_dac_1_enable, + input [(DBUS_WIDTH-1):0] core_dac_1_data, + output core_dac_1_valid, + output core_dac_2_enable, + input [(DBUS_WIDTH-1):0] core_dac_2_data, + output core_dac_2_valid, + output core_dac_3_enable, + input [(DBUS_WIDTH-1):0] core_dac_3_data, + output core_dac_3_valid, // RX side - dma_adc_0_enable, - dma_adc_0_data, - dma_adc_0_valid, - dma_adc_1_enable, - dma_adc_1_data, - dma_adc_1_valid, - dma_adc_2_enable, - dma_adc_2_data, - dma_adc_2_valid, - dma_adc_3_enable, - dma_adc_3_data, - dma_adc_3_valid, + input dma_adc_0_enable, + input [(DBUS_WIDTH-1):0] dma_adc_0_data, + input dma_adc_0_valid, + input dma_adc_1_enable, + input [(DBUS_WIDTH-1):0] dma_adc_1_data, + input dma_adc_1_valid, + input dma_adc_2_enable, + input [(DBUS_WIDTH-1):0] dma_adc_2_data, + input dma_adc_2_valid, + input dma_adc_3_enable, + input [(DBUS_WIDTH-1):0] dma_adc_3_data, + input dma_adc_3_valid, - core_adc_0_enable, - core_adc_0_data, - core_adc_0_valid, - core_adc_1_enable, - core_adc_1_data, - core_adc_1_valid, - core_adc_2_enable, - core_adc_2_data, - core_adc_2_valid, - core_adc_3_enable, - core_adc_3_data, - core_adc_3_valid -); + output core_adc_0_enable, + output [(DBUS_WIDTH-1):0] core_adc_0_data, + output core_adc_0_valid, + output core_adc_1_enable, + output [(DBUS_WIDTH-1):0] core_adc_1_data, + output core_adc_1_valid, + output core_adc_2_enable, + output [(DBUS_WIDTH-1):0] core_adc_2_data, + output core_adc_2_valid, + output core_adc_3_enable, + output [(DBUS_WIDTH-1):0] core_adc_3_data, + output core_adc_3_valid); localparam ENABELED = 1; localparam DATA_WIDTH = 16; - parameter NUM_CHANNEL = 4; - parameter ADC_EN = 1; - parameter DAC_EN = 1; localparam DBUS_WIDTH = DATA_WIDTH * NUM_CHANNEL; - input clk; - - input [31:0] dac_gpio_input; - output [31:0] dac_gpio_output; - input [31:0] adc_gpio_input; - output [31:0] adc_gpio_output; - - input dma_dac_0_enable; - output [(DBUS_WIDTH-1):0] dma_dac_0_data; - input dma_dac_0_valid; - input dma_dac_1_enable; - output [(DBUS_WIDTH-1):0] dma_dac_1_data; - input dma_dac_1_valid; - input dma_dac_2_enable; - output [(DBUS_WIDTH-1):0] dma_dac_2_data; - input dma_dac_2_valid; - input dma_dac_3_enable; - output [(DBUS_WIDTH-1):0] dma_dac_3_data; - input dma_dac_3_valid; - - output core_dac_0_enable; - input [(DBUS_WIDTH-1):0] core_dac_0_data; - output core_dac_0_valid; - output core_dac_1_enable; - input [(DBUS_WIDTH-1):0] core_dac_1_data; - output core_dac_1_valid; - output core_dac_2_enable; - input [(DBUS_WIDTH-1):0] core_dac_2_data; - output core_dac_2_valid; - output core_dac_3_enable; - input [(DBUS_WIDTH-1):0] core_dac_3_data; - output core_dac_3_valid; - - // RX side - input dma_adc_0_enable; - input [(DBUS_WIDTH-1):0] dma_adc_0_data; - input dma_adc_0_valid; - input dma_adc_1_enable; - input [(DBUS_WIDTH-1):0] dma_adc_1_data; - input dma_adc_1_valid; - input dma_adc_2_enable; - input [(DBUS_WIDTH-1):0] dma_adc_2_data; - input dma_adc_2_valid; - input dma_adc_3_enable; - input [(DBUS_WIDTH-1):0] dma_adc_3_data; - input dma_adc_3_valid; - - output core_adc_0_enable; - output [(DBUS_WIDTH-1):0] core_adc_0_data; - output core_adc_0_valid; - output core_adc_1_enable; - output [(DBUS_WIDTH-1):0] core_adc_1_data; - output core_adc_1_valid; - output core_adc_2_enable; - output [(DBUS_WIDTH-1):0] core_adc_2_data; - output core_adc_2_valid; - output core_adc_3_enable; - output [(DBUS_WIDTH-1):0] core_adc_3_data; - output core_adc_3_valid; - wire [31:0] adc_gpio_out_s[(NUM_CHANNEL - 1):0]; wire [(NUM_CHANNEL - 1):0] adc_gpio_out_s_inv[31:0]; diff --git a/library/prcfg/default/prcfg_adc.v b/library/prcfg/default/prcfg_adc.v index df84bf0f5..1f947263c 100644 --- a/library/prcfg/default/prcfg_adc.v +++ b/library/prcfg/default/prcfg_adc.v @@ -40,42 +40,25 @@ `timescale 1ns/1ns -module prcfg_adc ( - clk, +module prcfg_adc #( + + parameter CHANNEL_ID = 0) ( + input clk, // control ports - control, - status, + input [31:0] control, + output [31:0] status, // FIFO interface - src_adc_enable, - src_adc_valid, - src_adc_data, + input src_adc_enable, + input src_adc_valid, + input [15:0] src_adc_data, - dst_adc_enable, - dst_adc_valid, - dst_adc_data -); + output reg dst_adc_enable, + output reg dst_adc_valid, + output reg [15:0] dst_adc_data); localparam RP_ID = 8'hA0; - parameter CHANNEL_ID = 0; - - input clk; - - input [31:0] control; - output [31:0] status; - - input src_adc_enable; - input src_adc_valid; - input [15:0] src_adc_data; - - output dst_adc_enable; - output dst_adc_valid; - output [15:0] dst_adc_data; - - reg dst_adc_enable; - reg dst_adc_valid; - reg [15:0] dst_adc_data; assign status = {24'h0, RP_ID}; diff --git a/library/prcfg/default/prcfg_dac.v b/library/prcfg/default/prcfg_dac.v index eb5b473a6..9c8f804ba 100644 --- a/library/prcfg/default/prcfg_dac.v +++ b/library/prcfg/default/prcfg_dac.v @@ -40,43 +40,26 @@ `timescale 1ns/1ns -module prcfg_dac( +module prcfg_dac#( - clk, + parameter CHANNEL_ID = 0) ( + + input clk, // control ports - control, - status, + input [31:0] control, + output [31:0] status, // FIFO interface - src_dac_enable, - src_dac_data, - src_dac_valid, + output reg src_dac_enable, + input [15:0] src_dac_data, + output reg src_dac_valid, - dst_dac_enable, - dst_dac_data, - dst_dac_valid -); + input dst_dac_enable, + output reg [15:0] dst_dac_data, + input dst_dac_valid); localparam RP_ID = 8'hA0; - parameter CHANNEL_ID = 0; - - input clk; - - input [31:0] control; - output [31:0] status; - - output src_dac_enable; - input [15:0] src_dac_data; - output src_dac_valid; - - input dst_dac_enable; - output [15:0] dst_dac_data; - input dst_dac_valid; - - reg src_dac_enable; - reg src_dac_valid; - reg [15:0] dst_dac_data; assign status = {24'h0, RP_ID}; diff --git a/library/prcfg/qpsk/prcfg_adc.v b/library/prcfg/qpsk/prcfg_adc.v index e46ffe883..ae5ffaa27 100644 --- a/library/prcfg/qpsk/prcfg_adc.v +++ b/library/prcfg/qpsk/prcfg_adc.v @@ -40,48 +40,30 @@ `timescale 1ns/1ns -module prcfg_adc ( - clk, +module prcfg_adc #( + + parameter CHANNEL_ID = 0, + parameter DATA_WIDTH = 32) ( + input clk, // control ports - control, - status, + input [31:0] control, + output reg [31:0] status, // FIFO interface - src_adc_valid, - src_adc_data, - src_adc_enable, + input src_adc_valid, + input [(DATA_WIDTH-1):0] src_adc_data, + input src_adc_enable, - dst_adc_valid, - dst_adc_data, - dst_adc_enable -); + output reg dst_adc_valid, + output reg [(DATA_WIDTH-1):0] dst_adc_data, + output reg dst_adc_enable); - parameter CHANNEL_ID = 0; - parameter DATA_WIDTH = 32; localparam SYMBOL_WIDTH = 2; localparam RP_ID = 8'hA2; - input clk; - - input [31:0] control; - output [31:0] status; - - input src_adc_valid; - input [(DATA_WIDTH-1):0] src_adc_data; - input src_adc_enable; - - output dst_adc_valid; - output [(DATA_WIDTH-1):0] dst_adc_data; - output dst_adc_enable; - - reg dst_adc_valid = 'h0; - reg [(DATA_WIDTH-1):0] dst_adc_data = 'h0; - reg dst_adc_enable = 'h0; - reg [ 7:0] adc_pn_data = 'hF1; - reg [31:0] status = 'h0; reg [ 3:0] mode = 'h0; reg [ 3:0] channel_sel = 'h0; diff --git a/library/prcfg/qpsk/prcfg_dac.v b/library/prcfg/qpsk/prcfg_dac.v index b4bb89811..c29fc1c7f 100644 --- a/library/prcfg/qpsk/prcfg_dac.v +++ b/library/prcfg/qpsk/prcfg_dac.v @@ -40,51 +40,34 @@ `timescale 1ns/1ns -module prcfg_dac( +module prcfg_dac#( - clk, + parameter CHANNEL_ID = 0, + parameter DATA_WIDTH = 16) ( + + input clk, // control ports - control, - status, + input [31:0] control, + output reg [31:0] status, // FIFO interface - src_dac_enable, - src_dac_data, - src_dac_valid, + output reg src_dac_enable, + input [(DATA_WIDTH-1):0] src_dac_data, + output reg src_dac_valid, - dst_dac_enable, - dst_dac_data, - dst_dac_valid -); + input dst_dac_enable, + output reg [(DATA_WIDTH-1):0] dst_dac_data, + input dst_dac_valid); - parameter CHANNEL_ID = 0; - parameter DATA_WIDTH = 16; localparam SYMBOL_WIDTH = 2; localparam RP_ID = 8'hA2; - input clk; - - input [31:0] control; - output [31:0] status; - - output src_dac_enable; - input [(DATA_WIDTH-1):0] src_dac_data; - output src_dac_valid; - - input dst_dac_enable; - output [(DATA_WIDTH-1):0] dst_dac_data; - input dst_dac_valid; - // output register to improve timing - reg [(DATA_WIDTH-1):0] dst_dac_data = 'h0; - reg src_dac_valid = 'h0; - reg src_dac_enable = 'h0; // internal registers reg [ 7:0] pn_data = 'hF2; - reg [31:0] status = 'h0; reg [ 3:0] mode = 'h0; // internal wires diff --git a/library/prcfg/qpsk/qpsk_demod.v b/library/prcfg/qpsk/qpsk_demod.v index 7d22110c1..a8da7624c 100644 --- a/library/prcfg/qpsk/qpsk_demod.v +++ b/library/prcfg/qpsk/qpsk_demod.v @@ -39,18 +39,11 @@ `timescale 1ns/1ns module qpsk_demod ( - clk, - data_qpsk_i, - data_qpsk_q, - data_valid, - data_output -); - - input clk; - input [15:0] data_qpsk_i; - input [15:0] data_qpsk_q; - input data_valid; - output [ 1:0] data_output; + input clk, + input [15:0] data_qpsk_i, + input [15:0] data_qpsk_q, + input data_valid, + output [ 1:0] data_output); wire [15:0] filtered_data_i; wire [15:0] filtered_data_q; diff --git a/library/prcfg/qpsk/qpsk_mod.v b/library/prcfg/qpsk/qpsk_mod.v index 4c6daf9ff..bdb376663 100644 --- a/library/prcfg/qpsk/qpsk_mod.v +++ b/library/prcfg/qpsk/qpsk_mod.v @@ -39,18 +39,11 @@ `timescale 1ns/1ns module qpsk_mod ( - clk, - data_input, - data_valid, - data_qpsk_i, - data_qpsk_q -); - - input clk; - input [ 1:0] data_input; - input data_valid; - output [15:0] data_qpsk_i; - output [15:0] data_qpsk_q; + input clk, + input [ 1:0] data_input, + input data_valid, + output [15:0] data_qpsk_i, + output [15:0] data_qpsk_q); wire [15:0] modulated_data_i; wire [15:0] modulated_data_q; diff --git a/library/util_adcfifo/util_adcfifo.v b/library/util_adcfifo/util_adcfifo.v index f1a2db291..148fc3801 100644 --- a/library/util_adcfifo/util_adcfifo.v +++ b/library/util_adcfifo/util_adcfifo.v @@ -39,54 +39,36 @@ `timescale 1ns/100ps -module util_adcfifo ( +module util_adcfifo #( + + parameter ADC_DATA_WIDTH = 256, + parameter DMA_DATA_WIDTH = 64, + parameter DMA_READY_ENABLE = 1, + parameter DMA_ADDRESS_WIDTH = 10) ( // fifo interface - adc_rst, - adc_clk, - adc_wr, - adc_wdata, - adc_wovf, + input adc_rst, + input adc_clk, + input adc_wr, + input [ADC_DATA_WIDTH-1:0] adc_wdata, + output adc_wovf, // dma interface - dma_clk, - dma_wr, - dma_wdata, - dma_wready, - dma_xfer_req, - dma_xfer_status); + input dma_clk, + output dma_wr, + output [DMA_DATA_WIDTH-1:0] dma_wdata, + input dma_wready, + input dma_xfer_req, + output [ 3:0] dma_xfer_status); - // parameters - - parameter ADC_DATA_WIDTH = 256; - parameter DMA_DATA_WIDTH = 64; - parameter DMA_READY_ENABLE = 1; - parameter DMA_ADDRESS_WIDTH = 10; localparam DMA_MEM_RATIO = ADC_DATA_WIDTH/DMA_DATA_WIDTH; localparam ADC_ADDRESS_WIDTH = (DMA_MEM_RATIO == 1) ? (DMA_ADDRESS_WIDTH) : (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) : ((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3)); localparam ADC_ADDR_LIMIT = (2**ADC_ADDRESS_WIDTH)-1; - // adc interface - - input adc_rst; - input adc_clk; - input adc_wr; - input [ADC_DATA_WIDTH-1:0] adc_wdata; - output adc_wovf; - - // dma interface - - input dma_clk; - output dma_wr; - output [DMA_DATA_WIDTH-1:0] dma_wdata; - input dma_wready; - input dma_xfer_req; - output [ 3:0] dma_xfer_status; - // internal registers reg [ 2:0] adc_xfer_req_m = 'd0; @@ -134,7 +116,6 @@ module util_adcfifo ( end end - always @(posedge adc_clk or posedge adc_rst) begin if (adc_rst == 1'b1) begin adc_wr_int <= 'd0; diff --git a/library/util_bsplit/util_bsplit.v b/library/util_bsplit/util_bsplit.v index ac97588da..0793c12d9 100755 --- a/library/util_bsplit/util_bsplit.v +++ b/library/util_bsplit/util_bsplit.v @@ -38,37 +38,24 @@ `timescale 1ns/100ps -module util_bsplit ( +module util_bsplit #( - data, + parameter CHANNEL_DATA_WIDTH = 1, + parameter NUM_OF_CHANNELS = 8) ( - split_data_0, - split_data_1, - split_data_2, - split_data_3, - split_data_4, - split_data_5, - split_data_6, - split_data_7); + input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] data, - // parameters + output [(CHANNEL_DATA_WIDTH-1):0] split_data_0, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_1, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_2, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_3, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_4, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_5, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_6, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_7); - parameter CHANNEL_DATA_WIDTH = 1; - parameter NUM_OF_CHANNELS = 8; localparam NUM_OF_CHANNELS_M = 9; - // interface - - input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] data; - output [(CHANNEL_DATA_WIDTH-1):0] split_data_0; - output [(CHANNEL_DATA_WIDTH-1):0] split_data_1; - output [(CHANNEL_DATA_WIDTH-1):0] split_data_2; - output [(CHANNEL_DATA_WIDTH-1):0] split_data_3; - output [(CHANNEL_DATA_WIDTH-1):0] split_data_4; - output [(CHANNEL_DATA_WIDTH-1):0] split_data_5; - output [(CHANNEL_DATA_WIDTH-1):0] split_data_6; - output [(CHANNEL_DATA_WIDTH-1):0] split_data_7; - // internal signals wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] data_s; diff --git a/library/util_ccat/util_ccat.v b/library/util_ccat/util_ccat.v index b0e4d2810..3bfa2b55f 100755 --- a/library/util_ccat/util_ccat.v +++ b/library/util_ccat/util_ccat.v @@ -38,37 +38,24 @@ `timescale 1ns/100ps -module util_ccat ( +module util_ccat #( - data_0, - data_1, - data_2, - data_3, - data_4, - data_5, - data_6, - data_7, + parameter CHANNEL_DATA_WIDTH = 1, + parameter NUM_OF_CHANNELS = 8) ( - ccat_data); + input [(CHANNEL_DATA_WIDTH-1):0] data_0, + input [(CHANNEL_DATA_WIDTH-1):0] data_1, + input [(CHANNEL_DATA_WIDTH-1):0] data_2, + input [(CHANNEL_DATA_WIDTH-1):0] data_3, + input [(CHANNEL_DATA_WIDTH-1):0] data_4, + input [(CHANNEL_DATA_WIDTH-1):0] data_5, + input [(CHANNEL_DATA_WIDTH-1):0] data_6, + input [(CHANNEL_DATA_WIDTH-1):0] data_7, - // parameters + output [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] ccat_data); - parameter CHANNEL_DATA_WIDTH = 1; - parameter NUM_OF_CHANNELS = 8; localparam NUM_OF_CHANNELS_M = 8; - // interface - - input [(CHANNEL_DATA_WIDTH-1):0] data_0; - input [(CHANNEL_DATA_WIDTH-1):0] data_1; - input [(CHANNEL_DATA_WIDTH-1):0] data_2; - input [(CHANNEL_DATA_WIDTH-1):0] data_3; - input [(CHANNEL_DATA_WIDTH-1):0] data_4; - input [(CHANNEL_DATA_WIDTH-1):0] data_5; - input [(CHANNEL_DATA_WIDTH-1):0] data_6; - input [(CHANNEL_DATA_WIDTH-1):0] data_7; - output [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] ccat_data; - // internal signals wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] data_s; diff --git a/library/util_cpack/util_cpack.v b/library/util_cpack/util_cpack.v index 39fe15157..e7f891160 100755 --- a/library/util_cpack/util_cpack.v +++ b/library/util_cpack/util_cpack.v @@ -37,88 +37,52 @@ `timescale 1ns/100ps -module util_cpack ( +module util_cpack #( + + parameter CHANNEL_DATA_WIDTH = 32, + parameter NUM_OF_CHANNELS = 8) ( // adc interface - adc_rst, - adc_clk, - adc_enable_0, - adc_valid_0, - adc_data_0, - adc_enable_1, - adc_valid_1, - adc_data_1, - adc_enable_2, - adc_valid_2, - adc_data_2, - adc_enable_3, - adc_valid_3, - adc_data_3, - adc_enable_4, - adc_valid_4, - adc_data_4, - adc_enable_5, - adc_valid_5, - adc_data_5, - adc_enable_6, - adc_valid_6, - adc_data_6, - adc_enable_7, - adc_valid_7, - adc_data_7, + input adc_rst, + input adc_clk, + input adc_enable_0, + input adc_valid_0, + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_0, + input adc_enable_1, + input adc_valid_1, + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_1, + input adc_enable_2, + input adc_valid_2, + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_2, + input adc_enable_3, + input adc_valid_3, + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_3, + input adc_enable_4, + input adc_valid_4, + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_4, + input adc_enable_5, + input adc_valid_5, + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_5, + input adc_enable_6, + input adc_valid_6, + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_6, + input adc_enable_7, + input adc_valid_7, + input [(CHANNEL_DATA_WIDTH-1):0] adc_data_7, // fifo interface - adc_valid, - adc_sync, - adc_data); + output reg adc_valid, + output reg adc_sync, + output reg [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] adc_data); - // parameters - - parameter CHANNEL_DATA_WIDTH = 32; - parameter NUM_OF_CHANNELS = 8; localparam SAMPLES_PCHANNEL = CHANNEL_DATA_WIDTH/16; localparam NUM_OF_CHANNELS_M = 8; localparam BUS_DATA_WIDTH = NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH; localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS; - // adc interface - - input adc_rst; - input adc_clk; - input adc_enable_0; - input adc_valid_0; - input [(CHANNEL_DATA_WIDTH-1):0] adc_data_0; - input adc_enable_1; - input adc_valid_1; - input [(CHANNEL_DATA_WIDTH-1):0] adc_data_1; - input adc_enable_2; - input adc_valid_2; - input [(CHANNEL_DATA_WIDTH-1):0] adc_data_2; - input adc_enable_3; - input adc_valid_3; - input [(CHANNEL_DATA_WIDTH-1):0] adc_data_3; - input adc_enable_4; - input adc_valid_4; - input [(CHANNEL_DATA_WIDTH-1):0] adc_data_4; - input adc_enable_5; - input adc_valid_5; - input [(CHANNEL_DATA_WIDTH-1):0] adc_data_5; - input adc_enable_6; - input adc_valid_6; - input [(CHANNEL_DATA_WIDTH-1):0] adc_data_6; - input adc_enable_7; - input adc_valid_7; - input [(CHANNEL_DATA_WIDTH-1):0] adc_data_7; - - // fifo interface - - output adc_valid; - output adc_sync; - output [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] adc_data; - // internal registers reg adc_valid_d = 'd0; @@ -126,9 +90,6 @@ module util_cpack ( reg adc_mux_valid = 'd0; reg [(NUM_OF_CHANNELS_M-1):0] adc_mux_enable = 'd0; reg [((SAMPLES_PCHANNEL*16*79)-1):0] adc_mux_data = 'd0; - reg adc_valid = 'd0; - reg adc_sync = 'd0; - reg [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] adc_data = 'd0; // internal signals diff --git a/library/util_cpack/util_cpack_dsf.v b/library/util_cpack/util_cpack_dsf.v index 773fac4f4..38e765675 100755 --- a/library/util_cpack/util_cpack_dsf.v +++ b/library/util_cpack/util_cpack_dsf.v @@ -37,46 +37,32 @@ `timescale 1ns/100ps -module util_cpack_dsf ( +module util_cpack_dsf #( + + parameter CHANNEL_DATA_WIDTH = 32, + parameter NUM_OF_CHANNELS_I = 4, + parameter NUM_OF_CHANNELS_M = 8, + parameter NUM_OF_CHANNELS_P = 4) ( // adc interface - adc_clk, - adc_valid, - adc_enable, - adc_data, + input adc_clk, + input adc_valid, + input adc_enable, + input [(I_WIDTH-1):0] adc_data, // dma interface - adc_dsf_valid, - adc_dsf_sync, - adc_dsf_data); + output reg adc_dsf_valid, + output reg adc_dsf_sync, + output reg [(P_WIDTH-1):0] adc_dsf_data); - // parameters - - parameter CHANNEL_DATA_WIDTH = 32; - parameter NUM_OF_CHANNELS_I = 4; - parameter NUM_OF_CHANNELS_M = 8; - parameter NUM_OF_CHANNELS_P = 4; localparam CH_DCNT = NUM_OF_CHANNELS_P - NUM_OF_CHANNELS_I; localparam I_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_I; localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P; localparam M_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_M; - // adc interface - - input adc_clk; - input adc_valid; - input adc_enable; - input [(I_WIDTH-1):0] adc_data; - - // dma interface - - output adc_dsf_valid; - output adc_dsf_sync; - output [(P_WIDTH-1):0] adc_dsf_data; - // internal registers reg [ 2:0] adc_samples_int = 'd0; @@ -85,9 +71,6 @@ module util_cpack_dsf ( reg adc_dsf_valid_int = 'd0; reg adc_dsf_sync_int = 'd0; reg [(P_WIDTH-1):0] adc_dsf_data_int = 'd0; - reg adc_dsf_valid = 'd0; - reg adc_dsf_sync = 'd0; - reg [(P_WIDTH-1):0] adc_dsf_data = 'd0; // internal signals diff --git a/library/util_cpack/util_cpack_mux.v b/library/util_cpack/util_cpack_mux.v index ca385824d..5ff0ce7bc 100755 --- a/library/util_cpack/util_cpack_mux.v +++ b/library/util_cpack/util_cpack_mux.v @@ -41,78 +41,34 @@ module util_cpack_mux ( // adc interface - adc_clk, - adc_valid, - adc_enable, - adc_data, + input adc_clk, + input adc_valid, + input [ 7:0] adc_enable, + input [127:0] adc_data, // fifo interface - adc_mux_valid, - adc_mux_enable_0, - adc_mux_data_0, - adc_mux_enable_1, - adc_mux_data_1, - adc_mux_enable_2, - adc_mux_data_2, - adc_mux_enable_3, - adc_mux_data_3, - adc_mux_enable_4, - adc_mux_data_4, - adc_mux_enable_5, - adc_mux_data_5, - adc_mux_enable_6, - adc_mux_data_6, - adc_mux_enable_7, - adc_mux_data_7); - - // adc interface - - input adc_clk; - input adc_valid; - input [ 7:0] adc_enable; - input [127:0] adc_data; - - // fifo interface - - output adc_mux_valid; - output adc_mux_enable_0; - output [ 15:0] adc_mux_data_0; - output adc_mux_enable_1; - output [ 31:0] adc_mux_data_1; - output adc_mux_enable_2; - output [ 47:0] adc_mux_data_2; - output adc_mux_enable_3; - output [ 63:0] adc_mux_data_3; - output adc_mux_enable_4; - output [ 79:0] adc_mux_data_4; - output adc_mux_enable_5; - output [ 95:0] adc_mux_data_5; - output adc_mux_enable_6; - output [111:0] adc_mux_data_6; - output adc_mux_enable_7; - output [127:0] adc_mux_data_7; + output reg adc_mux_valid, + output reg adc_mux_enable_0, + output reg [ 15:0] adc_mux_data_0, + output reg adc_mux_enable_1, + output reg [ 31:0] adc_mux_data_1, + output reg adc_mux_enable_2, + output reg [ 47:0] adc_mux_data_2, + output reg adc_mux_enable_3, + output reg [ 63:0] adc_mux_data_3, + output reg adc_mux_enable_4, + output reg [ 79:0] adc_mux_data_4, + output reg adc_mux_enable_5, + output reg [ 95:0] adc_mux_data_5, + output reg adc_mux_enable_6, + output reg [111:0] adc_mux_data_6, + output reg adc_mux_enable_7, + output reg [127:0] adc_mux_data_7); // internal registers reg adc_valid_d = 'd0; - reg adc_mux_valid = 'd0; - reg adc_mux_enable_0 = 'd0; - reg adc_mux_enable_1 = 'd0; - reg adc_mux_enable_2 = 'd0; - reg adc_mux_enable_3 = 'd0; - reg adc_mux_enable_4 = 'd0; - reg adc_mux_enable_5 = 'd0; - reg adc_mux_enable_6 = 'd0; - reg adc_mux_enable_7 = 'd0; - reg [ 15:0] adc_mux_data_0 = 'd0; - reg [ 31:0] adc_mux_data_1 = 'd0; - reg [ 47:0] adc_mux_data_2 = 'd0; - reg [ 63:0] adc_mux_data_3 = 'd0; - reg [ 79:0] adc_mux_data_4 = 'd0; - reg [ 95:0] adc_mux_data_5 = 'd0; - reg [111:0] adc_mux_data_6 = 'd0; - reg [127:0] adc_mux_data_7 = 'd0; reg adc_mux_enable_0_0 = 'd0; reg [ 15:0] adc_mux_data_0_0 = 'd0; reg adc_mux_enable_1_0 = 'd0; diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index 32273a56b..2da72bc30 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -39,57 +39,32 @@ `timescale 1ns/100ps -module util_dacfifo ( +module util_dacfifo #( + + parameter ADDRESS_WIDTH = 6, + parameter DATA_WIDTH = 128) ( // DMA interface - dma_clk, - dma_rst, - dma_valid, - dma_data, - dma_ready, - dma_xfer_req, - dma_xfer_last, + input dma_clk, + input dma_rst, + input dma_valid, + input [(DATA_WIDTH-1):0] dma_data, + output reg dma_ready, + input dma_xfer_req, + input dma_xfer_last, // DAC interface - dac_clk, - dac_rst, - dac_valid, - dac_data, - dac_dunf, - dac_xfer_out, + input dac_clk, + input dac_rst, + input dac_valid, + output reg [(DATA_WIDTH-1):0] dac_data, + output reg dac_dunf, + output reg dac_xfer_out, - bypass -); + input bypass); - // depth of the FIFO - - parameter ADDRESS_WIDTH = 6; - parameter DATA_WIDTH = 128; - - // port definitions - - // DMA interface - - input dma_clk; - input dma_rst; - input dma_valid; - input [(DATA_WIDTH-1):0] dma_data; - output dma_ready; - input dma_xfer_req; - input dma_xfer_last; - - // DAC interface - - input dac_clk; - input dac_rst; - input dac_valid; - output [(DATA_WIDTH-1):0] dac_data; - output dac_dunf; - output dac_xfer_out; - - input bypass; localparam FIFO_THRESHOLD_HI = {(ADDRESS_WIDTH){1'b1}} - 4; @@ -102,7 +77,6 @@ module util_dacfifo ( reg [(ADDRESS_WIDTH-1):0] dma_raddr_m2 = 'b0; reg [(ADDRESS_WIDTH-1):0] dma_raddr = 'b0; reg [(ADDRESS_WIDTH-1):0] dma_addr_diff = 'b0; - reg dma_ready = 1'b0; reg dma_ready_fifo = 1'b0; reg dma_ready_bypass = 1'b0; reg dma_bypass = 1'b0; @@ -119,16 +93,13 @@ module util_dacfifo ( reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m1 = 'b0; reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m2 = 'b0; reg [(ADDRESS_WIDTH-1):0] dac_lastaddr = 'b0; - reg [(DATA_WIDTH-1):0] dac_data = 'b0; reg dac_mem_ready = 1'b0; - reg dac_xfer_out = 1'b0; reg dac_xfer_out_fifo = 1'b0; reg dac_xfer_out_fifo_m1 = 1'b0; reg dac_xfer_out_bypass = 1'b0; reg dac_xfer_out_bypass_m1 = 1'b0; reg dac_bypass = 1'b0; reg dac_bypass_m1 = 1'b0; - reg dac_dunf = 1'b0; // internal wires diff --git a/library/util_extract/util_extract.v b/library/util_extract/util_extract.v index 155a49558..3018a522d 100644 --- a/library/util_extract/util_extract.v +++ b/library/util_extract/util_extract.v @@ -37,35 +37,27 @@ `timescale 1ns/100ps -module util_extract ( +module util_extract #( - clk, + parameter CHANNELS = 2, + parameter DW = CHANNELS * 16) ( - data_in, - data_in_trigger, - data_valid, + input clk, - data_out, - trigger_out + input [DW-1:0] data_in, + input [DW-1:0] data_in_trigger, + input data_valid, + output [DW-1:0] data_out, + output reg trigger_out ); - parameter CHANNELS = 2; - parameter DW = CHANNELS * 16; - input clk; - input [DW-1:0] data_in; - input [DW-1:0] data_in_trigger; - input data_valid; - - output [DW-1:0] data_out; - output trigger_out; // loop variables genvar n; - reg trigger_out; reg trigger_d1; wire [15:0] trigger; // 16 maximum channels diff --git a/library/util_gmii_to_rgmii/mdc_mdio.v b/library/util_gmii_to_rgmii/mdc_mdio.v index f74094d90..6c91453d4 100644 --- a/library/util_gmii_to_rgmii/mdc_mdio.v +++ b/library/util_gmii_to_rgmii/mdc_mdio.v @@ -35,22 +35,17 @@ // *************************************************************************** // *************************************************************************** -module mdc_mdio ( +module mdc_mdio #( - mdio_mdc, - mdio_in_w, - mdio_in_r, + parameter PHY_AD = 5'b10000) ( - speed_select, - duplex_mode); + input mdio_mdc, + input mdio_in_w, + input mdio_in_r, - parameter PHY_AD = 5'b10000; + output reg [ 1:0] speed_select, + output reg duplex_mode); - input mdio_mdc; - input mdio_in_w; - input mdio_in_r; - output [ 1:0] speed_select; - output duplex_mode; localparam IDLE = 2'b01; localparam ACQUIRE = 2'b10; @@ -62,8 +57,6 @@ module mdc_mdio ( reg [31:0] data_in = 32'h0; reg [31:0] data_in_r = 32'h0; reg [ 5:0] data_counter = 6'h0; - reg [ 1:0] speed_select = 2'h0; - reg duplex_mode = 1'h0; assign preamble = &data_in; diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v index 80f72703b..470fc534e 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v @@ -38,70 +38,42 @@ // specific for MOTCON2 ADI board // works correctly if the PHY is set with Autonegotiation on -module util_gmii_to_rgmii ( +module util_gmii_to_rgmii #( - clk_20m, - clk_25m, - clk_125m, - idelayctrl_clk, + parameter PHY_AD = 5'b10000, + parameter IODELAY_CTRL = 1'b0, + parameter IDELAY_VALUE = 18, + parameter IODELAY_GROUP = "if_delay_group") ( - reset, + input clk_20m, + input clk_25m, + input clk_125m, + input idelayctrl_clk, - rgmii_td, - rgmii_tx_ctl, - rgmii_txc, - rgmii_rd, - rgmii_rx_ctl, - rgmii_rxc, + input reset, - mdio_mdc, - mdio_in_w, - mdio_in_r, + output [ 3:0] rgmii_td, + output rgmii_tx_ctl, + output rgmii_txc, + input [ 3:0] rgmii_rd, + input rgmii_rx_ctl, + input rgmii_rxc, - gmii_txd, - gmii_tx_en, - gmii_tx_er, - gmii_tx_clk, - gmii_crs, - gmii_col, - gmii_rxd, - gmii_rx_dv, - gmii_rx_er, - gmii_rx_clk); + input mdio_mdc, + input mdio_in_w, + input mdio_in_r, - parameter PHY_AD = 5'b10000; - parameter IODELAY_CTRL = 1'b0; - parameter IDELAY_VALUE = 18; - parameter IODELAY_GROUP = "if_delay_group"; + input [ 7:0] gmii_txd, + input gmii_tx_en, + input gmii_tx_er, + output gmii_tx_clk, + output reg gmii_crs, + output reg gmii_col, + output reg [ 7:0] gmii_rxd, + output reg gmii_rx_dv, + output reg gmii_rx_er, + output gmii_rx_clk); - input clk_20m; - input clk_25m; - input clk_125m; - input idelayctrl_clk; - - input reset; - - output [ 3:0] rgmii_td; - output rgmii_tx_ctl; - output rgmii_txc; - input [ 3:0] rgmii_rd; - input rgmii_rx_ctl; - input rgmii_rxc; - - input mdio_mdc; - input mdio_in_w; - input mdio_in_r; - - input [ 7:0] gmii_txd; - input gmii_tx_en; - input gmii_tx_er; - output gmii_tx_clk; - output gmii_crs; - output gmii_col; - output [ 7:0] gmii_rxd; - output gmii_rx_dv; - output gmii_rx_er; - output gmii_rx_clk; // wires wire clk_2_5m; @@ -127,12 +99,6 @@ module util_gmii_to_rgmii ( reg rgmii_tx_ctl_r; reg [ 3:0] gmii_txd_low; - reg gmii_col; - reg gmii_crs; - - reg [ 7:0] gmii_rxd; - reg gmii_rx_dv; - reg gmii_rx_er; reg idelayctrl_reset; reg [ 3:0] idelay_reset_cnt; diff --git a/library/util_mfifo/util_mfifo.v b/library/util_mfifo/util_mfifo.v index 92bbe4b12..9f07b5cd9 100644 --- a/library/util_mfifo/util_mfifo.v +++ b/library/util_mfifo/util_mfifo.v @@ -37,69 +37,40 @@ `timescale 1ns/100ps -module util_mfifo ( +module util_mfifo #( + + parameter NUM_OF_CHANNELS = 4, + parameter DIN_DATA_WIDTH = 32, + parameter ADDRESS_WIDTH = 8) ( // d-in interface - din_rst, - din_clk, - din_valid, - din_data_0, - din_data_1, - din_data_2, - din_data_3, - din_data_4, - din_data_5, - din_data_6, - din_data_7, + input din_rst, + input din_clk, + input din_valid, + input [DIN_DATA_WIDTH-1:0] din_data_0, + input [DIN_DATA_WIDTH-1:0] din_data_1, + input [DIN_DATA_WIDTH-1:0] din_data_2, + input [DIN_DATA_WIDTH-1:0] din_data_3, + input [DIN_DATA_WIDTH-1:0] din_data_4, + input [DIN_DATA_WIDTH-1:0] din_data_5, + input [DIN_DATA_WIDTH-1:0] din_data_6, + input [DIN_DATA_WIDTH-1:0] din_data_7, // d-out interface - dout_rst, - dout_clk, - dout_valid, - dout_data_0, - dout_data_1, - dout_data_2, - dout_data_3, - dout_data_4, - dout_data_5, - dout_data_6, - dout_data_7); + input dout_rst, + input dout_clk, + output reg dout_valid, + output [15:0] dout_data_0, + output [15:0] dout_data_1, + output [15:0] dout_data_2, + output [15:0] dout_data_3, + output [15:0] dout_data_4, + output [15:0] dout_data_5, + output [15:0] dout_data_6, + output [15:0] dout_data_7); - // parameters - - parameter NUM_OF_CHANNELS = 4; - parameter DIN_DATA_WIDTH = 32; - parameter ADDRESS_WIDTH = 8; - - // d-in interface - - input din_rst; - input din_clk; - input din_valid; - input [DIN_DATA_WIDTH-1:0] din_data_0; - input [DIN_DATA_WIDTH-1:0] din_data_1; - input [DIN_DATA_WIDTH-1:0] din_data_2; - input [DIN_DATA_WIDTH-1:0] din_data_3; - input [DIN_DATA_WIDTH-1:0] din_data_4; - input [DIN_DATA_WIDTH-1:0] din_data_5; - input [DIN_DATA_WIDTH-1:0] din_data_6; - input [DIN_DATA_WIDTH-1:0] din_data_7; - - // dout interface - - input dout_rst; - input dout_clk; - output dout_valid; - output [15:0] dout_data_0; - output [15:0] dout_data_1; - output [15:0] dout_data_2; - output [15:0] dout_data_3; - output [15:0] dout_data_4; - output [15:0] dout_data_5; - output [15:0] dout_data_6; - output [15:0] dout_data_7; // internal registers @@ -119,7 +90,6 @@ module util_mfifo ( reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0; reg dout_enable = 'd0; reg dout_toggle = 'd0; - reg dout_valid = 'd0; reg [(DIN_DATA_WIDTH-1):0] dout_rdata_0 = 'd0; reg [(DIN_DATA_WIDTH-1):0] dout_rdata_1 = 'd0; reg [(DIN_DATA_WIDTH-1):0] dout_rdata_2 = 'd0; diff --git a/library/util_pmod_adc/util_pmod_adc.v b/library/util_pmod_adc/util_pmod_adc.v index b0d59b83f..3866b988a 100644 --- a/library/util_pmod_adc/util_pmod_adc.v +++ b/library/util_pmod_adc/util_pmod_adc.v @@ -58,36 +58,34 @@ `timescale 1ns/1ns -module util_pmod_adc ( +module util_pmod_adc #( + + parameter FPGA_CLOCK_MHZ = 100, + parameter ADC_CONVST_NS = 100, + parameter ADC_CONVERT_NS = 650, + parameter ADC_TQUIET_NS = 60, + parameter SPI_WORD_LENGTH = 12, + parameter ADC_RESET_LENGTH = 3, + parameter ADC_CLK_DIVIDE = 16) ( // clock and reset signals - clk, - resetn, + input clk, + input resetn, // dma interface - adc_data, - adc_valid, - adc_dbg, + output reg [15:0] adc_data, + output reg adc_valid, + output reg [24:0] adc_dbg, // adc interface (clk, data, cs and conversion start) - adc_sdo, - adc_sclk, - adc_cs_n, - adc_convst_n -); + input adc_sdo, + output adc_sclk, + output reg adc_cs_n, + output reg adc_convst_n); - // parameters and local parameters - parameter FPGA_CLOCK_MHZ = 100; // FPGA clock frequency [MHz] - parameter ADC_CONVST_NS = 100; // minimum time to keep /CONVST low is 10ns, default is 100ns - parameter ADC_CONVERT_NS = 650; // conversion time [ns] - parameter ADC_TQUIET_NS = 60; // quite time between the last SPI read and next conversion start - parameter SPI_WORD_LENGTH = 12; - parameter ADC_RESET_LENGTH = 3; - parameter ADC_CLK_DIVIDE = 16; - // ADC states localparam ADC_POWERUP = 0; localparam ADC_SW_RESET = 1; localparam ADC_IDLE = 2; @@ -97,37 +95,13 @@ module util_pmod_adc ( localparam ADC_DATA_VALID = 6; localparam ADC_TQUIET = 7; - // ADC timing - localparam [15:0] FPGA_CLOCK_PERIOD_NS = 1000 / FPGA_CLOCK_MHZ; localparam [15:0] ADC_CONVST_CNT = ADC_CONVST_NS / FPGA_CLOCK_PERIOD_NS; localparam [15:0] ADC_CONVERT_CNT = ADC_CONVERT_NS / FPGA_CLOCK_PERIOD_NS; localparam [15:0] ADC_TQUITE_CNT = ADC_TQUIET_NS / FPGA_CLOCK_PERIOD_NS; - // clock and reset signals - - input clk; // system clock (100 MHz) - input resetn; // active low reset signal - - // dma interface - - output [15:0] adc_data; - output adc_valid; - output [24:0] adc_dbg; - - // adc interface - - input adc_sdo; - output adc_sclk; - output adc_cs_n; - output adc_convst_n; - // Internal registers - reg [15:0] adc_data = 16'b0; - reg adc_valid = 1'b0; - reg [24:0] adc_dbg = 25'b0; - reg [ 2:0] adc_state = 3'b0; // current state for the ADC control state machine reg [ 2:0] adc_next_state = 3'b0; // next state for the ADC control state machine @@ -138,9 +112,7 @@ module util_pmod_adc ( reg [15:0] sclk_clk_cnt_m1 = 16'b0; reg [7:0] adc_clk_cnt = 8'h0; - reg adc_convst_n = 1'b1; reg adc_clk_en = 1'b0; - reg adc_cs_n = 1'b1; reg adc_sw_reset = 1'b0; reg data_rd_ready = 1'b0; reg adc_spi_clk = 1'b0; diff --git a/library/util_pmod_fmeter/util_pmod_fmeter.v b/library/util_pmod_fmeter/util_pmod_fmeter.v index 8cae03366..457d8cd3e 100644 --- a/library/util_pmod_fmeter/util_pmod_fmeter.v +++ b/library/util_pmod_fmeter/util_pmod_fmeter.v @@ -37,67 +37,36 @@ // *************************************************************************** // *************************************************************************** -module util_pmod_fmeter ( +module util_pmod_fmeter #( - ref_clk, - square_signal, + parameter ID = 0) ( + + input ref_clk, + input square_signal, // axi interface - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready, - s_axi_awprot, - s_axi_arprot); - - // parameters - - parameter ID = 0; - - // physical interface - - input ref_clk; - input square_signal; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - input [ 2:0] s_axi_awprot; - input [ 2:0] s_axi_arprot; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); // internal signals diff --git a/library/util_pmod_fmeter/util_pmod_fmeter_core.v b/library/util_pmod_fmeter/util_pmod_fmeter_core.v index 92285da80..e1495dec4 100644 --- a/library/util_pmod_fmeter/util_pmod_fmeter_core.v +++ b/library/util_pmod_fmeter/util_pmod_fmeter_core.v @@ -38,19 +38,13 @@ // *************************************************************************** module util_pmod_fmeter_core ( - ref_clk, - reset, - square_signal, - signal_freq); - - input ref_clk; - input reset; - input square_signal; - output [31:0] signal_freq; + input ref_clk, + input reset, + input square_signal, + output reg [31:0] signal_freq); // registers - reg [31:0] signal_freq = 'h0; reg [31:0] signal_freq_counter = 'h0; reg [ 2:0] square_signal_buf = 'h0; diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v index e0b35a19b..f0fd82568 100644 --- a/library/util_rfifo/util_rfifo.v +++ b/library/util_rfifo/util_rfifo.v @@ -37,74 +37,73 @@ `timescale 1ns/100ps -module util_rfifo ( +module util_rfifo #( + + parameter NUM_OF_CHANNELS = 4, + parameter DIN_DATA_WIDTH = 32, + parameter DOUT_DATA_WIDTH = 64, + parameter DIN_ADDRESS_WIDTH = 8) ( // d-in interface - din_rstn, - din_clk, - din_enable_0, - din_valid_0, - din_data_0, - din_enable_1, - din_valid_1, - din_data_1, - din_enable_2, - din_valid_2, - din_data_2, - din_enable_3, - din_valid_3, - din_data_3, - din_enable_4, - din_valid_4, - din_data_4, - din_enable_5, - din_valid_5, - din_data_5, - din_enable_6, - din_valid_6, - din_data_6, - din_enable_7, - din_valid_7, - din_data_7, - din_unf, + input din_rstn, + input din_clk, + output din_enable_0, + output din_valid_0, + input [DIN_DATA_WIDTH-1:0] din_data_0, + output din_enable_1, + output din_valid_1, + input [DIN_DATA_WIDTH-1:0] din_data_1, + output din_enable_2, + output din_valid_2, + input [DIN_DATA_WIDTH-1:0] din_data_2, + output din_enable_3, + output din_valid_3, + input [DIN_DATA_WIDTH-1:0] din_data_3, + output din_enable_4, + output din_valid_4, + input [DIN_DATA_WIDTH-1:0] din_data_4, + output din_enable_5, + output din_valid_5, + input [DIN_DATA_WIDTH-1:0] din_data_5, + output din_enable_6, + output din_valid_6, + input [DIN_DATA_WIDTH-1:0] din_data_6, + output din_enable_7, + output din_valid_7, + input [DIN_DATA_WIDTH-1:0] din_data_7, + input din_unf, // d-out interface - dout_rst, - dout_clk, - dout_enable_0, - dout_valid_0, - dout_data_0, - dout_enable_1, - dout_valid_1, - dout_data_1, - dout_enable_2, - dout_valid_2, - dout_data_2, - dout_enable_3, - dout_valid_3, - dout_data_3, - dout_enable_4, - dout_valid_4, - dout_data_4, - dout_enable_5, - dout_valid_5, - dout_data_5, - dout_enable_6, - dout_valid_6, - dout_data_6, - dout_enable_7, - dout_valid_7, - dout_data_7, - dout_unf); + input dout_rst, + input dout_clk, + input dout_enable_0, + input dout_valid_0, + output [DOUT_DATA_WIDTH-1:0] dout_data_0, + input dout_enable_1, + input dout_valid_1, + output [DOUT_DATA_WIDTH-1:0] dout_data_1, + input dout_enable_2, + input dout_valid_2, + output [DOUT_DATA_WIDTH-1:0] dout_data_2, + input dout_enable_3, + input dout_valid_3, + output [DOUT_DATA_WIDTH-1:0] dout_data_3, + input dout_enable_4, + input dout_valid_4, + output [DOUT_DATA_WIDTH-1:0] dout_data_4, + input dout_enable_5, + input dout_valid_5, + output [DOUT_DATA_WIDTH-1:0] dout_data_5, + input dout_enable_6, + input dout_valid_6, + output [DOUT_DATA_WIDTH-1:0] dout_data_6, + input dout_enable_7, + input dout_valid_7, + output [DOUT_DATA_WIDTH-1:0] dout_data_7, + output reg dout_unf); - // parameters - - parameter NUM_OF_CHANNELS = 4; - parameter DIN_DATA_WIDTH = 32; - parameter DOUT_DATA_WIDTH = 64; - parameter DIN_ADDRESS_WIDTH = 8; localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH; localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 5) ? DIN_ADDRESS_WIDTH : 5; @@ -112,66 +111,6 @@ module util_rfifo ( localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8; localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8; - // d-in interface - - input din_rstn; - input din_clk; - output din_enable_0; - output din_valid_0; - input [DIN_DATA_WIDTH-1:0] din_data_0; - output din_enable_1; - output din_valid_1; - input [DIN_DATA_WIDTH-1:0] din_data_1; - output din_enable_2; - output din_valid_2; - input [DIN_DATA_WIDTH-1:0] din_data_2; - output din_enable_3; - output din_valid_3; - input [DIN_DATA_WIDTH-1:0] din_data_3; - output din_enable_4; - output din_valid_4; - input [DIN_DATA_WIDTH-1:0] din_data_4; - output din_enable_5; - output din_valid_5; - input [DIN_DATA_WIDTH-1:0] din_data_5; - output din_enable_6; - output din_valid_6; - input [DIN_DATA_WIDTH-1:0] din_data_6; - output din_enable_7; - output din_valid_7; - input [DIN_DATA_WIDTH-1:0] din_data_7; - input din_unf; - - // dout interface - - input dout_rst; - input dout_clk; - input dout_enable_0; - input dout_valid_0; - output [DOUT_DATA_WIDTH-1:0] dout_data_0; - input dout_enable_1; - input dout_valid_1; - output [DOUT_DATA_WIDTH-1:0] dout_data_1; - input dout_enable_2; - input dout_valid_2; - output [DOUT_DATA_WIDTH-1:0] dout_data_2; - input dout_enable_3; - input dout_valid_3; - output [DOUT_DATA_WIDTH-1:0] dout_data_3; - input dout_enable_4; - input dout_valid_4; - output [DOUT_DATA_WIDTH-1:0] dout_data_4; - input dout_enable_5; - input dout_valid_5; - output [DOUT_DATA_WIDTH-1:0] dout_data_5; - input dout_enable_6; - input dout_valid_6; - output [DOUT_DATA_WIDTH-1:0] dout_data_6; - input dout_enable_7; - input dout_valid_7; - output [DOUT_DATA_WIDTH-1:0] dout_data_7; - output dout_unf; - // internal registers reg [(DATA_WIDTH-1):0] din_wdata = 'd0; @@ -194,7 +133,6 @@ module util_rfifo ( reg [(ADDRESS_WIDTH-4):0] dout_rinit = 'd0; reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0; reg dout_unf_m1 = 'd0; - reg dout_unf = 'd0; // internal signals diff --git a/library/util_tdd_sync/util_tdd_sync.v b/library/util_tdd_sync/util_tdd_sync.v index e75ce0687..0099eb73e 100644 --- a/library/util_tdd_sync/util_tdd_sync.v +++ b/library/util_tdd_sync/util_tdd_sync.v @@ -45,29 +45,20 @@ `timescale 1ns/1ps -module util_tdd_sync ( - clk, - rstn, +module util_tdd_sync #( - sync_mode, + parameter TDD_SYNC_PERIOD = 100000000) ( + input clk, + input rstn, - sync_in, - sync_out -); + input sync_mode, - input clk; - input rstn; + input sync_in, + output reg sync_out); - input sync_mode; - - input sync_in; - output sync_out; - - parameter TDD_SYNC_PERIOD = 100000000; reg sync_mode_d1 = 1'b0; reg sync_mode_d2 = 1'b0; - reg sync_out = 1'b0; wire sync_internal; wire sync_external; diff --git a/library/util_upack/util_upack.v b/library/util_upack/util_upack.v index 6eadaaf7a..c6516875e 100755 --- a/library/util_upack/util_upack.v +++ b/library/util_upack/util_upack.v @@ -37,57 +37,56 @@ `timescale 1ns/100ps -module util_upack ( +module util_upack #( + + parameter CHANNEL_DATA_WIDTH = 32, + parameter NUM_OF_CHANNELS = 8) ( // dac interface - dac_clk, - dac_enable_0, - dac_valid_0, - dac_data_0, - upack_valid_0, - dac_enable_1, - dac_valid_1, - dac_data_1, - upack_valid_1, - dac_enable_2, - dac_valid_2, - dac_data_2, - upack_valid_2, - dac_enable_3, - dac_valid_3, - dac_data_3, - upack_valid_3, - dac_enable_4, - dac_valid_4, - dac_data_4, - upack_valid_4, - dac_enable_5, - dac_valid_5, - dac_data_5, - upack_valid_5, - dac_enable_6, - dac_valid_6, - dac_data_6, - upack_valid_6, - dac_enable_7, - dac_valid_7, - dac_data_7, - upack_valid_7, + input dac_clk, + input dac_enable_0, + input dac_valid_0, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_0, + output upack_valid_0, + input dac_enable_1, + input dac_valid_1, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_1, + output upack_valid_1, + input dac_enable_2, + input dac_valid_2, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_2, + output upack_valid_2, + input dac_enable_3, + input dac_valid_3, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_3, + output upack_valid_3, + input dac_enable_4, + input dac_valid_4, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_4, + output upack_valid_4, + input dac_enable_5, + input dac_valid_5, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_5, + output upack_valid_5, + input dac_enable_6, + input dac_valid_6, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_6, + output upack_valid_6, + input dac_enable_7, + input dac_valid_7, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_7, + output upack_valid_7, - dma_xfer_in, - dac_xfer_out, + input dma_xfer_in, + output reg dac_xfer_out, // fifo interface - dac_valid, - dac_sync, - dac_data); + output reg dac_valid, + output reg dac_sync, + input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] dac_data); - // parameters - - parameter CHANNEL_DATA_WIDTH = 32; - parameter NUM_OF_CHANNELS = 8; localparam NUM_OF_CHANNELS_M = 8; localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS; @@ -95,55 +94,8 @@ module util_upack ( localparam M_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_M; localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P; - // dac interface - - input dac_clk; - input dac_enable_0; - input dac_valid_0; - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_0; - output upack_valid_0; - input dac_enable_1; - input dac_valid_1; - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_1; - output upack_valid_1; - input dac_enable_2; - input dac_valid_2; - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_2; - output upack_valid_2; - input dac_enable_3; - input dac_valid_3; - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_3; - output upack_valid_3; - input dac_enable_4; - input dac_valid_4; - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_4; - output upack_valid_4; - input dac_enable_5; - input dac_valid_5; - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_5; - output upack_valid_5; - input dac_enable_6; - input dac_valid_6; - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_6; - output upack_valid_6; - input dac_enable_7; - input dac_valid_7; - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_7; - output upack_valid_7; - - input dma_xfer_in; - output dac_xfer_out; - - // fifo interface - - output dac_valid; - output dac_sync; - input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] dac_data; - // internal registers - reg dac_valid = 'd0; - reg dac_sync = 'd0; reg [(M_WIDTH-1):0] dac_dsf_data = 'd0; reg [ 7:0] dac_dmx_enable = 'd0; reg xfer_valid_d1; @@ -151,7 +103,6 @@ module util_upack ( reg xfer_valid_d3; reg xfer_valid_d4; reg xfer_valid_d5; - reg dac_xfer_out; // internal signals @@ -172,7 +123,6 @@ module util_upack ( genvar n; - // parameter breaks here (max. 8) -- reduce won't work across 2d arrays. assign dac_valid_s = dac_valid_7 | dac_valid_6 | dac_valid_5 | dac_valid_4 | dac_valid_3 | dac_valid_2 | dac_valid_1 | dac_valid_0; diff --git a/library/util_upack/util_upack_dmx.v b/library/util_upack/util_upack_dmx.v index b0560af7f..5b7c6e175 100755 --- a/library/util_upack/util_upack_dmx.v +++ b/library/util_upack/util_upack_dmx.v @@ -41,51 +41,24 @@ module util_upack_dmx ( // dac interface - dac_clk, - dac_enable, - dac_data_0, - dac_data_1, - dac_data_2, - dac_data_3, - dac_data_4, - dac_data_5, - dac_data_6, - dac_data_7, + input dac_clk, + input [ 7:0] dac_enable, + output reg [ 15:0] dac_data_0, + output reg [ 15:0] dac_data_1, + output reg [ 15:0] dac_data_2, + output reg [ 15:0] dac_data_3, + output reg [ 15:0] dac_data_4, + output reg [ 15:0] dac_data_5, + output reg [ 15:0] dac_data_6, + output reg [ 15:0] dac_data_7, // dmx interface - dac_dmx_enable, - dac_dsf_data); - - // dac interface - - input dac_clk; - input [ 7:0] dac_enable; - output [ 15:0] dac_data_0; - output [ 15:0] dac_data_1; - output [ 15:0] dac_data_2; - output [ 15:0] dac_data_3; - output [ 15:0] dac_data_4; - output [ 15:0] dac_data_5; - output [ 15:0] dac_data_6; - output [ 15:0] dac_data_7; - - // dmx interface - - output [ 7:0] dac_dmx_enable; - input [127:0] dac_dsf_data; + output reg [ 7:0] dac_dmx_enable, + input [127:0] dac_dsf_data); // internal registers - reg [ 7:0] dac_dmx_enable = 'd0; - reg [ 15:0] dac_data_0 = 'd0; - reg [ 15:0] dac_data_1 = 'd0; - reg [ 15:0] dac_data_2 = 'd0; - reg [ 15:0] dac_data_3 = 'd0; - reg [ 15:0] dac_data_4 = 'd0; - reg [ 15:0] dac_data_5 = 'd0; - reg [ 15:0] dac_data_6 = 'd0; - reg [ 15:0] dac_data_7 = 'd0; reg dac_dmx_enable_0 = 'd0; reg [ 15:0] dac_dmx_data_0_0 = 'd0; reg [ 15:0] dac_dmx_data_1_0 = 'd0; diff --git a/library/util_upack/util_upack_dsf.v b/library/util_upack/util_upack_dsf.v index c5ee8ed61..0d2a13a75 100755 --- a/library/util_upack/util_upack_dsf.v +++ b/library/util_upack/util_upack_dsf.v @@ -37,27 +37,26 @@ `timescale 1ns/100ps -module util_upack_dsf ( +module util_upack_dsf #( + + parameter NUM_OF_CHANNELS_P = 4, + parameter NUM_OF_CHANNELS_M = 8, + parameter CHANNEL_DATA_WIDTH = 32, + parameter NUM_OF_CHANNELS_O = 4) ( // dac interface - dac_clk, - dac_valid, - dac_data, + input dac_clk, + input dac_valid, + input [(P_WIDTH-1):0] dac_data, // dmx interface - dac_dmx_enable, - dac_dsf_valid, - dac_dsf_sync, - dac_dsf_data); + input dac_dmx_enable, + output reg dac_dsf_valid, + output reg dac_dsf_sync, + output reg [(M_WIDTH-1):0] dac_dsf_data); - // parameters - - parameter NUM_OF_CHANNELS_P = 4; - parameter NUM_OF_CHANNELS_M = 8; - parameter CHANNEL_DATA_WIDTH = 32; - parameter NUM_OF_CHANNELS_O = 4; localparam CH_SCNT = CHANNEL_DATA_WIDTH/16; localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P; @@ -66,31 +65,15 @@ module util_upack_dsf ( localparam E_WIDTH = CHANNEL_DATA_WIDTH*(NUM_OF_CHANNELS_M+1); localparam CH_DCNT = NUM_OF_CHANNELS_P - NUM_OF_CHANNELS_O; - // dac interface - - input dac_clk; - input dac_valid; - input [(P_WIDTH-1):0] dac_data; - - // dmx interface - - input dac_dmx_enable; - output dac_dsf_valid; - output dac_dsf_sync; - output [(M_WIDTH-1):0] dac_dsf_data; - // internal registers reg dac_dmx_valid = 'd0; - reg dac_dsf_valid = 'd0; - reg dac_dsf_sync = 'd0; reg [ 2:0] dac_samples_int = 'd0; reg dac_dmx_valid_d = 'd0; reg dac_dsf_valid_d = 'd0; reg [ 2:0] dac_samples_int_d = 'd0; reg [(M_WIDTH-1):0] dac_data_int = 'd0; reg [(M_WIDTH-1):0] dac_dsf_data_int = 'd0; - reg [(M_WIDTH-1):0] dac_dsf_data = 'd0; reg dac_valid_d1 = 'd0; // internal signals @@ -148,7 +131,6 @@ module util_upack_dsf ( assign dac_samples_int_s = (dac_dsf_valid == 1'b1) ? (dac_samples_int + CH_DCNT) : ((dac_samples_int >= NUM_OF_CHANNELS_O) ? (dac_samples_int - NUM_OF_CHANNELS_O) : dac_samples_int); - always @(posedge dac_clk) begin dac_dmx_valid <= dac_valid & dac_dmx_enable; dac_valid_d1 <= dac_valid; diff --git a/library/util_var_fifo/util_var_fifo.v b/library/util_var_fifo/util_var_fifo.v index cc6ad2dd9..2f4619cc3 100644 --- a/library/util_var_fifo/util_var_fifo.v +++ b/library/util_var_fifo/util_var_fifo.v @@ -37,37 +37,26 @@ `timescale 1ns/100ps -module util_var_fifo ( +module util_var_fifo #( - clk, - rst, + parameter DATA_WIDTH = 32, + parameter ADDRESS_WIDTH = 13) ( - depth, + input clk, + input rst, - data_in, - data_in_valid, + input [31:0] depth, - data_out, - data_out_valid + input [ -1:0] data_in, + input data_in_valid, + output [DATA_WIDTH-1:0] data_out, + output data_out_valid ); - parameter DATA_WIDTH = 32; - parameter ADDRESS_WIDTH = 13; localparam MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1; - input clk; - input rst; - - input [31:0] depth; - - input [DATA_WIDTH -1:0] data_in; - input data_in_valid; - - output [DATA_WIDTH-1:0] data_out; - output data_out_valid; - // internal registers reg [ADDRESS_WIDTH-1:0] addra = 'd0; diff --git a/library/util_wfifo/util_wfifo.v b/library/util_wfifo/util_wfifo.v index 6a2d55728..fc251189a 100644 --- a/library/util_wfifo/util_wfifo.v +++ b/library/util_wfifo/util_wfifo.v @@ -37,74 +37,73 @@ `timescale 1ns/100ps -module util_wfifo ( +module util_wfifo #( + + parameter NUM_OF_CHANNELS = 4, + parameter DIN_DATA_WIDTH = 32, + parameter DOUT_DATA_WIDTH = 64, + parameter DIN_ADDRESS_WIDTH = 8) ( // d-in interface - din_rst, - din_clk, - din_enable_0, - din_valid_0, - din_data_0, - din_enable_1, - din_valid_1, - din_data_1, - din_enable_2, - din_valid_2, - din_data_2, - din_enable_3, - din_valid_3, - din_data_3, - din_enable_4, - din_valid_4, - din_data_4, - din_enable_5, - din_valid_5, - din_data_5, - din_enable_6, - din_valid_6, - din_data_6, - din_enable_7, - din_valid_7, - din_data_7, - din_ovf, + input din_rst, + input din_clk, + input din_enable_0, + input din_valid_0, + input [DIN_DATA_WIDTH-1:0] din_data_0, + input din_enable_1, + input din_valid_1, + input [DIN_DATA_WIDTH-1:0] din_data_1, + input din_enable_2, + input din_valid_2, + input [DIN_DATA_WIDTH-1:0] din_data_2, + input din_enable_3, + input din_valid_3, + input [DIN_DATA_WIDTH-1:0] din_data_3, + input din_enable_4, + input din_valid_4, + input [DIN_DATA_WIDTH-1:0] din_data_4, + input din_enable_5, + input din_valid_5, + input [DIN_DATA_WIDTH-1:0] din_data_5, + input din_enable_6, + input din_valid_6, + input [DIN_DATA_WIDTH-1:0] din_data_6, + input din_enable_7, + input din_valid_7, + input [DIN_DATA_WIDTH-1:0] din_data_7, + output reg din_ovf, // d-out interface - dout_rstn, - dout_clk, - dout_enable_0, - dout_valid_0, - dout_data_0, - dout_enable_1, - dout_valid_1, - dout_data_1, - dout_enable_2, - dout_valid_2, - dout_data_2, - dout_enable_3, - dout_valid_3, - dout_data_3, - dout_enable_4, - dout_valid_4, - dout_data_4, - dout_enable_5, - dout_valid_5, - dout_data_5, - dout_enable_6, - dout_valid_6, - dout_data_6, - dout_enable_7, - dout_valid_7, - dout_data_7, - dout_ovf); + input dout_rstn, + input dout_clk, + output dout_enable_0, + output dout_valid_0, + output [DOUT_DATA_WIDTH-1:0] dout_data_0, + output dout_enable_1, + output dout_valid_1, + output [DOUT_DATA_WIDTH-1:0] dout_data_1, + output dout_enable_2, + output dout_valid_2, + output [DOUT_DATA_WIDTH-1:0] dout_data_2, + output dout_enable_3, + output dout_valid_3, + output [DOUT_DATA_WIDTH-1:0] dout_data_3, + output dout_enable_4, + output dout_valid_4, + output [DOUT_DATA_WIDTH-1:0] dout_data_4, + output dout_enable_5, + output dout_valid_5, + output [DOUT_DATA_WIDTH-1:0] dout_data_5, + output dout_enable_6, + output dout_valid_6, + output [DOUT_DATA_WIDTH-1:0] dout_data_6, + output dout_enable_7, + output dout_valid_7, + output [DOUT_DATA_WIDTH-1:0] dout_data_7, + input dout_ovf); - // parameters - - parameter NUM_OF_CHANNELS = 4; - parameter DIN_DATA_WIDTH = 32; - parameter DOUT_DATA_WIDTH = 64; - parameter DIN_ADDRESS_WIDTH = 8; localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH; localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 4) ? DIN_ADDRESS_WIDTH : 4; @@ -112,66 +111,6 @@ module util_wfifo ( localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8; localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8; - // d-in interface - - input din_rst; - input din_clk; - input din_enable_0; - input din_valid_0; - input [DIN_DATA_WIDTH-1:0] din_data_0; - input din_enable_1; - input din_valid_1; - input [DIN_DATA_WIDTH-1:0] din_data_1; - input din_enable_2; - input din_valid_2; - input [DIN_DATA_WIDTH-1:0] din_data_2; - input din_enable_3; - input din_valid_3; - input [DIN_DATA_WIDTH-1:0] din_data_3; - input din_enable_4; - input din_valid_4; - input [DIN_DATA_WIDTH-1:0] din_data_4; - input din_enable_5; - input din_valid_5; - input [DIN_DATA_WIDTH-1:0] din_data_5; - input din_enable_6; - input din_valid_6; - input [DIN_DATA_WIDTH-1:0] din_data_6; - input din_enable_7; - input din_valid_7; - input [DIN_DATA_WIDTH-1:0] din_data_7; - output din_ovf; - - // dout interface - - input dout_rstn; - input dout_clk; - output dout_enable_0; - output dout_valid_0; - output [DOUT_DATA_WIDTH-1:0] dout_data_0; - output dout_enable_1; - output dout_valid_1; - output [DOUT_DATA_WIDTH-1:0] dout_data_1; - output dout_enable_2; - output dout_valid_2; - output [DOUT_DATA_WIDTH-1:0] dout_data_2; - output dout_enable_3; - output dout_valid_3; - output [DOUT_DATA_WIDTH-1:0] dout_data_3; - output dout_enable_4; - output dout_valid_4; - output [DOUT_DATA_WIDTH-1:0] dout_data_4; - output dout_enable_5; - output dout_valid_5; - output [DOUT_DATA_WIDTH-1:0] dout_data_5; - output dout_enable_6; - output dout_valid_6; - output [DOUT_DATA_WIDTH-1:0] dout_data_6; - output dout_enable_7; - output dout_valid_7; - output [DOUT_DATA_WIDTH-1:0] dout_data_7; - input dout_ovf; - // internal registers reg [(DATA_WIDTH-1):0] din_wdata = 'd0; @@ -182,7 +121,6 @@ module util_wfifo ( reg din_req_t = 'd0; reg [(ADDRESS_WIDTH-4):0] din_rinit = 'd0; reg din_ovf_m1 = 'd0; - reg din_ovf = 'd0; reg dout_req_t_m1 = 'd0; reg dout_req_t_m2 = 'd0; reg dout_req_t_m3 = 'd0; diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo.v b/library/xilinx/axi_adcfifo/axi_adcfifo.v index 831ff4c33..8411d229e 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo.v @@ -39,146 +39,81 @@ `timescale 1ns/100ps -module axi_adcfifo ( +module axi_adcfifo #( + + parameter ADC_DATA_WIDTH = 128, + parameter DMA_DATA_WIDTH = 64, + parameter AXI_DATA_WIDTH = 512, + parameter DMA_READY_ENABLE = 1, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 16, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'hffffffff) ( // fifo interface - adc_rst, - adc_clk, - adc_wr, - adc_wdata, - adc_wovf, + input adc_rst, + input adc_clk, + input adc_wr, + input [ADC_DATA_WIDTH-1:0] adc_wdata, + output adc_wovf, // dma interface - dma_clk, - dma_wr, - dma_wdata, - dma_wready, - dma_xfer_req, - dma_xfer_status, + input dma_clk, + output dma_wr, + output [DMA_DATA_WIDTH-1:0] dma_wdata, + input dma_wready, + input dma_xfer_req, + output [ 3:0] dma_xfer_status, // axi interface - axi_clk, - axi_resetn, - axi_awvalid, - axi_awid, - axi_awburst, - axi_awlock, - axi_awcache, - axi_awprot, - axi_awqos, - axi_awuser, - axi_awlen, - axi_awsize, - axi_awaddr, - axi_awready, - axi_wvalid, - axi_wdata, - axi_wstrb, - axi_wlast, - axi_wuser, - axi_wready, - axi_bvalid, - axi_bid, - axi_bresp, - axi_buser, - axi_bready, - axi_arvalid, - axi_arid, - axi_arburst, - axi_arlock, - axi_arcache, - axi_arprot, - axi_arqos, - axi_aruser, - axi_arlen, - axi_arsize, - axi_araddr, - axi_arready, - axi_rvalid, - axi_rid, - axi_ruser, - axi_rresp, - axi_rlast, - axi_rdata, - axi_rready); + input axi_clk, + input axi_resetn, + output axi_awvalid, + output [ 3:0] axi_awid, + output [ 1:0] axi_awburst, + output axi_awlock, + output [ 3:0] axi_awcache, + output [ 2:0] axi_awprot, + output [ 3:0] axi_awqos, + output [ 3:0] axi_awuser, + output [ 7:0] axi_awlen, + output [ 2:0] axi_awsize, + output [ 31:0] axi_awaddr, + input axi_awready, + output axi_wvalid, + output [AXI_DATA_WIDTH-1:0] axi_wdata, + output [(AXI_DATA_WIDTH/8)-1:0] axi_wstrb, + output axi_wlast, + output [ 3:0] axi_wuser, + input axi_wready, + input axi_bvalid, + input [ 3:0] axi_bid, + input [ 1:0] axi_bresp, + input [ 3:0] axi_buser, + output axi_bready, + output axi_arvalid, + output [ 3:0] axi_arid, + output [ 1:0] axi_arburst, + output axi_arlock, + output [ 3:0] axi_arcache, + output [ 2:0] axi_arprot, + output [ 3:0] axi_arqos, + output [ 3:0] axi_aruser, + output [ 7:0] axi_arlen, + output [ 2:0] axi_arsize, + output [ 31:0] axi_araddr, + input axi_arready, + input axi_rvalid, + input [ 3:0] axi_rid, + input [ 3:0] axi_ruser, + input [ 1:0] axi_rresp, + input axi_rlast, + input [AXI_DATA_WIDTH-1:0] axi_rdata, + output axi_rready); - // parameters - - parameter ADC_DATA_WIDTH = 128; - parameter DMA_DATA_WIDTH = 64; - parameter AXI_DATA_WIDTH = 512; - parameter DMA_READY_ENABLE = 1; - parameter AXI_SIZE = 2; - parameter AXI_LENGTH = 16; - parameter AXI_ADDRESS = 32'h00000000; - parameter AXI_ADDRESS_LIMIT = 32'hffffffff; - - // adc interface - - input adc_rst; - input adc_clk; - input adc_wr; - input [ADC_DATA_WIDTH-1:0] adc_wdata; - output adc_wovf; - - // dma interface - - input dma_clk; - output dma_wr; - output [DMA_DATA_WIDTH-1:0] dma_wdata; - input dma_wready; - input dma_xfer_req; - output [ 3:0] dma_xfer_status; - - // axi interface - - input axi_clk; - input axi_resetn; - output axi_awvalid; - output [ 3:0] axi_awid; - output [ 1:0] axi_awburst; - output axi_awlock; - output [ 3:0] axi_awcache; - output [ 2:0] axi_awprot; - output [ 3:0] axi_awqos; - output [ 3:0] axi_awuser; - output [ 7:0] axi_awlen; - output [ 2:0] axi_awsize; - output [ 31:0] axi_awaddr; - input axi_awready; - output axi_wvalid; - output [AXI_DATA_WIDTH-1:0] axi_wdata; - output [(AXI_DATA_WIDTH/8)-1:0] axi_wstrb; - output axi_wlast; - output [ 3:0] axi_wuser; - input axi_wready; - input axi_bvalid; - input [ 3:0] axi_bid; - input [ 1:0] axi_bresp; - input [ 3:0] axi_buser; - output axi_bready; - output axi_arvalid; - output [ 3:0] axi_arid; - output [ 1:0] axi_arburst; - output axi_arlock; - output [ 3:0] axi_arcache; - output [ 2:0] axi_arprot; - output [ 3:0] axi_arqos; - output [ 3:0] axi_aruser; - output [ 7:0] axi_arlen; - output [ 2:0] axi_arsize; - output [ 31:0] axi_araddr; - input axi_arready; - input axi_rvalid; - input [ 3:0] axi_rid; - input [ 3:0] axi_ruser; - input [ 1:0] axi_rresp; - input axi_rlast; - input [AXI_DATA_WIDTH-1:0] axi_rdata; - output axi_rready; // internal signals diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v b/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v index 93855546e..78e071d82 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v @@ -39,52 +39,32 @@ `timescale 1ns/100ps -module axi_adcfifo_adc ( +module axi_adcfifo_adc #( + + parameter ADC_DATA_WIDTH = 128, + parameter AXI_DATA_WIDTH = 512) ( // fifo interface - adc_rst, - adc_clk, - adc_wr, - adc_wdata, - adc_wovf, - adc_dwr, - adc_ddata, + input adc_rst, + input adc_clk, + input adc_wr, + input [ADC_DATA_WIDTH-1:0] adc_wdata, + output reg adc_wovf, + output reg adc_dwr, + output reg [AXI_DATA_WIDTH-1:0] adc_ddata, // axi interface - axi_drst, - axi_clk, - axi_xfer_status); + input axi_drst, + input axi_clk, + input [ 3:0] axi_xfer_status); - // parameters - - parameter ADC_DATA_WIDTH = 128; - parameter AXI_DATA_WIDTH = 512; localparam ADC_MEM_RATIO = AXI_DATA_WIDTH/ADC_DATA_WIDTH; - // adc interface - - input adc_rst; - input adc_clk; - input adc_wr; - input [ADC_DATA_WIDTH-1:0] adc_wdata; - output adc_wovf; - output adc_dwr; - output [AXI_DATA_WIDTH-1:0] adc_ddata; - - // axi interface - - input axi_clk; - input axi_drst; - input [ 3:0] axi_xfer_status; - // internal registers - reg adc_wovf = 'd0; reg [ 2:0] adc_wcnt_int = 'd0; - reg adc_dwr = 'd0; - reg [AXI_DATA_WIDTH-1:0] adc_ddata = 'd0; // internal signals diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v b/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v index 5ebdd0c0a..17051be4a 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v @@ -39,50 +39,32 @@ `timescale 1ns/100ps -module axi_adcfifo_dma ( +module axi_adcfifo_dma #( - axi_clk, - axi_drst, - axi_dvalid, - axi_ddata, - axi_dready, - axi_xfer_status, + parameter AXI_DATA_WIDTH = 512, + parameter DMA_DATA_WIDTH = 64, + parameter DMA_READY_ENABLE = 1) ( - dma_clk, - dma_wr, - dma_wdata, - dma_wready, - dma_xfer_req, - dma_xfer_status); + input axi_clk, + input axi_drst, + input axi_dvalid, + input [AXI_DATA_WIDTH-1:0] axi_ddata, + output reg axi_dready, + input [ 3:0] axi_xfer_status, - // parameters + input dma_clk, + output dma_wr, + output [DMA_DATA_WIDTH-1:0] dma_wdata, + input dma_wready, + input dma_xfer_req, + output [ 3:0] dma_xfer_status); - parameter AXI_DATA_WIDTH = 512; - parameter DMA_DATA_WIDTH = 64; - parameter DMA_READY_ENABLE = 1; localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH; localparam DMA_ADDRESS_WIDTH = 8; localparam AXI_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) : ((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3)); - // adc write - - input axi_clk; - input axi_drst; - input axi_dvalid; - input [AXI_DATA_WIDTH-1:0] axi_ddata; - output axi_dready; - input [ 3:0] axi_xfer_status; - - // dma read - - input dma_clk; - output dma_wr; - output [DMA_DATA_WIDTH-1:0] dma_wdata; - input dma_wready; - input dma_xfer_req; - output [ 3:0] dma_xfer_status; // internal registers @@ -93,7 +75,6 @@ module axi_adcfifo_dma ( reg [ 2:0] axi_raddr_rel_t_m = 'd0; reg [DMA_ADDRESS_WIDTH-1:0] axi_raddr_rel = 'd0; reg [DMA_ADDRESS_WIDTH-1:0] axi_addr_diff = 'd0; - reg axi_dready = 'd0; reg dma_rst = 'd0; reg [ 2:0] dma_waddr_rel_t_m = 'd0; reg [AXI_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0; diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v b/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v index 8018d4678..dc969c0d1 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v @@ -39,108 +39,63 @@ `timescale 1ns/100ps -module axi_adcfifo_rd ( +module axi_adcfifo_rd #( + + parameter AXI_DATA_WIDTH = 512, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 16, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'h00000000) ( // request and synchronization - dma_xfer_req, + input dma_xfer_req, // read interface - axi_rd_req, - axi_rd_addr, + input axi_rd_req, + input [ 31:0] axi_rd_addr, // axi interface - axi_clk, - axi_resetn, - axi_arvalid, - axi_arid, - axi_arburst, - axi_arlock, - axi_arcache, - axi_arprot, - axi_arqos, - axi_aruser, - axi_arlen, - axi_arsize, - axi_araddr, - axi_arready, - axi_rvalid, - axi_rid, - axi_ruser, - axi_rresp, - axi_rlast, - axi_rdata, - axi_rready, + input axi_clk, + input axi_resetn, + output reg axi_arvalid, + output [ 3:0] axi_arid, + output [ 1:0] axi_arburst, + output axi_arlock, + output [ 3:0] axi_arcache, + output [ 2:0] axi_arprot, + output [ 3:0] axi_arqos, + output [ 3:0] axi_aruser, + output [ 7:0] axi_arlen, + output [ 2:0] axi_arsize, + output reg [ 31:0] axi_araddr, + input axi_arready, + input axi_rvalid, + input [ 3:0] axi_rid, + input [ 3:0] axi_ruser, + input [ 1:0] axi_rresp, + input axi_rlast, + input [AXI_DATA_WIDTH-1:0] axi_rdata, + output reg axi_rready, // axi status - axi_rerror, + output reg axi_rerror, // fifo interface - axi_drst, - axi_dvalid, - axi_ddata, - axi_dready); + output reg axi_drst, + output reg axi_dvalid, + output reg [AXI_DATA_WIDTH-1:0] axi_ddata, + input axi_dready); - // parameters - - parameter AXI_DATA_WIDTH = 512; - parameter AXI_SIZE = 2; - parameter AXI_LENGTH = 16; - parameter AXI_ADDRESS = 32'h00000000; - parameter AXI_ADDRESS_LIMIT = 32'h00000000; localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH; localparam BUF_THRESHOLD_LO = 6'd3; localparam BUF_THRESHOLD_HI = 6'd60; - // request and synchronization - - input dma_xfer_req; - - // read interface - - input axi_rd_req; - input [ 31:0] axi_rd_addr; - - // axi interface - - input axi_clk; - input axi_resetn; - output axi_arvalid; - output [ 3:0] axi_arid; - output [ 1:0] axi_arburst; - output axi_arlock; - output [ 3:0] axi_arcache; - output [ 2:0] axi_arprot; - output [ 3:0] axi_arqos; - output [ 3:0] axi_aruser; - output [ 7:0] axi_arlen; - output [ 2:0] axi_arsize; - output [ 31:0] axi_araddr; - input axi_arready; - input axi_rvalid; - input [ 3:0] axi_rid; - input [ 3:0] axi_ruser; - input [ 1:0] axi_rresp; - input axi_rlast; - input [AXI_DATA_WIDTH-1:0] axi_rdata; - output axi_rready; - - // axi status - - output axi_rerror; - - // fifo interface - - output axi_drst; - output axi_dvalid; - output [AXI_DATA_WIDTH-1:0] axi_ddata; - input axi_dready; - // internal registers reg [ 31:0] axi_rd_addr_h = 'd0; @@ -149,13 +104,6 @@ module axi_adcfifo_rd ( reg [ 2:0] axi_xfer_req_m = 'd0; reg axi_xfer_init = 'd0; reg axi_xfer_enable = 'd0; - reg axi_arvalid = 'd0; - reg [ 31:0] axi_araddr = 'd0; - reg axi_drst = 'd0; - reg axi_dvalid = 'd0; - reg [AXI_DATA_WIDTH-1:0] axi_ddata = 'd0; - reg axi_rready = 'd0; - reg axi_rerror = 'd0; // internal signals diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v b/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v index 7a21dc8fe..c6bb02b95 100644 --- a/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v @@ -39,120 +39,69 @@ `timescale 1ns/100ps -module axi_adcfifo_wr ( +module axi_adcfifo_wr #( + + parameter AXI_DATA_WIDTH = 512, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 16, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'h00000000) ( // request and synchronization - dma_xfer_req, + input dma_xfer_req, // read interface - axi_rd_req, - axi_rd_addr, + output reg axi_rd_req, + output reg [ 31:0] axi_rd_addr, // fifo interface - adc_rst, - adc_clk, - adc_wr, - adc_wdata, + input adc_rst, + input adc_clk, + input adc_wr, + input [AXI_DATA_WIDTH-1:0] adc_wdata, // axi interface - axi_clk, - axi_resetn, - axi_awvalid, - axi_awid, - axi_awburst, - axi_awlock, - axi_awcache, - axi_awprot, - axi_awqos, - axi_awuser, - axi_awlen, - axi_awsize, - axi_awaddr, - axi_awready, - axi_wvalid, - axi_wdata, - axi_wstrb, - axi_wlast, - axi_wuser, - axi_wready, - axi_bvalid, - axi_bid, - axi_bresp, - axi_buser, - axi_bready, + input axi_clk, + input axi_resetn, + output reg axi_awvalid, + output [ 3:0] axi_awid, + output [ 1:0] axi_awburst, + output axi_awlock, + output [ 3:0] axi_awcache, + output [ 2:0] axi_awprot, + output [ 3:0] axi_awqos, + output [ 3:0] axi_awuser, + output [ 7:0] axi_awlen, + output [ 2:0] axi_awsize, + output reg [ 31:0] axi_awaddr, + input axi_awready, + output axi_wvalid, + output [AXI_DATA_WIDTH-1:0] axi_wdata, + output [AXI_BYTE_WIDTH-1:0] axi_wstrb, + output axi_wlast, + output [ 3:0] axi_wuser, + input axi_wready, + input axi_bvalid, + input [ 3:0] axi_bid, + input [ 1:0] axi_bresp, + input [ 3:0] axi_buser, + output axi_bready, // axi status - axi_dwovf, - axi_dwunf, - axi_werror); + output reg axi_dwovf, + output reg axi_dwunf, + output reg axi_werror); - // parameters - - parameter AXI_DATA_WIDTH = 512; - parameter AXI_SIZE = 2; - parameter AXI_LENGTH = 16; - parameter AXI_ADDRESS = 32'h00000000; - parameter AXI_ADDRESS_LIMIT = 32'h00000000; localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH; localparam BUF_THRESHOLD_LO = 8'd6; localparam BUF_THRESHOLD_HI = 8'd250; - // request and synchronization - - input dma_xfer_req; - - // read interface - - output axi_rd_req; - output [ 31:0] axi_rd_addr; - - // fifo interface - - input adc_rst; - input adc_clk; - input adc_wr; - input [AXI_DATA_WIDTH-1:0] adc_wdata; - - // axi interface - - input axi_clk; - input axi_resetn; - output axi_awvalid; - output [ 3:0] axi_awid; - output [ 1:0] axi_awburst; - output axi_awlock; - output [ 3:0] axi_awcache; - output [ 2:0] axi_awprot; - output [ 3:0] axi_awqos; - output [ 3:0] axi_awuser; - output [ 7:0] axi_awlen; - output [ 2:0] axi_awsize; - output [ 31:0] axi_awaddr; - input axi_awready; - output axi_wvalid; - output [AXI_DATA_WIDTH-1:0] axi_wdata; - output [AXI_BYTE_WIDTH-1:0] axi_wstrb; - output axi_wlast; - output [ 3:0] axi_wuser; - input axi_wready; - input axi_bvalid; - input [ 3:0] axi_bid; - input [ 1:0] axi_bresp; - input [ 3:0] axi_buser; - output axi_bready; - - // axi status - - output axi_dwovf; - output axi_dwunf; - output axi_werror; - // internal registers reg [ 2:0] adc_xfer_req_m = 'd0; @@ -172,9 +121,7 @@ module axi_adcfifo_wr ( reg [ 7:0] axi_waddr = 'd0; reg [ 7:0] axi_addr_diff = 'd0; reg axi_almost_full = 'd0; - reg axi_dwunf = 'd0; reg axi_almost_empty = 'd0; - reg axi_dwovf = 'd0; reg [ 2:0] axi_xfer_req_m = 'd0; reg axi_xfer_init = 'd0; reg [ 7:0] axi_raddr = 'd0; @@ -183,11 +130,6 @@ module axi_adcfifo_wr ( reg axi_rd_d = 'd0; reg axi_rlast_d = 'd0; reg [AXI_DATA_WIDTH-1:0] axi_rdata_d = 'd0; - reg axi_rd_req = 'd0; - reg [ 31:0] axi_rd_addr = 'd0; - reg axi_awvalid = 'd0; - reg [ 31:0] axi_awaddr = 'd0; - reg axi_werror = 'd0; reg axi_reset = 'd0; // internal signals diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v index 1e68f95c4..7a948d15b 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v @@ -39,166 +39,93 @@ `timescale 1ns/100ps -module axi_dacfifo ( +module axi_dacfifo #( + + parameter DAC_DATA_WIDTH = 64, + parameter DMA_DATA_WIDTH = 64, + parameter AXI_DATA_WIDTH = 512, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 15, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'hffffffff) ( // dma interface (AXI Stream) - dma_clk, - dma_rst, - dma_valid, - dma_data, - dma_ready, - dma_xfer_req, - dma_xfer_last, + input dma_clk, + input dma_rst, + input dma_valid, + input [(DMA_DATA_WIDTH-1):0] dma_data, + output reg dma_ready, + input dma_xfer_req, + input dma_xfer_last, // dac interface - dac_clk, - dac_rst, - dac_valid, - dac_data, - dac_dunf, - dac_xfer_out, + input dac_clk, + input dac_rst, + input dac_valid, + output reg [(DAC_DATA_WIDTH-1):0] dac_data, + output reg dac_dunf, + output reg dac_xfer_out, - bypass, + input bypass, // axi interface - axi_clk, - axi_resetn, - axi_awvalid, - axi_awid, - axi_awburst, - axi_awlock, - axi_awcache, - axi_awprot, - axi_awqos, - axi_awuser, - axi_awlen, - axi_awsize, - axi_awaddr, - axi_awready, - axi_wvalid, - axi_wdata, - axi_wstrb, - axi_wlast, - axi_wuser, - axi_wready, - axi_bvalid, - axi_bid, - axi_bresp, - axi_buser, - axi_bready, - axi_arvalid, - axi_arid, - axi_arburst, - axi_arlock, - axi_arcache, - axi_arprot, - axi_arqos, - axi_aruser, - axi_arlen, - axi_arsize, - axi_araddr, - axi_arready, - axi_rvalid, - axi_rid, - axi_ruser, - axi_rresp, - axi_rlast, - axi_rdata, - axi_rready); + input axi_clk, + input axi_resetn, + output axi_awvalid, + output [ 3:0] axi_awid, + output [ 1:0] axi_awburst, + output axi_awlock, + output [ 3:0] axi_awcache, + output [ 2:0] axi_awprot, + output [ 3:0] axi_awqos, + output [ 3:0] axi_awuser, + output [ 7:0] axi_awlen, + output [ 2:0] axi_awsize, + output [ 31:0] axi_awaddr, + input axi_awready, + output axi_wvalid, + output [(AXI_DATA_WIDTH-1):0] axi_wdata, + output [(AXI_DATA_WIDTH/8-1):0] axi_wstrb, + output axi_wlast, + output [ 3:0] axi_wuser, + input axi_wready, + input axi_bvalid, + input [ 3:0] axi_bid, + input [ 1:0] axi_bresp, + input [ 3:0] axi_buser, + output axi_bready, + output axi_arvalid, + output [ 3:0] axi_arid, + output [ 1:0] axi_arburst, + output axi_arlock, + output [ 3:0] axi_arcache, + output [ 2:0] axi_arprot, + output [ 3:0] axi_arqos, + output [ 3:0] axi_aruser, + output [ 7:0] axi_arlen, + output [ 2:0] axi_arsize, + output [ 31:0] axi_araddr, + input axi_arready, + input axi_rvalid, + input [ 3:0] axi_rid, + input [ 3:0] axi_ruser, + input [ 1:0] axi_rresp, + input axi_rlast, + input [(AXI_DATA_WIDTH-1):0] axi_rdata, + output axi_rready); - // parameters - - parameter DAC_DATA_WIDTH = 64; - parameter DMA_DATA_WIDTH = 64; - parameter AXI_DATA_WIDTH = 512; - parameter AXI_SIZE = 2; - parameter AXI_LENGTH = 15; - parameter AXI_ADDRESS = 32'h00000000; - parameter AXI_ADDRESS_LIMIT = 32'hffffffff; localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0; - // dma interface - - input dma_clk; - input dma_rst; - input dma_valid; - input [(DMA_DATA_WIDTH-1):0] dma_data; - output dma_ready; - input dma_xfer_req; - input dma_xfer_last; - - // dac interface - - input dac_clk; - input dac_rst; - input dac_valid; - output [(DAC_DATA_WIDTH-1):0] dac_data; - output dac_dunf; - output dac_xfer_out; - - input bypass; - - // axi interface - - input axi_clk; - input axi_resetn; - output axi_awvalid; - output [ 3:0] axi_awid; - output [ 1:0] axi_awburst; - output axi_awlock; - output [ 3:0] axi_awcache; - output [ 2:0] axi_awprot; - output [ 3:0] axi_awqos; - output [ 3:0] axi_awuser; - output [ 7:0] axi_awlen; - output [ 2:0] axi_awsize; - output [ 31:0] axi_awaddr; - input axi_awready; - output axi_wvalid; - output [(AXI_DATA_WIDTH-1):0] axi_wdata; - output [(AXI_DATA_WIDTH/8-1):0] axi_wstrb; - output axi_wlast; - output [ 3:0] axi_wuser; - input axi_wready; - input axi_bvalid; - input [ 3:0] axi_bid; - input [ 1:0] axi_bresp; - input [ 3:0] axi_buser; - output axi_bready; - output axi_arvalid; - output [ 3:0] axi_arid; - output [ 1:0] axi_arburst; - output axi_arlock; - output [ 3:0] axi_arcache; - output [ 2:0] axi_arprot; - output [ 3:0] axi_arqos; - output [ 3:0] axi_aruser; - output [ 7:0] axi_arlen; - output [ 2:0] axi_arsize; - output [ 31:0] axi_araddr; - input axi_arready; - input axi_rvalid; - input [ 3:0] axi_rid; - input [ 3:0] axi_ruser; - input [ 1:0] axi_rresp; - input axi_rlast; - input [(AXI_DATA_WIDTH-1):0] axi_rdata; - output axi_rready; - - reg dma_ready = 1'b0; reg dma_bypass_m1 = 1'b0; reg dma_bypass = 1'b0; reg dac_bypass_m1 = 1'b0; reg dac_bypass = 1'b0; - reg dac_xfer_out = 1'b0; reg dac_xfer_out_m1 = 1'b0; reg dac_xfer_out_bypass = 1'b0; - reg dac_dunf = 1'b0; - reg [(DAC_DATA_WIDTH-1):0] dac_data = 'b0; // internal signals diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v b/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v index 5042abfb6..468913fd7 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v @@ -39,30 +39,28 @@ `timescale 1ns/100ps -module axi_dacfifo_dac ( +module axi_dacfifo_dac #( - axi_clk, - axi_dvalid, - axi_ddata, - axi_dready, - axi_dlast, - axi_xfer_req, + parameter AXI_DATA_WIDTH = 512, + parameter AXI_LENGTH = 15, + parameter DAC_DATA_WIDTH = 64) ( - dma_last_beats, + input axi_clk, + input axi_dvalid, + input [(AXI_DATA_WIDTH-1):0] axi_ddata, + output reg axi_dready, + input axi_dlast, + input axi_xfer_req, - dac_clk, - dac_rst, - dac_valid, - dac_data, - dac_xfer_out, - dac_dunf -); + input [ 3:0] dma_last_beats, - // parameters + input dac_clk, + input dac_rst, + input dac_valid, + output [(DAC_DATA_WIDTH-1):0] dac_data, + output dac_xfer_out, + output reg dac_dunf); - parameter AXI_DATA_WIDTH = 512; - parameter AXI_LENGTH = 15; - parameter DAC_DATA_WIDTH = 64; localparam MEM_RATIO = AXI_DATA_WIDTH/DAC_DATA_WIDTH; localparam DAC_ADDRESS_WIDTH = 10; @@ -71,34 +69,12 @@ module axi_dacfifo_dac ( (MEM_RATIO == 4) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH - 3); - // BUF_THRESHOLD_LO will make sure that there are always at least two burst in the memmory - localparam AXI_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1); localparam AXI_BUF_THRESHOLD_HI = {(AXI_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1); localparam DAC_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1) * MEM_RATIO; localparam DAC_BUF_THRESHOLD_HI = {(DAC_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1) * MEM_RATIO; localparam DAC_ARINCR = (AXI_LENGTH+1) * MEM_RATIO; - // dma write - - input axi_clk; - input axi_dvalid; - input [(AXI_DATA_WIDTH-1):0] axi_ddata; - output axi_dready; - input axi_dlast; - input axi_xfer_req; - - input [ 3:0] dma_last_beats; - - // dac read - - input dac_clk; - input dac_rst; - input dac_valid; - output [(DAC_DATA_WIDTH-1):0] dac_data; - output dac_xfer_out; - output dac_dunf; - // internal registers reg [(AXI_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0; @@ -109,7 +85,6 @@ module axi_dacfifo_dac ( reg [(DAC_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0; reg [(DAC_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0; reg [(AXI_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'd0; - reg axi_dready = 'd0; reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0; reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0; @@ -129,7 +104,6 @@ module axi_dacfifo_dac ( reg [ 3:0] dac_last_beats = 4'b0; reg [ 3:0] dac_last_beats_m = 4'b0; - reg dac_dunf = 1'b0; reg [ 3:0] dac_beat_cnt = 4'b0; reg dac_dlast = 1'b0; reg dac_dlast_m1 = 1'b0; diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v index 3e93a6ee6..357287b45 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v @@ -39,111 +39,62 @@ `timescale 1ns/100ps -module axi_dacfifo_rd ( +module axi_dacfifo_rd #( + + parameter AXI_DATA_WIDTH = 512, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 15, + parameter AXI_ADDRESS = 32'h00000000) ( // xfer last for read/write synchronization - axi_xfer_req, - axi_last_raddr, - axi_last_beats, + input axi_xfer_req, + input [31:0] axi_last_raddr, + input [ 3:0] axi_last_beats, // axi read address and read data channels - axi_clk, - axi_resetn, - axi_arvalid, - axi_arid, - axi_arburst, - axi_arlock, - axi_arcache, - axi_arprot, - axi_arqos, - axi_aruser, - axi_arlen, - axi_arsize, - axi_araddr, - axi_arready, - axi_rvalid, - axi_rid, - axi_ruser, - axi_rresp, - axi_rlast, - axi_rdata, - axi_rready, + input axi_clk, + input axi_resetn, + output reg axi_arvalid, + output [ 3:0] axi_arid, + output [ 1:0] axi_arburst, + output axi_arlock, + output [ 3:0] axi_arcache, + output [ 2:0] axi_arprot, + output [ 3:0] axi_arqos, + output [ 3:0] axi_aruser, + output [ 7:0] axi_arlen, + output [ 2:0] axi_arsize, + output reg [31:0] axi_araddr, + input axi_arready, + input axi_rvalid, + input [ 3:0] axi_rid, + input [ 3:0] axi_ruser, + input [ 1:0] axi_rresp, + input axi_rlast, + input [(AXI_DATA_WIDTH-1):0] axi_rdata, + output reg axi_rready, // axi status - axi_rerror, + output reg axi_rerror, // fifo interface - axi_dvalid, - axi_ddata, - axi_dready, - axi_dlast); + output reg axi_dvalid, + output reg [(AXI_DATA_WIDTH-1):0] axi_ddata, + input axi_dready, + output reg axi_dlast); - // parameters - - parameter AXI_DATA_WIDTH = 512; - parameter AXI_SIZE = 2; - parameter AXI_LENGTH = 15; - parameter AXI_ADDRESS = 32'h00000000; localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; localparam AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH; - // xfer last for read/write synchronization - - input axi_xfer_req; - input [31:0] axi_last_raddr; - input [ 3:0] axi_last_beats; - - // axi interface - - input axi_clk; - input axi_resetn; - output axi_arvalid; - output [ 3:0] axi_arid; - output [ 1:0] axi_arburst; - output axi_arlock; - output [ 3:0] axi_arcache; - output [ 2:0] axi_arprot; - output [ 3:0] axi_arqos; - output [ 3:0] axi_aruser; - output [ 7:0] axi_arlen; - output [ 2:0] axi_arsize; - output [31:0] axi_araddr; - input axi_arready; - input axi_rvalid; - input [ 3:0] axi_rid; - input [ 3:0] axi_ruser; - input [ 1:0] axi_rresp; - input axi_rlast; - input [(AXI_DATA_WIDTH-1):0] axi_rdata; - output axi_rready; - - // axi status - - output axi_rerror; - - // fifo interface - - output axi_dvalid; - output [(AXI_DATA_WIDTH-1):0] axi_ddata; - input axi_dready; - output axi_dlast; - // internal registers reg axi_rnext = 1'b0; reg axi_ractive = 1'b0; - reg axi_arvalid = 1'b0; - reg [ 31:0] axi_araddr = 32'b0; reg [ 31:0] axi_araddr_prev = 32'b0; - reg [(AXI_DATA_WIDTH-1):0] axi_ddata = 'b0; - reg axi_dvalid = 1'b0; - reg axi_dlast = 1'b0; - reg axi_rready = 1'b0; - reg axi_rerror = 1'b0; reg [ 1:0] axi_xfer_req_m = 2'b0; reg [ 4:0] axi_last_beats_cntr = 16'b0; diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v index 513c1a7af..880c1b1ee 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v @@ -39,69 +39,66 @@ `timescale 1ns/100ps -module axi_dacfifo_wr ( +module axi_dacfifo_wr #( + + parameter AXI_DATA_WIDTH = 512, + parameter DMA_DATA_WIDTH = 64, + parameter AXI_SIZE = 6, + parameter AXI_LENGTH = 15, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'h00000000, + parameter DMA_MEM_ADDRESS_WIDTH = 8) ( // dma fifo interface - dma_clk, - dma_data, - dma_ready, - dma_ready_out, - dma_valid, + input dma_clk, + input [(DMA_DATA_WIDTH-1):0] dma_data, + input dma_ready, + output reg dma_ready_out, + input dma_valid, // request and syncronizaiton - dma_xfer_req, - dma_xfer_last, - dma_last_beats, + input dma_xfer_req, + input dma_xfer_last, + output reg [ 3:0] dma_last_beats, // syncronization for the read side - axi_last_addr, - axi_last_beats, - axi_xfer_out, + output reg [31:0] axi_last_addr, + output reg [ 3:0] axi_last_beats, + output reg axi_xfer_out, // axi write address, write data and write response channels - axi_clk, - axi_resetn, - axi_awvalid, - axi_awid, - axi_awburst, - axi_awlock, - axi_awcache, - axi_awprot, - axi_awqos, - axi_awuser, - axi_awlen, - axi_awsize, - axi_awaddr, - axi_awready, - axi_wvalid, - axi_wdata, - axi_wstrb, - axi_wlast, - axi_wuser, - axi_wready, - axi_bvalid, - axi_bid, - axi_bresp, - axi_buser, - axi_bready, + input axi_clk, + input axi_resetn, + output reg axi_awvalid, + output [ 3:0] axi_awid, + output [ 1:0] axi_awburst, + output axi_awlock, + output [ 3:0] axi_awcache, + output [ 2:0] axi_awprot, + output [ 3:0] axi_awqos, + output [ 3:0] axi_awuser, + output [ 7:0] axi_awlen, + output [ 2:0] axi_awsize, + output reg [31:0] axi_awaddr, + input axi_awready, + output axi_wvalid, + output [(AXI_DATA_WIDTH-1):0] axi_wdata, + output [(AXI_BYTE_WIDTH-1):0] axi_wstrb, + output axi_wlast, + output [ 3:0] axi_wuser, + input axi_wready, + input axi_bvalid, + input [ 3:0] axi_bid, + input [ 1:0] axi_bresp, + input [ 3:0] axi_buser, + output axi_bready, - axi_werror); + output reg axi_werror); - // parameters - - parameter AXI_DATA_WIDTH = 512; - parameter DMA_DATA_WIDTH = 64; - parameter AXI_SIZE = 6; // axi_awsize format - parameter AXI_LENGTH = 15; // axi_awlength format - parameter AXI_ADDRESS = 32'h00000000; - parameter AXI_ADDRESS_LIMIT = 32'h00000000; - parameter DMA_MEM_ADDRESS_WIDTH = 8; - - // for the syncronization buffer localparam MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH; // Max supported MEM_RATIO is 16 localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH : @@ -110,59 +107,11 @@ module axi_dacfifo_wr ( (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) : (DMA_MEM_ADDRESS_WIDTH - 4); - // for the AXI interface - localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; localparam DMA_BYTE_WIDTH = DMA_DATA_WIDTH/8; localparam AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH; localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4; - // dma fifo interface - - input dma_clk; - input [(DMA_DATA_WIDTH-1):0] dma_data; - input dma_ready; - output dma_ready_out; - input dma_valid; - - input dma_xfer_req; - input dma_xfer_last; - output [ 3:0] dma_last_beats; - - output [31:0] axi_last_addr; - output [ 3:0] axi_last_beats; - output axi_xfer_out; - - // axi interface - - input axi_clk; - input axi_resetn; - output axi_awvalid; - output [ 3:0] axi_awid; - output [ 1:0] axi_awburst; - output axi_awlock; - output [ 3:0] axi_awcache; - output [ 2:0] axi_awprot; - output [ 3:0] axi_awqos; - output [ 3:0] axi_awuser; - output [ 7:0] axi_awlen; - output [ 2:0] axi_awsize; - output [31:0] axi_awaddr; - input axi_awready; - output axi_wvalid; - output [(AXI_DATA_WIDTH-1):0] axi_wdata; - output [(AXI_BYTE_WIDTH-1):0] axi_wstrb; - output axi_wlast; - output [ 3:0] axi_wuser; - input axi_wready; - input axi_bvalid; - input [ 3:0] axi_bid; - input [ 1:0] axi_bresp; - input [ 3:0] axi_buser; - output axi_bready; - - output axi_werror; - // registers reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0; @@ -171,12 +120,10 @@ module axi_dacfifo_wr ( reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0; reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0; reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0; - reg dma_ready_out = 1'b0; reg dma_rst_m1 = 1'b0; reg dma_rst_m2 = 1'b0; reg [ 2:0] dma_mem_last_read_toggle_m = 3'b0; reg dma_xfer_req_d = 1'b0; - reg [ 3:0] dma_last_beats = 4'b0; reg [ 4:0] axi_xfer_req_m = 3'b0; reg [ 4:0] axi_xfer_last_m = 3'b0; @@ -198,13 +145,7 @@ module axi_dacfifo_wr ( reg axi_mem_last_read_toggle = 1'b0; reg axi_reset = 1'b0; - reg axi_xfer_out = 1'b0; - reg [31:0] axi_last_addr = 32'b0; - reg [ 3:0] axi_last_beats = 4'b0; - reg axi_awvalid = 1'b0; - reg [31:0] axi_awaddr = 32'b0; reg axi_xfer_init = 1'b0; - reg axi_werror = 1'b0; reg [ 3:0] axi_wvalid_counter = 4'b0; reg axi_endof_transaction = 1'b0; diff --git a/library/xilinx/common/ad_cmos_clk.v b/library/xilinx/common/ad_cmos_clk.v index bbd9d8e1f..023358eed 100644 --- a/library/xilinx/common/ad_cmos_clk.v +++ b/library/xilinx/common/ad_cmos_clk.v @@ -37,24 +37,19 @@ `timescale 1ns/100ps -module ad_cmos_clk ( +module ad_cmos_clk #( - rst, - locked, + parameter DEVICE_TYPE = 0) ( - clk_in, - clk); + input rst, + output locked, + + input clk_in, + output clk); - parameter DEVICE_TYPE = 0; localparam SERIES7 = 0; localparam VIRTEX6 = 1; - input rst; - output locked; - - input clk_in; - output clk; - // wires wire clk_ibuf_s; diff --git a/library/xilinx/common/ad_cmos_in.v b/library/xilinx/common/ad_cmos_in.v index cf2081778..5e37e6f60 100644 --- a/library/xilinx/common/ad_cmos_in.v +++ b/library/xilinx/common/ad_cmos_in.v @@ -37,61 +37,38 @@ `timescale 1ns/100ps -module ad_cmos_in ( +module ad_cmos_in #( + + parameter SINGLE_ENDED = 0, + parameter DEVICE_TYPE = 0, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( // data interface - rx_clk, - rx_data_in, - rx_data_p, - rx_data_n, + input rx_clk, + input rx_data_in, + output rx_data_p, + output reg rx_data_n, // delay-data interface - up_clk, - up_dld, - up_dwdata, - up_drdata, + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, // delay-cntrl interface - delay_clk, - delay_rst, - delay_locked); + input delay_clk, + input delay_rst, + output delay_locked); - // parameters - - parameter SINGLE_ENDED = 0; - parameter DEVICE_TYPE = 0; - parameter IODELAY_CTRL = 0; - parameter IODELAY_GROUP = "dev_if_delay_group"; localparam SERIES7 = 0; localparam VIRTEX6 = 1; - // data interface - - input rx_clk; - input rx_data_in; - output rx_data_p; - output rx_data_n; - - // delay-data interface - - input up_clk; - input up_dld; - input [ 4:0] up_dwdata; - output [ 4:0] up_drdata; - - // delay-cntrl interface - - input delay_clk; - input delay_rst; - output delay_locked; - // internal registers - reg rx_data_n; - // internal signals wire rx_data_n_s; diff --git a/library/xilinx/common/ad_cmos_out.v b/library/xilinx/common/ad_cmos_out.v index 9537d6dd1..00444b8f9 100644 --- a/library/xilinx/common/ad_cmos_out.v +++ b/library/xilinx/common/ad_cmos_out.v @@ -37,58 +37,37 @@ `timescale 1ns/100ps -module ad_cmos_out ( +module ad_cmos_out #( + + parameter DEVICE_TYPE = 0, + parameter SINGLE_ENDED = 0, + parameter IODELAY_ENABLE = 0, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( // data interface - tx_clk, - tx_data_p, - tx_data_n, - tx_data_out, + input tx_clk, + input tx_data_p, + input tx_data_n, + output tx_data_out, // delay-data interface - up_clk, - up_dld, - up_dwdata, - up_drdata, + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, // delay-cntrl interface - delay_clk, - delay_rst, - delay_locked); + input delay_clk, + input delay_rst, + output delay_locked); - // parameters - - parameter DEVICE_TYPE = 0; - parameter SINGLE_ENDED = 0; - parameter IODELAY_ENABLE = 0; - parameter IODELAY_CTRL = 0; - parameter IODELAY_GROUP = "dev_if_delay_group"; localparam SERIES7 = 0; localparam VIRTEX6 = 1; - // data interface - - input tx_clk; - input tx_data_p; - input tx_data_n; - output tx_data_out; - - // delay-data interface - - input up_clk; - input up_dld; - input [ 4:0] up_dwdata; - output [ 4:0] up_drdata; - - // delay-cntrl interface - - input delay_clk; - input delay_rst; - output delay_locked; - // internal signals wire tx_data_oddr_s; diff --git a/library/xilinx/common/ad_iobuf.v b/library/xilinx/common/ad_iobuf.v index 48c779288..637813a85 100644 --- a/library/xilinx/common/ad_iobuf.v +++ b/library/xilinx/common/ad_iobuf.v @@ -39,19 +39,15 @@ `timescale 1ns/100ps -module ad_iobuf ( +module ad_iobuf #( - dio_t, - dio_i, - dio_o, - dio_p); + parameter DATA_WIDTH = 1) ( - parameter DATA_WIDTH = 1; + input [(DATA_WIDTH-1):0] dio_t, + input [(DATA_WIDTH-1):0] dio_i, + output [(DATA_WIDTH-1):0] dio_o, + inout [(DATA_WIDTH-1):0] dio_p); - input [(DATA_WIDTH-1):0] dio_t; - input [(DATA_WIDTH-1):0] dio_i; - output [(DATA_WIDTH-1):0] dio_o; - inout [(DATA_WIDTH-1):0] dio_p; genvar n; generate diff --git a/library/xilinx/common/ad_lvds_clk.v b/library/xilinx/common/ad_lvds_clk.v index a4c0ca153..aa6706211 100644 --- a/library/xilinx/common/ad_lvds_clk.v +++ b/library/xilinx/common/ad_lvds_clk.v @@ -39,26 +39,20 @@ `timescale 1ns/100ps -module ad_lvds_clk ( +module ad_lvds_clk #( - rst, - locked, + parameter DEVICE_TYPE = 0) ( - clk_in_p, - clk_in_n, - clk); + input rst, + output locked, + + input clk_in_p, + input clk_in_n, + output clk); - parameter DEVICE_TYPE = 0; localparam SERIES7 = 0; localparam VIRTEX6 = 1; - input rst; - output locked; - - input clk_in_p; - input clk_in_n; - output clk; - // wires wire clk_ibuf_s; @@ -88,8 +82,6 @@ module ad_lvds_clk ( end endgenerate - - endmodule // *************************************************************************** diff --git a/library/xilinx/common/ad_lvds_out.v b/library/xilinx/common/ad_lvds_out.v index 1cbc93389..6f28b86d9 100644 --- a/library/xilinx/common/ad_lvds_out.v +++ b/library/xilinx/common/ad_lvds_out.v @@ -37,61 +37,39 @@ `timescale 1ns/100ps -module ad_lvds_out ( +module ad_lvds_out #( + + parameter DEVICE_TYPE = 0, + parameter SINGLE_ENDED = 0, + parameter IODELAY_ENABLE = 0, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( // data interface - tx_clk, - tx_data_p, - tx_data_n, - tx_data_out_p, - tx_data_out_n, + input tx_clk, + input tx_data_p, + input tx_data_n, + output tx_data_out_p, + output tx_data_out_n, // delay-data interface - up_clk, - up_dld, - up_dwdata, - up_drdata, + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, // delay-cntrl interface - delay_clk, - delay_rst, - delay_locked); + input delay_clk, + input delay_rst, + output delay_locked); - // parameters - - parameter DEVICE_TYPE = 0; - parameter SINGLE_ENDED = 0; - parameter IODELAY_ENABLE = 0; - parameter IODELAY_CTRL = 0; - parameter IODELAY_GROUP = "dev_if_delay_group"; localparam VIRTEX7 = 0; localparam VIRTEX6 = 1; localparam ULTRASCALE = 2; - // data interface - - input tx_clk; - input tx_data_p; - input tx_data_n; - output tx_data_out_p; - output tx_data_out_n; - - // delay-data interface - - input up_clk; - input up_dld; - input [ 4:0] up_dwdata; - output [ 4:0] up_drdata; - - // delay-cntrl interface - - input delay_clk; - input delay_rst; - output delay_locked; - // internal signals wire tx_data_oddr_s; diff --git a/library/xilinx/common/ad_mmcm_drp.v b/library/xilinx/common/ad_mmcm_drp.v index e9d5f0e37..1fb25fa3f 100644 --- a/library/xilinx/common/ad_mmcm_drp.v +++ b/library/xilinx/common/ad_mmcm_drp.v @@ -38,75 +38,49 @@ `timescale 1ns/100ps -module ad_mmcm_drp ( +module ad_mmcm_drp #( + + parameter MMCM_DEVICE_TYPE = 0, + parameter MMCM_CLKIN_PERIOD = 1.667, + parameter MMCM_CLKIN2_PERIOD = 1.667, + parameter MMCM_VCO_DIV = 6, + parameter MMCM_VCO_MUL = 12.000, + parameter MMCM_CLK0_DIV = 2.000, + parameter MMCM_CLK0_PHASE = 0.000, + parameter MMCM_CLK1_DIV = 6, + parameter MMCM_CLK1_PHASE = 0.000, + parameter MMCM_CLK2_DIV = 2.000, + parameter MMCM_CLK2_PHASE = 0.000) ( // clocks - clk, - clk2, - clk_sel, - mmcm_rst, - mmcm_clk_0, - mmcm_clk_1, - mmcm_clk_2, + input clk, + input clk2, + input clk_sel, + input mmcm_rst, + output mmcm_clk_0, + output mmcm_clk_1, + output mmcm_clk_2, // drp interface - up_clk, - up_rstn, - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked); + input up_clk, + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [15:0] up_drp_wdata, + output reg [15:0] up_drp_rdata, + output reg up_drp_ready, + output reg up_drp_locked); - // parameters - - parameter MMCM_DEVICE_TYPE = 0; localparam MMCM_DEVICE_7SERIES = 0; localparam MMCM_DEVICE_VIRTEX6 = 1; - parameter MMCM_CLKIN_PERIOD = 1.667; - parameter MMCM_CLKIN2_PERIOD = 1.667; - parameter MMCM_VCO_DIV = 6; - parameter MMCM_VCO_MUL = 12.000; - parameter MMCM_CLK0_DIV = 2.000; - parameter MMCM_CLK0_PHASE = 0.000; - parameter MMCM_CLK1_DIV = 6; - parameter MMCM_CLK1_PHASE = 0.000; - parameter MMCM_CLK2_DIV = 2.000; - parameter MMCM_CLK2_PHASE = 0.000; - - // clocks - - input clk; - input clk2; - input clk_sel; - input mmcm_rst; - output mmcm_clk_0; - output mmcm_clk_1; - output mmcm_clk_2; - - // drp interface - - input up_clk; - input up_rstn; - input up_drp_sel; - input up_drp_wr; - input [11:0] up_drp_addr; - input [15:0] up_drp_wdata; - output [15:0] up_drp_rdata; - output up_drp_ready; - output up_drp_locked; // internal registers - reg [15:0] up_drp_rdata = 'd0; - reg up_drp_ready = 'd0; reg up_drp_locked_m1 = 'd0; - reg up_drp_locked = 'd0; // internal signals diff --git a/library/xilinx/common/ad_mul.v b/library/xilinx/common/ad_mul.v index 2c3ad9f6a..5429230ed 100644 --- a/library/xilinx/common/ad_mul.v +++ b/library/xilinx/common/ad_mul.v @@ -39,41 +39,27 @@ `timescale 1ps/1ps -module ad_mul ( +module ad_mul #( + + parameter DELAY_DATA_WIDTH = 16) ( // data_p = data_a * data_b; - clk, - data_a, - data_b, - data_p, + input clk, + input [16:0] data_a, + input [16:0] data_b, + output [33:0] data_p, // delay interface - ddata_in, - ddata_out); + input [(DELAY_DATA_WIDTH-1):0] ddata_in, + output reg [(DELAY_DATA_WIDTH-1):0] ddata_out); - // delayed data bus width - - parameter DELAY_DATA_WIDTH = 16; - - // data_p = data_a * data_b; - - input clk; - input [16:0] data_a; - input [16:0] data_b; - output [33:0] data_p; - - // delay interface - - input [(DELAY_DATA_WIDTH-1):0] ddata_in; - output [(DELAY_DATA_WIDTH-1):0] ddata_out; // internal registers reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0; reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0; - reg [(DELAY_DATA_WIDTH-1):0] ddata_out = 'd0; // a/b reg, m-reg, p-reg delay match diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v index 6a5f4a892..713f71d91 100644 --- a/projects/ad6676evb/vc707/system_top.v +++ b/projects/ad6676evb/vc707/system_top.v @@ -39,155 +39,80 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_reset_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ras_n, - ddr3_we_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, + output ddr3_reset_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output ddr3_ras_n, + output ddr3_we_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, - sgmii_rxp, - sgmii_rxn, - sgmii_txp, - sgmii_txn, + input sgmii_rxp, + input sgmii_rxn, + output sgmii_txp, + output sgmii_txn, - phy_rstn, - mgt_clk_p, - mgt_clk_n, - mdio_mdc, - mdio_mdio, + output phy_rstn, + input mgt_clk_p, + input mgt_clk_n, + output mdio_mdc, + inout mdio_mdio, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_dq_io, - linear_flash_oen, - linear_flash_wen, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + inout [15:0] linear_flash_dq_io, + output linear_flash_oen, + output linear_flash_wen, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [20:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + output rx_sysref_p, + output rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 1:0] rx_data_p, + input [ 1:0] rx_data_n, - adc_oen, - adc_sela, - adc_selb, - adc_s0, - adc_s1, - adc_resetb, - adc_agc1, - adc_agc2, - adc_agc3, - adc_agc4, + inout adc_oen, + inout adc_sela, + inout adc_selb, + inout adc_s0, + inout adc_s1, + inout adc_resetb, + inout adc_agc1, + inout adc_agc2, + inout adc_agc3, + inout adc_agc4, - spi_csn, - spi_clk, - spi_mosi, - spi_miso); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output ddr3_reset_n; - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output ddr3_ras_n; - output ddr3_we_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - - input sgmii_rxp; - input sgmii_rxn; - output sgmii_txp; - output sgmii_txn; - - output phy_rstn; - input mgt_clk_p; - input mgt_clk_n; - output mdio_mdc; - inout mdio_mdio; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - inout [15:0] linear_flash_dq_io; - output linear_flash_oen; - output linear_flash_wen; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [20:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - output rx_sysref_p; - output rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 1:0] rx_data_p; - input [ 1:0] rx_data_n; - - inout adc_oen; - inout adc_sela; - inout adc_selb; - inout adc_s0; - inout adc_s1; - inout adc_resetb; - inout adc_agc1; - inout adc_agc2; - inout adc_agc3; - inout adc_agc4; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); // internal signals diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v index fc387b1d8..6699ef20b 100644 --- a/projects/ad6676evb/zc706/system_top.v +++ b/projects/ad6676evb/zc706/system_top.v @@ -41,127 +41,66 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + output rx_sysref_p, + output rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 1:0] rx_data_p, + input [ 1:0] rx_data_n, - adc_oen, - adc_sela, - adc_selb, - adc_s0, - adc_s1, - adc_resetb, - adc_agc1, - adc_agc2, - adc_agc3, - adc_agc4, + inout adc_oen, + inout adc_sela, + inout adc_selb, + inout adc_s0, + inout adc_s1, + inout adc_resetb, + inout adc_agc1, + inout adc_agc2, + inout adc_agc3, + inout adc_agc4, - spi_csn, - spi_clk, - spi_mosi, - spi_miso); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - output rx_sysref_p; - output rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 1:0] rx_data_p; - input [ 1:0] rx_data_n; - - inout adc_oen; - inout adc_sela; - inout adc_selb; - inout adc_s0; - inout adc_s1; - inout adc_resetb; - inout adc_agc1; - inout adc_agc2; - inout adc_agc3; - inout adc_agc4; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); // internal signals diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v index 3abb0fbef..78fd68771 100644 --- a/projects/ad7616_sdz/zc706/system_top_pi.v +++ b/projects/ad7616_sdz/zc706/system_top_pi.v @@ -41,101 +41,53 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - adc_db, - adc_rd_n, - adc_wr_n, + inout [15:0] adc_db, + output adc_rd_n, + output adc_wr_n, - adc_cs_n, - adc_reset_n, - adc_convst, - adc_busy, - adc_seq_en, - adc_hw_rngsel, - adc_chsel); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - inout [15:0] adc_db; - output adc_rd_n; - output adc_wr_n; - - output adc_cs_n; - output adc_reset_n; - output adc_convst; - input adc_busy; - output adc_seq_en; - output [ 1:0] adc_hw_rngsel; - output [ 2:0] adc_chsel; + output adc_cs_n, + output adc_reset_n, + output adc_convst, + input adc_busy, + output adc_seq_en, + output [ 1:0] adc_hw_rngsel, + output [ 2:0] adc_chsel); // internal signals diff --git a/projects/ad7616_sdz/zc706/system_top_si.v b/projects/ad7616_sdz/zc706/system_top_si.v index fef99aef4..058cf87ee 100644 --- a/projects/ad7616_sdz/zc706/system_top_si.v +++ b/projects/ad7616_sdz/zc706/system_top_si.v @@ -41,109 +41,57 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - spi_sclk, - spi_sdo, - spi_sdi_0, - spi_sdi_1, - spi_cs_n, + output spi_sclk, + output spi_sdo, + input spi_sdi_0, + input spi_sdi_1, + output spi_cs_n, - adc_reset_n, - adc_convst, - adc_busy, - adc_seq_en, - adc_hw_rngsel, - adc_chsel, - adc_crcen, - adc_burst, - adc_os); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - output spi_sclk; - output spi_sdo; - input spi_sdi_0; - input spi_sdi_1; - output spi_cs_n; - - output adc_reset_n; - output adc_convst; - input adc_busy; - output adc_seq_en; - output [ 1:0] adc_hw_rngsel; - output [ 2:0] adc_chsel; - output adc_crcen; - output adc_burst; - output [ 2:0] adc_os; + output adc_reset_n, + output adc_convst, + input adc_busy, + output adc_seq_en, + output [ 1:0] adc_hw_rngsel, + output [ 2:0] adc_chsel, + output adc_crcen, + output adc_burst, + output [ 2:0] adc_os); // internal signals diff --git a/projects/ad7616_sdz/zed/system_top_pi.v b/projects/ad7616_sdz/zed/system_top_pi.v index 0a21783d3..58c624a0a 100644 --- a/projects/ad7616_sdz/zed/system_top_pi.v +++ b/projects/ad7616_sdz/zed/system_top_pi.v @@ -41,122 +41,63 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - otg_vbusoc, + input otg_vbusoc, - adc_db, - adc_rd_n, - adc_wr_n, + inout [15:0] adc_db, + output adc_rd_n, + output adc_wr_n, - adc_cs_n, - adc_reset_n, - adc_convst, - adc_busy, - adc_seq_en, - adc_hw_rngsel, - adc_chsel); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - input otg_vbusoc; - - inout [15:0] adc_db; - output adc_rd_n; - output adc_wr_n; - - output adc_cs_n; - output adc_reset_n; - output adc_convst; - input adc_busy; - output adc_seq_en; - output [ 1:0] adc_hw_rngsel; - output [ 2:0] adc_chsel; + output adc_cs_n, + output adc_reset_n, + output adc_convst, + input adc_busy, + output adc_seq_en, + output [ 1:0] adc_hw_rngsel, + output [ 2:0] adc_chsel); // internal signals diff --git a/projects/ad7616_sdz/zed/system_top_si.v b/projects/ad7616_sdz/zed/system_top_si.v index 312baad48..38a78d819 100644 --- a/projects/ad7616_sdz/zed/system_top_si.v +++ b/projects/ad7616_sdz/zed/system_top_si.v @@ -41,130 +41,67 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - otg_vbusoc, + input otg_vbusoc, - spi_sclk, - spi_sdo, - spi_sdi_0, - spi_sdi_1, - spi_cs_n, + output spi_sclk, + output spi_sdo, + input spi_sdi_0, + input spi_sdi_1, + output spi_cs_n, - adc_reset_n, - adc_convst, - adc_busy, - adc_seq_en, - adc_hw_rngsel, - adc_chsel, - adc_crcen, - adc_burst, - adc_os); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - input otg_vbusoc; - - output spi_sclk; - output spi_sdo; - input spi_sdi_0; - input spi_sdi_1; - output spi_cs_n; - - output adc_reset_n; - output adc_convst; - input adc_busy; - output adc_seq_en; - output [ 1:0] adc_hw_rngsel; - output [ 2:0] adc_chsel; - output adc_crcen; - output adc_burst; - output [ 2:0] adc_os; + output adc_reset_n, + output adc_convst, + input adc_busy, + output adc_seq_en, + output [ 1:0] adc_hw_rngsel, + output [ 2:0] adc_chsel, + output adc_crcen, + output adc_burst, + output [ 2:0] adc_os); // internal signals diff --git a/projects/ad7768evb/common/ad7768_if.v b/projects/ad7768evb/common/ad7768_if.v index c51f44e04..c0642d217 100644 --- a/projects/ad7768evb/common/ad7768_if.v +++ b/projects/ad7768evb/common/ad7768_if.v @@ -41,45 +41,24 @@ module ad7768_if ( // device-interface - clk_in, - ready_in, - data_in, + input clk_in, + input ready_in, + input [ 7:0] data_in, // data path interface - adc_clk, - adc_valid, - adc_data, + output adc_clk, + output reg adc_valid, + output reg [ 31:0] adc_data, // control interface - up_sshot, - up_format, - up_crc_enable, - up_crc_4_or_16_n, - up_status_clr, - up_status); - - // device-interface - - input clk_in; - input ready_in; - input [ 7:0] data_in; - - // data path interface - - output adc_clk; - output adc_valid; - output [ 31:0] adc_data; - - // control interface - - input up_sshot; - input [ 1:0] up_format; - input up_crc_enable; - input up_crc_4_or_16_n; - input [ 35:0] up_status_clr; - output [ 35:0] up_status; + input up_sshot, + input [ 1:0] up_format, + input up_crc_enable, + input up_crc_4_or_16_n, + input [ 35:0] up_status_clr, + output [ 35:0] up_status); // internal registers @@ -92,8 +71,6 @@ module ad7768_if ( reg [ 2:0] adc_status_2 = 'd0; reg [ 2:0] adc_status_1 = 'd0; reg [ 2:0] adc_status_0 = 'd0; - reg adc_valid = 'd0; - reg [ 31:0] adc_data = 'd0; reg [ 2:0] adc_seq = 'd0; reg [ 4:0] adc_status = 'd0; reg [ 63:0] adc_crc_8 = 'd0; diff --git a/projects/ad7768evb/zed/system_top.v b/projects/ad7768evb/zed/system_top.v index 64814dba9..8b37d1d9a 100644 --- a/projects/ad7768evb/zed/system_top.v +++ b/projects/ad7768evb/zed/system_top.v @@ -41,137 +41,71 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - otg_vbusoc, + input otg_vbusoc, - clk_in, - ready_in, - data_in, + input clk_in, + input ready_in, + input [ 7:0] data_in, - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, - gpio_0_mode_0, - gpio_1_mode_1, - gpio_2_mode_2, - gpio_3_mode_3, - gpio_4_filter, - reset_n, - start_n, - sync_n, - sync_in_n, - mclk); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - input otg_vbusoc; - - input clk_in; - input ready_in; - input [ 7:0] data_in; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - inout gpio_0_mode_0; - inout gpio_1_mode_1; - inout gpio_2_mode_2; - inout gpio_3_mode_3; - inout gpio_4_filter; - inout reset_n; - inout start_n; - inout sync_n; - inout sync_in_n; - output mclk; + inout gpio_0_mode_0, + inout gpio_1_mode_1, + inout gpio_2_mode_2, + inout gpio_3_mode_3, + inout gpio_4_filter, + inout reset_n, + inout start_n, + inout sync_n, + inout sync_in_n, + output mclk); // internal signals diff --git a/projects/ad9265_fmc/common/ad9265_spi.v b/projects/ad9265_fmc/common/ad9265_spi.v index 6e1242802..2b59cdf24 100644 --- a/projects/ad9265_fmc/common/ad9265_spi.v +++ b/projects/ad9265_fmc/common/ad9265_spi.v @@ -39,23 +39,12 @@ module ad9265_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input [ 1:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio); - - // 4 wire - - input [ 1:0] spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; + inout spi_sdio); // internal registers diff --git a/projects/ad9265_fmc/zc706/system_top.v b/projects/ad9265_fmc/zc706/system_top.v index ccbb1880c..bb4fbccb0 100644 --- a/projects/ad9265_fmc/zc706/system_top.v +++ b/projects/ad9265_fmc/zc706/system_top.v @@ -40,101 +40,52 @@ `timescale 1ns/100ps module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - adc_clk_in_n, - adc_clk_in_p, - adc_data_in_n, - adc_data_in_p, - adc_data_or_n, - adc_data_or_p, - spi_clk, - spi_csn_adc, - spi_csn_clk, - spi_sdio -); - -inout [14:0] ddr_addr; -inout [ 2:0] ddr_ba; -inout ddr_cas_n; -inout ddr_ck_n; -inout ddr_ck_p; -inout ddr_cke; -inout ddr_cs_n; -inout [ 3:0] ddr_dm; -inout [31:0] ddr_dq; -inout [ 3:0] ddr_dqs_n; -inout [ 3:0] ddr_dqs_p; -inout ddr_odt; -inout ddr_ras_n; -inout ddr_reset_n; -inout ddr_we_n; - - -inout fixed_io_ddr_vrn; -inout fixed_io_ddr_vrp; -inout [53:0] fixed_io_mio; -inout fixed_io_ps_clk; -inout fixed_io_ps_porb; -inout fixed_io_ps_srstb; - -inout [14:0] gpio_bd; - -output hdmi_out_clk; -output hdmi_vsync; -output hdmi_hsync; -output hdmi_data_e; -output [23:0] hdmi_data; - -output spdif; - -inout iic_scl; -inout iic_sda; - -input adc_clk_in_n; -input adc_clk_in_p; -input [ 7:0] adc_data_in_n; -input [ 7:0] adc_data_in_p; -input adc_data_or_n; -input adc_data_or_p; -output spi_clk; -output spi_csn_adc; -output spi_csn_clk; -inout spi_sdio; + input adc_clk_in_n, + input adc_clk_in_p, + input [ 7:0] adc_data_in_n, + input [ 7:0] adc_data_in_p, + input adc_data_or_n, + input adc_data_or_p, + output spi_clk, + output spi_csn_adc, + output spi_csn_clk, + inout spi_sdio); // internal signals wire [ 1:0] spi_csn; diff --git a/projects/ad9434_fmc/common/ad9434_spi.v b/projects/ad9434_fmc/common/ad9434_spi.v index f2de32a10..c12e073d4 100644 --- a/projects/ad9434_fmc/common/ad9434_spi.v +++ b/projects/ad9434_fmc/common/ad9434_spi.v @@ -40,23 +40,12 @@ module ad9434_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input [ 1:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio); - - // 4 wire - - input [ 1:0] spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; + inout spi_sdio); // internal registers diff --git a/projects/ad9434_fmc/zc706/system_top.v b/projects/ad9434_fmc/zc706/system_top.v index d246337c4..07a569aa6 100644 --- a/projects/ad9434_fmc/zc706/system_top.v +++ b/projects/ad9434_fmc/zc706/system_top.v @@ -41,101 +41,53 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - adc_clk_p, - adc_clk_n, - adc_data_p, - adc_data_n, - adc_or_p, - adc_or_n, + input adc_clk_p, + input adc_clk_n, + input [11:0] adc_data_p, + input [11:0] adc_data_n, + input adc_or_p, + input adc_or_n, - spi_csn_clk, - spi_csn_adc, - spi_sclk, - spi_dio); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input adc_clk_p; - input adc_clk_n; - input [11:0] adc_data_p; - input [11:0] adc_data_n; - input adc_or_p; - input adc_or_n; - - output spi_csn_clk; - output spi_csn_adc; - output spi_sclk; - inout spi_dio; + output spi_csn_clk, + output spi_csn_adc, + output spi_sclk, + inout spi_dio); // internal signals diff --git a/projects/ad9467_fmc/common/ad9467_spi.v b/projects/ad9467_fmc/common/ad9467_spi.v index 322cf4656..fd208a5e7 100644 --- a/projects/ad9467_fmc/common/ad9467_spi.v +++ b/projects/ad9467_fmc/common/ad9467_spi.v @@ -39,23 +39,12 @@ module ad9467_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input [ 1:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio); - - // 4 wire - - input [ 1:0] spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; + inout spi_sdio); // internal registers diff --git a/projects/ad9467_fmc/kc705/system_top.v b/projects/ad9467_fmc/kc705/system_top.v index a44c82b11..54605a632 100644 --- a/projects/ad9467_fmc/kc705/system_top.v +++ b/projects/ad9467_fmc/kc705/system_top.v @@ -41,136 +41,70 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_1_n, - ddr3_1_p, - ddr3_reset_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ras_n, - ddr3_we_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, + output [ 2:0] ddr3_1_n, + output [ 1:0] ddr3_1_p, + output ddr3_reset_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output ddr3_ras_n, + output ddr3_we_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, - mdio_mdc, - mdio_mdio, - mii_rst_n, - mii_col, - mii_crs, - mii_rx_clk, - mii_rx_er, - mii_rx_dv, - mii_rxd, - mii_tx_clk, - mii_tx_en, - mii_txd, + output mdio_mdc, + inout mdio_mdio, + output mii_rst_n, + input mii_col, + input mii_crs, + input mii_rx_clk, + input mii_rx_er, + input mii_rx_dv, + input [ 3:0] mii_rxd, + input mii_tx_clk, + output mii_tx_en, + output [ 3:0] mii_txd, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_dq_io, - linear_flash_oen, - linear_flash_wen, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + inout [15:0] linear_flash_dq_io, + output linear_flash_oen, + output linear_flash_wen, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [16:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - adc_clk_in_n, - adc_clk_in_p, - adc_data_in_n, - adc_data_in_p, - adc_data_or_n, - adc_data_or_p, - spi_clk, - spi_csn_adc, - spi_csn_clk, - spi_sdio -); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [ 2:0] ddr3_1_n; - output [ 1:0] ddr3_1_p; - output ddr3_reset_n; - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output ddr3_ras_n; - output ddr3_we_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - - output mdio_mdc; - inout mdio_mdio; - output mii_rst_n; - input mii_col; - input mii_crs; - input mii_rx_clk; - input mii_rx_er; - input mii_rx_dv; - input [ 3:0] mii_rxd; - input mii_tx_clk; - output mii_tx_en; - output [ 3:0] mii_txd; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - inout [15:0] linear_flash_dq_io; - output linear_flash_oen; - output linear_flash_wen; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [16:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input adc_clk_in_n; - input adc_clk_in_p; - input [ 7:0] adc_data_in_n; - input [ 7:0] adc_data_in_p; - input adc_data_or_n; - input adc_data_or_p; - output spi_clk; - output spi_csn_adc; - output spi_csn_clk; - inout spi_sdio; + input adc_clk_in_n, + input adc_clk_in_p, + input [ 7:0] adc_data_in_n, + input [ 7:0] adc_data_in_p, + input adc_data_or_n, + input adc_data_or_p, + output spi_clk, + output spi_csn_adc, + output spi_csn_clk, + inout spi_sdio); // internal signals wire [ 7:0] spi_csn; diff --git a/projects/ad9467_fmc/zed/system_top.v b/projects/ad9467_fmc/zed/system_top.v index 5ba52f2bf..c60d6b02d 100644 --- a/projects/ad9467_fmc/zed/system_top.v +++ b/projects/ad9467_fmc/zed/system_top.v @@ -40,122 +40,62 @@ `timescale 1ns/100ps module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - otg_vbusoc, + input otg_vbusoc, - adc_clk_in_n, - adc_clk_in_p, - adc_data_in_n, - adc_data_in_p, - adc_data_or_n, - adc_data_or_p, - spi_clk, - spi_csn_adc, - spi_csn_clk, - spi_sdio -); - -inout [14:0] ddr_addr; -inout [ 2:0] ddr_ba; -inout ddr_cas_n; -inout ddr_ck_n; -inout ddr_ck_p; -inout ddr_cke; -inout ddr_cs_n; -inout [ 3:0] ddr_dm; -inout [31:0] ddr_dq; -inout [ 3:0] ddr_dqs_n; -inout [ 3:0] ddr_dqs_p; -inout ddr_odt; -inout ddr_ras_n; -inout ddr_reset_n; -inout ddr_we_n; - - -inout fixed_io_ddr_vrn; -inout fixed_io_ddr_vrp; -inout [53:0] fixed_io_mio; -inout fixed_io_ps_clk; -inout fixed_io_ps_porb; -inout fixed_io_ps_srstb; - -inout [31:0] gpio_bd; - -output hdmi_out_clk; -output hdmi_vsync; -output hdmi_hsync; -output hdmi_data_e; -output [15:0] hdmi_data; - -output spdif; - -output i2s_mclk; -output i2s_bclk; -output i2s_lrclk; -output i2s_sdata_out; -input i2s_sdata_in; - - -inout iic_scl; -inout iic_sda; -inout [ 1:0] iic_mux_scl; -inout [ 1:0] iic_mux_sda; - -input otg_vbusoc; - -input adc_clk_in_n; -input adc_clk_in_p; -input [ 7:0] adc_data_in_n; -input [ 7:0] adc_data_in_p; -input adc_data_or_n; -input adc_data_or_p; -output spi_clk; -output spi_csn_adc; -output spi_csn_clk; -inout spi_sdio; + input adc_clk_in_n, + input adc_clk_in_p, + input [ 7:0] adc_data_in_n, + input [ 7:0] adc_data_in_p, + input adc_data_or_n, + input adc_data_or_p, + output spi_clk, + output spi_csn_adc, + output spi_csn_clk, + inout spi_sdio); // internal signals wire [ 1:0] spi_csn; diff --git a/projects/ad9739a_fmc/zc706/system_top.v b/projects/ad9739a_fmc/zc706/system_top.v index 745a859c9..0a5e41737 100644 --- a/projects/ad9739a_fmc/zc706/system_top.v +++ b/projects/ad9739a_fmc/zc706/system_top.v @@ -41,107 +41,56 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_data_out_a_p, - dac_data_out_a_n, - dac_data_out_b_p, - dac_data_out_b_n, + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output [13:0] dac_data_out_a_p, + output [13:0] dac_data_out_a_n, + output [13:0] dac_data_out_b_p, + output [13:0] dac_data_out_b_n, - spi_csn_clk, - spi_csn_dac, - spi_clk, - spi_mosi, - spi_miso); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output [13:0] dac_data_out_a_p; - output [13:0] dac_data_out_a_n; - output [13:0] dac_data_out_b_p; - output [13:0] dac_data_out_b_n; - - output spi_csn_clk; - output spi_csn_dac; - output spi_clk; - output spi_mosi; - input spi_miso; + output spi_csn_clk, + output spi_csn_dac, + output spi_clk, + output spi_mosi, + input spi_miso); // internal signals diff --git a/projects/adrv9371x/zc706/system_top.v b/projects/adrv9371x/zc706/system_top.v index ddda7293e..fc787214c 100644 --- a/projects/adrv9371x/zc706/system_top.v +++ b/projects/adrv9371x/zc706/system_top.v @@ -39,224 +39,114 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - ref_clk0_p, - ref_clk0_n, - ref_clk1_p, - ref_clk1_n, - rx_data_p, - rx_data_n, - tx_data_p, - tx_data_n, - rx_sync_p, - rx_sync_n, - rx_os_sync_p, - rx_os_sync_n, - tx_sync_p, - tx_sync_n, - sysref_p, - sysref_n, + input ref_clk0_p, + input ref_clk0_n, + input ref_clk1_p, + input ref_clk1_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, + output rx_sync_p, + output rx_sync_n, + output rx_os_sync_p, + output rx_os_sync_n, + input tx_sync_p, + input tx_sync_n, + input sysref_p, + input sysref_n, - spi_csn_ad9528, - spi_csn_ad9371, - spi_clk, - spi_mosi, - spi_miso, + output spi_csn_ad9528, + output spi_csn_ad9371, + output spi_clk, + output spi_mosi, + input spi_miso, - ad9528_reset_b, - ad9528_sysref_req, - ad9371_tx1_enable, - ad9371_tx2_enable, - ad9371_rx1_enable, - ad9371_rx2_enable, - ad9371_test, - ad9371_reset_b, - ad9371_gpint, + inout ad9528_reset_b, + inout ad9528_sysref_req, + inout ad9371_tx1_enable, + inout ad9371_tx2_enable, + inout ad9371_rx1_enable, + inout ad9371_rx2_enable, + inout ad9371_test, + inout ad9371_reset_b, + inout ad9371_gpint, - ad9371_gpio_00, - ad9371_gpio_01, - ad9371_gpio_02, - ad9371_gpio_03, - ad9371_gpio_04, - ad9371_gpio_05, - ad9371_gpio_06, - ad9371_gpio_07, - ad9371_gpio_15, - ad9371_gpio_08, - ad9371_gpio_09, - ad9371_gpio_10, - ad9371_gpio_11, - ad9371_gpio_12, - ad9371_gpio_14, - ad9371_gpio_13, - ad9371_gpio_17, - ad9371_gpio_16, - ad9371_gpio_18, + inout ad9371_gpio_00, + inout ad9371_gpio_01, + inout ad9371_gpio_02, + inout ad9371_gpio_03, + inout ad9371_gpio_04, + inout ad9371_gpio_05, + inout ad9371_gpio_06, + inout ad9371_gpio_07, + inout ad9371_gpio_15, + inout ad9371_gpio_08, + inout ad9371_gpio_09, + inout ad9371_gpio_10, + inout ad9371_gpio_11, + inout ad9371_gpio_12, + inout ad9371_gpio_14, + inout ad9371_gpio_13, + inout ad9371_gpio_17, + inout ad9371_gpio_16, + inout ad9371_gpio_18, - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input ref_clk0_p; - input ref_clk0_n; - input ref_clk1_p; - input ref_clk1_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - output [ 3:0] tx_data_p; - output [ 3:0] tx_data_n; - output rx_sync_p; - output rx_sync_n; - output rx_os_sync_p; - output rx_os_sync_n; - input tx_sync_p; - input tx_sync_n; - input sysref_p; - input sysref_n; - - output spi_csn_ad9528; - output spi_csn_ad9371; - output spi_clk; - output spi_mosi; - input spi_miso; - - inout ad9528_reset_b; - inout ad9528_sysref_req; - inout ad9371_tx1_enable; - inout ad9371_tx2_enable; - inout ad9371_rx1_enable; - inout ad9371_rx2_enable; - inout ad9371_test; - inout ad9371_reset_b; - inout ad9371_gpint; - - inout ad9371_gpio_00; - inout ad9371_gpio_01; - inout ad9371_gpio_02; - inout ad9371_gpio_03; - inout ad9371_gpio_04; - inout ad9371_gpio_05; - inout ad9371_gpio_06; - inout ad9371_gpio_07; - inout ad9371_gpio_15; - inout ad9371_gpio_08; - inout ad9371_gpio_09; - inout ad9371_gpio_10; - inout ad9371_gpio_11; - inout ad9371_gpio_12; - inout ad9371_gpio_14; - inout ad9371_gpio_13; - inout ad9371_gpio_17; - inout ad9371_gpio_16; - inout ad9371_gpio_18; - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n); // internal signals diff --git a/projects/adv7511/ac701/system_top.v b/projects/adv7511/ac701/system_top.v index 1461c7d30..bcbf0a827 100644 --- a/projects/adv7511/ac701/system_top.v +++ b/projects/adv7511/ac701/system_top.v @@ -41,105 +41,55 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - phy_reset_n, - phy_mdc, - phy_mdio, - phy_tx_clk, - phy_tx_ctrl, - phy_tx_data, - phy_rx_clk, - phy_rx_ctrl, - phy_rx_data, + output phy_reset_n, + output phy_mdc, + inout phy_mdio, + output phy_tx_clk, + output phy_tx_ctrl, + output [ 3:0] phy_tx_data, + input phy_rx_clk, + input phy_rx_ctrl, + input [ 3:0] phy_rx_data, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [12:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - hdmi_out_clk, - hdmi_hsync, - hdmi_vsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_hsync, + output hdmi_vsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - output phy_reset_n; - output phy_mdc; - inout phy_mdio; - output phy_tx_clk; - output phy_tx_ctrl; - output [ 3:0] phy_tx_data; - input phy_rx_clk; - input phy_rx_ctrl; - input [ 3:0] phy_rx_data; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [12:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - output hdmi_out_clk; - output hdmi_hsync; - output hdmi_vsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; + output spdif); // internal signals diff --git a/projects/adv7511/kc705/system_top.v b/projects/adv7511/kc705/system_top.v index 6be7fd3ed..980fa9e56 100644 --- a/projects/adv7511/kc705/system_top.v +++ b/projects/adv7511/kc705/system_top.v @@ -41,129 +41,67 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_1_n, - ddr3_1_p, - ddr3_reset_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ras_n, - ddr3_we_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, + output [ 2:0] ddr3_1_n, + output [ 1:0] ddr3_1_p, + output ddr3_reset_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output ddr3_ras_n, + output ddr3_we_n, + output ddr3_ck_n, + output ddr3_ck_p, + output ddr3_cke, + output ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output ddr3_odt, - mdio_mdc, - mdio_mdio, - mii_rst_n, - mii_col, - mii_crs, - mii_rx_clk, - mii_rx_er, - mii_rx_dv, - mii_rxd, - mii_tx_clk, - mii_tx_en, - mii_txd, + output mdio_mdc, + inout mdio_mdio, + output mii_rst_n, + input mii_col, + input mii_crs, + input mii_rx_clk, + input mii_rx_er, + input mii_rx_dv, + input [ 3:0] mii_rxd, + input mii_tx_clk, + output mii_tx_en, + output [ 3:0] mii_txd, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_dq_io, - linear_flash_oen, - linear_flash_wen, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + inout [15:0] linear_flash_dq_io, + output linear_flash_oen, + output linear_flash_wen, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [16:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - hdmi_out_clk, - hdmi_hsync, - hdmi_vsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_hsync, + output hdmi_vsync, + output hdmi_data_e, + output [15:0] hdmi_data, - spdif); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [ 2:0] ddr3_1_n; - output [ 1:0] ddr3_1_p; - output ddr3_reset_n; - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output ddr3_ras_n; - output ddr3_we_n; - output ddr3_ck_n; - output ddr3_ck_p; - output ddr3_cke; - output ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output ddr3_odt; - - output mdio_mdc; - inout mdio_mdio; - output mii_rst_n; - input mii_col; - input mii_crs; - input mii_rx_clk; - input mii_rx_er; - input mii_rx_dv; - input [ 3:0] mii_rxd; - input mii_tx_clk; - output mii_tx_en; - output [ 3:0] mii_txd; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - inout [15:0] linear_flash_dq_io; - output linear_flash_oen; - output linear_flash_wen; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [16:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - output hdmi_out_clk; - output hdmi_hsync; - output hdmi_vsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; + output spdif); // internal signals diff --git a/projects/adv7511/kcu105/system_top.v b/projects/adv7511/kcu105/system_top.v index 751017452..c3affb590 100644 --- a/projects/adv7511/kcu105/system_top.v +++ b/projects/adv7511/kcu105/system_top.v @@ -41,99 +41,52 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr4_act_n, - ddr4_addr, - ddr4_ba, - ddr4_bg, - ddr4_ck_p, - ddr4_ck_n, - ddr4_cke, - ddr4_cs_n, - ddr4_dm_n, - ddr4_dq, - ddr4_dqs_p, - ddr4_dqs_n, - ddr4_odt, - ddr4_reset_n, + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, - mdio_mdc, - mdio_mdio, - phy_clk_p, - phy_clk_n, - phy_rst_n, - phy_rx_p, - phy_rx_n, - phy_tx_p, - phy_tx_n, + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, - fan_pwm, + output fan_pwm, - gpio_bd, + inout [16:0] gpio_bd, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - hdmi_out_clk, - hdmi_hsync, - hdmi_vsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_hsync, + output hdmi_vsync, + output hdmi_data_e, + output [15:0] hdmi_data, - spdif); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output ddr4_act_n; - output [16:0] ddr4_addr; - output [ 1:0] ddr4_ba; - output [ 0:0] ddr4_bg; - output ddr4_ck_p; - output ddr4_ck_n; - output [ 0:0] ddr4_cke; - output [ 0:0] ddr4_cs_n; - inout [ 7:0] ddr4_dm_n; - inout [63:0] ddr4_dq; - inout [ 7:0] ddr4_dqs_p; - inout [ 7:0] ddr4_dqs_n; - output [ 0:0] ddr4_odt; - output ddr4_reset_n; - - output mdio_mdc; - inout mdio_mdio; - input phy_clk_p; - input phy_clk_n; - output phy_rst_n; - input phy_rx_p; - input phy_rx_n; - output phy_tx_p; - output phy_tx_n; - - output fan_pwm; - - inout [16:0] gpio_bd; - - inout iic_scl; - inout iic_sda; - - output hdmi_out_clk; - output hdmi_hsync; - output hdmi_vsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; + output spdif); // internal signals diff --git a/projects/adv7511/mitx045/system_top.v b/projects/adv7511/mitx045/system_top.v index c8065d62a..0a2821f4c 100644 --- a/projects/adv7511/mitx045/system_top.v +++ b/projects/adv7511/mitx045/system_top.v @@ -41,89 +41,47 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [11:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - spdif, + output spdif, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - iic_scl, - iic_sda); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [11:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - inout iic_scl; - inout iic_sda; + inout iic_scl, + inout iic_sda); // internal signals diff --git a/projects/adv7511/vc707/system_top.v b/projects/adv7511/vc707/system_top.v index 2f58c8bd7..6a7053ffe 100644 --- a/projects/adv7511/vc707/system_top.v +++ b/projects/adv7511/vc707/system_top.v @@ -41,121 +41,63 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - sgmii_rxp, - sgmii_rxn, - sgmii_txp, - sgmii_txn, + input sgmii_rxp, + input sgmii_rxn, + output sgmii_txp, + output sgmii_txn, - phy_rstn, - mgt_clk_p, - mgt_clk_n, - mdio_mdc, - mdio_mdio, + output phy_rstn, + input mgt_clk_p, + input mgt_clk_n, + output mdio_mdc, + inout mdio_mdio, - fan_pwm, + output fan_pwm, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_oen, - linear_flash_wen, - linear_flash_dq_io, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + output linear_flash_oen, + output linear_flash_wen, + inout [15:0] linear_flash_dq_io, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [20:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - hdmi_out_clk, - hdmi_hsync, - hdmi_vsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_hsync, + output hdmi_vsync, + output hdmi_data_e, + output [35:0] hdmi_data, - spdif); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - input sgmii_rxp; - input sgmii_rxn; - output sgmii_txp; - output sgmii_txn; - - output phy_rstn; - input mgt_clk_p; - input mgt_clk_n; - output mdio_mdc; - inout mdio_mdio; - - output fan_pwm; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - output linear_flash_oen; - output linear_flash_wen; - inout [15:0] linear_flash_dq_io; - - inout [ 6:0] gpio_lcd; - inout [20:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - output hdmi_out_clk; - output hdmi_hsync; - output hdmi_vsync; - output hdmi_data_e; - output [35:0] hdmi_data; - - output spdif; + output spdif); // internal signals diff --git a/projects/adv7511/zc702/system_top.v b/projects/adv7511/zc702/system_top.v index 7a94305f6..4df095ecf 100644 --- a/projects/adv7511/zc702/system_top.v +++ b/projects/adv7511/zc702/system_top.v @@ -41,77 +41,41 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [15:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [15:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; + inout iic_scl, + inout iic_sda); // internal signals diff --git a/projects/adv7511/zc706/system_top.v b/projects/adv7511/zc706/system_top.v index 281f57ec4..cc6c848c7 100644 --- a/projects/adv7511/zc706/system_top.v +++ b/projects/adv7511/zc706/system_top.v @@ -41,77 +41,41 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; + inout iic_scl, + inout iic_sda); // internal signals diff --git a/projects/adv7511/zed/system_top.v b/projects/adv7511/zed/system_top.v index 67f4c72c8..bdf123542 100644 --- a/projects/adv7511/zed/system_top.v +++ b/projects/adv7511/zed/system_top.v @@ -41,98 +41,51 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - otg_vbusoc); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - input otg_vbusoc; + input otg_vbusoc); // internal signals diff --git a/projects/cftl_cip/zed/system_top.v b/projects/cftl_cip/zed/system_top.v index 360694b5a..2b6fa0ce8 100644 --- a/projects/cftl_cip/zed/system_top.v +++ b/projects/cftl_cip/zed/system_top.v @@ -41,112 +41,58 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - otg_vbusoc, + input otg_vbusoc, - pmod_spi_cs, - pmod_spi_miso, - pmod_spi_clk, - pmod_spi_convst, + output pmod_spi_cs, + input pmod_spi_miso, + output pmod_spi_clk, + output pmod_spi_convst, - pmod_gpio); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - input otg_vbusoc; - - output pmod_spi_cs; - input pmod_spi_miso; - output pmod_spi_clk; - output pmod_spi_convst; - - input pmod_gpio; + input pmod_gpio); // internal signals diff --git a/projects/cftl_std/zed/system_top.v b/projects/cftl_std/zed/system_top.v index c5b8e4244..3d9aee446 100644 --- a/projects/cftl_std/zed/system_top.v +++ b/projects/cftl_std/zed/system_top.v @@ -41,129 +41,67 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - iic_cftl_scl_io, - iic_cftl_sda_io, + inout iic_cftl_scl_io, + inout iic_cftl_sda_io, - spi0_mosi, - spi0_miso, - spi0_clk, - spi0_csn, + output spi0_mosi, + input spi0_miso, + output spi0_clk, + output spi0_csn, - spi1_mosi, - spi1_miso, - spi1_clk, - spi1_csn0, - spi1_csn1, + output spi1_mosi, + input spi1_miso, + output spi1_clk, + output spi1_csn0, + output spi1_csn1, - gpio_cftl, + inout [ 1:0] gpio_cftl, - otg_vbusoc); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - inout iic_cftl_scl_io; - inout iic_cftl_sda_io; - - output spi0_mosi; - input spi0_miso; - output spi0_clk; - output spi0_csn; - - output spi1_mosi; - input spi1_miso; - output spi1_clk; - output spi1_csn0; - output spi1_csn1; - - inout [ 1:0] gpio_cftl; - - input otg_vbusoc; + input otg_vbusoc); // internal signals diff --git a/projects/cn0363/microzed/system_top.v b/projects/cn0363/microzed/system_top.v index d123450d7..3715aa677 100644 --- a/projects/cn0363/microzed/system_top.v +++ b/projects/cn0363/microzed/system_top.v @@ -40,71 +40,38 @@ `timescale 1ns/100ps module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - spi_sdo, - spi_sdi, - spi_cs, - spi_sclk, - led_clk_o, - gain0_o, - gain1_o, + inout spi_sdo, + input spi_sdi, + output [ 1:0] spi_cs, + output spi_sclk, + output led_clk_o, + output gain0_o, + output gain1_o, - otg_vbusoc); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - input spi_sdi; - inout spi_sdo; - output spi_sclk; - output [ 1:0] spi_cs; - output led_clk_o; - output gain0_o; - output gain1_o; - - input otg_vbusoc; + input otg_vbusoc); // internal signals diff --git a/projects/cn0363/zed/system_top.v b/projects/cn0363/zed/system_top.v index 4c13ce0f5..f02b7c82d 100644 --- a/projects/cn0363/zed/system_top.v +++ b/projects/cn0363/zed/system_top.v @@ -40,114 +40,59 @@ `timescale 1ns/100ps module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - spi_sdo, - spi_sdi, - spi_cs, - spi_sclk, - led_clk_o, - gain0_o, - gain1_o, + inout spi_sdo, + input spi_sdi, + output [ 1:0] spi_cs, + output spi_sclk, + output led_clk_o, + output gain0_o, + output gain1_o, - otg_vbusoc); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - input spi_sdi; - inout spi_sdo; - output spi_sclk; - output [ 1:0] spi_cs; - output led_clk_o; - output gain0_o; - output gain1_o; - - input otg_vbusoc; + input otg_vbusoc); // internal signals diff --git a/projects/common/a5gte/system_top.v b/projects/common/a5gte/system_top.v index 8891789e6..9bbebb1df 100644 --- a/projects/common/a5gte/system_top.v +++ b/projects/common/a5gte/system_top.v @@ -41,55 +41,29 @@ module system_top ( // fpga-fpga interface - eth_rx_clk, - eth_rx_cntrl, - eth_rx_data, - eth_tx_clk, - eth_tx_cntrl, - eth_tx_data, - eth_mdc, - eth_mdio_i, - eth_mdio_o, - eth_mdio_t, - eth_phy_resetn, + output eth_rx_clk, + output eth_rx_cntrl, + output [ 3:0] eth_rx_data, + input eth_tx_clk, + input eth_tx_cntrl, + input [ 3:0] eth_tx_data, + input eth_mdc, + output eth_mdio_i, + input eth_mdio_o, + input eth_mdio_t, + input eth_phy_resetn, // phy interface - phy_resetn, - phy_rx_clk, - phy_rx_cntrl, - phy_rx_data, - phy_tx_clk_out, - phy_tx_cntrl, - phy_tx_data, - phy_mdc, - phy_mdio); - - // fpga-fpga interface - - output eth_rx_clk; - output eth_rx_cntrl; - output [ 3:0] eth_rx_data; - input eth_tx_clk; - input eth_tx_cntrl; - input [ 3:0] eth_tx_data; - input eth_mdc; - output eth_mdio_i; - input eth_mdio_o; - input eth_mdio_t; - input eth_phy_resetn; - - // phy interface - - output phy_resetn; - input phy_rx_clk; - input phy_rx_cntrl; - input [ 3:0] phy_rx_data; - output phy_tx_clk_out; - output phy_tx_cntrl; - output [ 3:0] phy_tx_data; - output phy_mdc; - inout phy_mdio; + output phy_resetn, + input phy_rx_clk, + input phy_rx_cntrl, + input [ 3:0] phy_rx_data, + output phy_tx_clk_out, + output phy_tx_cntrl, + output [ 3:0] phy_tx_data, + output phy_mdc, + inout phy_mdio); wire eth_rx_clk_90; wire eth_tx_clk_90; diff --git a/projects/daq1/common/daq1_spi.v b/projects/daq1/common/daq1_spi.v index 449329bbd..7647d7afa 100644 --- a/projects/daq1/common/daq1_spi.v +++ b/projects/daq1/common/daq1_spi.v @@ -39,23 +39,12 @@ module daq1_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio); - - // 4 wire - - input spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; + inout spi_sdio); // device address diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v index 6671ae029..c346913bd 100644 --- a/projects/daq1/cpld/daq1_cpld.v +++ b/projects/daq1/cpld/daq1_cpld.v @@ -41,66 +41,37 @@ module daq1_cpld ( // FMC SPI interface - fmc_spi_sclk, - fmc_spi_csn, - fmc_spi_sdio, - fmc_irq, + input fmc_spi_sclk, + input fmc_spi_csn, + inout fmc_spi_sdio, + output fmc_irq, // on board SPI interface - adc_spicsn, - dac_spicsn, - clk_spicsn, - sclk, - sdio, + output adc_spicsn, + output dac_spicsn, + output clk_spicsn, + output sclk, + inout sdio, // control and status lines - adc_fda, - adc_fdb, - adc_status_p, - adc_status_n, - adc_pwdn_stby, + input adc_fda, + input adc_fdb, + input adc_status_p, + input adc_status_n, + output adc_pwdn_stby, - dac_irqn, - dac_resetn, - - clk_status1, - clk_status2, - clk_pwdnn, - clk_syncn, - clk_resetn + input dac_irqn, + output dac_resetn, + input clk_status1, + input clk_status2, + output clk_pwdnn, + output clk_syncn, + output clk_resetn ); - input fmc_spi_csn; - input fmc_spi_sclk; - inout fmc_spi_sdio; - output fmc_irq; - - output adc_spicsn; - output dac_spicsn; - output clk_spicsn; - output sclk; - inout sdio; - - // control and status lines - - input adc_fda; - input adc_fdb; - input adc_status_p; - input adc_status_n; - output adc_pwdn_stby; - - input dac_irqn; - output dac_resetn; - - input clk_status1; - input clk_status2; - output clk_pwdnn; - output clk_syncn; - output clk_resetn; - // FMC SPI Selects localparam [ 7:0] FMC_SPI_SEL_AD9684 = 8'h80; diff --git a/projects/daq1/zc706/system_top.v b/projects/daq1/zc706/system_top.v index 2741a9b73..44c84facd 100644 --- a/projects/daq1/zc706/system_top.v +++ b/projects/daq1/zc706/system_top.v @@ -39,156 +39,80 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_frame_out_p, - dac_frame_out_n, - dac_data_out_p, - dac_data_out_n, + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output dac_frame_out_p, + output dac_frame_out_n, + output [15:0] dac_data_out_p, + output [15:0] dac_data_out_n, - adc_clk_in_p, - adc_clk_in_n, - adc_data_in_p, - adc_data_in_n, + input adc_clk_in_p, + input adc_clk_in_n, + input [13:0] adc_data_in_p, + input [13:0] adc_data_in_n, - spi_clk, - spi_csn, - spi_sdio, - spi_int, + output spi_clk, + output spi_csn, + inout spi_sdio, + input spi_int, - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n -); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output dac_frame_out_p; - output dac_frame_out_n; - output [15:0] dac_data_out_p; - output [15:0] dac_data_out_n; - - input adc_clk_in_p; - input adc_clk_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - - output spi_clk; - output spi_csn; - inout spi_sdio; - input spi_int; - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n); // internal signals diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v index 790563d09..7885e06b9 100644 --- a/projects/daq2/a10gx/system_top.v +++ b/projects/daq2/a10gx/system_top.v @@ -41,147 +41,75 @@ module system_top ( // clock and resets - sys_clk, - sys_resetn, + input sys_clk, + input sys_resetn, // ddr3 - ddr3_clk_p, - ddr3_clk_n, - ddr3_a, - ddr3_ba, - ddr3_cke, - ddr3_cs_n, - ddr3_odt, - ddr3_reset_n, - ddr3_we_n, - ddr3_ras_n, - ddr3_cas_n, - ddr3_dqs_p, - ddr3_dqs_n, - ddr3_dq, - ddr3_dm, - ddr3_rzq, - ddr3_ref_clk, + output ddr3_clk_p, + output ddr3_clk_n, + output [ 14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_odt, + output ddr3_reset_n, + output ddr3_we_n, + output ddr3_ras_n, + output ddr3_cas_n, + inout [ 7:0] ddr3_dqs_p, + inout [ 7:0] ddr3_dqs_n, + inout [ 63:0] ddr3_dq, + output [ 7:0] ddr3_dm, + input ddr3_rzq, + input ddr3_ref_clk, // ethernet - eth_ref_clk, - eth_rxd, - eth_txd, - eth_mdc, - eth_mdio, - eth_resetn, - eth_intn, + input eth_ref_clk, + input eth_rxd, + output eth_txd, + output eth_mdc, + inout eth_mdio, + output eth_resetn, + input eth_intn, // board gpio - gpio_bd_i, - gpio_bd_o, + input [ 10:0] gpio_bd_i, + output [ 15:0] gpio_bd_o, // lane interface - rx_ref_clk, - rx_sysref, - rx_sync, - rx_data, - tx_ref_clk, - tx_sysref, - tx_sync, - tx_data, + input rx_ref_clk, + input rx_sysref, + output rx_sync, + input [ 3:0] rx_data, + input tx_ref_clk, + input tx_sysref, + input tx_sync, + output [ 3:0] tx_data, // gpio - trig, - adc_fdb, - adc_fda, - dac_irq, - clkd_status, - adc_pd, - dac_txen, - dac_reset, - clkd_sync, + input trig, + input adc_fdb, + input adc_fda, + input dac_irq, + input [ 1:0] clkd_status, + output adc_pd, + output dac_txen, + output dac_reset, + output clkd_sync, // spi - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, - spi_clk, - spi_sdio, - spi_dir); - - // clock and resets - - input sys_clk; - input sys_resetn; - - // ddr3 - - output ddr3_clk_p; - output ddr3_clk_n; - output [ 14:0] ddr3_a; - output [ 2:0] ddr3_ba; - output ddr3_cke; - output ddr3_cs_n; - output ddr3_odt; - output ddr3_reset_n; - output ddr3_we_n; - output ddr3_ras_n; - output ddr3_cas_n; - inout [ 7:0] ddr3_dqs_p; - inout [ 7:0] ddr3_dqs_n; - inout [ 63:0] ddr3_dq; - output [ 7:0] ddr3_dm; - input ddr3_rzq; - input ddr3_ref_clk; - - // ethernet - - input eth_ref_clk; - input eth_rxd; - output eth_txd; - output eth_mdc; - inout eth_mdio; - output eth_resetn; - input eth_intn; - - // board gpio - - input [ 10:0] gpio_bd_i; - output [ 15:0] gpio_bd_o; - - // lane interface - - input rx_ref_clk; - input rx_sysref; - output rx_sync; - input [ 3:0] rx_data; - input tx_ref_clk; - input tx_sysref; - input tx_sync; - output [ 3:0] tx_data; - - // gpio - - input trig; - input adc_fdb; - input adc_fda; - input dac_irq; - input [ 1:0] clkd_status; - output adc_pd; - output dac_txen; - output dac_reset; - output clkd_sync; - - // spi - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; - output spi_clk; - inout spi_sdio; - output spi_dir; + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); // internal signals diff --git a/projects/daq2/common/daq2_spi.v b/projects/daq2/common/daq2_spi.v index 279199128..a4ce9b1f8 100644 --- a/projects/daq2/common/daq2_spi.v +++ b/projects/daq2/common/daq2_spi.v @@ -39,25 +39,13 @@ module daq2_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input [ 2:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio, - spi_dir); - - // 4 wire - - input [ 2:0] spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; - output spi_dir; + inout spi_sdio, + output spi_dir); // internal registers diff --git a/projects/daq2/kc705/system_top.v b/projects/daq2/kc705/system_top.v index aac500993..d681dcde1 100644 --- a/projects/daq2/kc705/system_top.v +++ b/projects/daq2/kc705/system_top.v @@ -39,189 +39,97 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_1_n, - ddr3_1_p, - ddr3_reset_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ras_n, - ddr3_we_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, + output [ 2:0] ddr3_1_n, + output [ 1:0] ddr3_1_p, + output ddr3_reset_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output ddr3_ras_n, + output ddr3_we_n, + output ddr3_ck_n, + output ddr3_ck_p, + output ddr3_cke, + output ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output ddr3_odt, - mdio_mdc, - mdio_mdio, - mii_rst_n, - mii_col, - mii_crs, - mii_rx_clk, - mii_rx_er, - mii_rx_dv, - mii_rxd, - mii_tx_clk, - mii_tx_en, - mii_txd, + output mdio_mdc, + inout mdio_mdio, + output mii_rst_n, + input mii_col, + input mii_crs, + input mii_rx_clk, + input mii_rx_er, + input mii_rx_dv, + input [ 3:0] mii_rxd, + input mii_tx_clk, + output mii_tx_en, + output [ 3:0] mii_txd, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_dq_io, - linear_flash_oen, - linear_flash_wen, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + inout [15:0] linear_flash_dq_io, + output linear_flash_oen, + output linear_flash_wen, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [16:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_sysref_p, - tx_sysref_n, - tx_sync_p, - tx_sync_n, - tx_data_p, - tx_data_n, + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync_p, + input tx_sync_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, - trig_p, - trig_n, + input trig_p, + input trig_n, - adc_fdb, - adc_fda, - dac_irq, - clkd_status, + inout adc_fdb, + inout adc_fda, + inout dac_irq, + inout [ 1:0] clkd_status, - adc_pd, - dac_txen, - dac_reset, - clkd_sync, + inout adc_pd, + inout dac_txen, + inout dac_reset, + inout clkd_sync, - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, - spi_clk, - spi_sdio, - spi_dir); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [ 2:0] ddr3_1_n; - output [ 1:0] ddr3_1_p; - output ddr3_reset_n; - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output ddr3_ras_n; - output ddr3_we_n; - output ddr3_ck_n; - output ddr3_ck_p; - output ddr3_cke; - output ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output ddr3_odt; - - output mdio_mdc; - inout mdio_mdio; - output mii_rst_n; - input mii_col; - input mii_crs; - input mii_rx_clk; - input mii_rx_er; - input mii_rx_dv; - input [ 3:0] mii_rxd; - input mii_tx_clk; - output mii_tx_en; - output [ 3:0] mii_txd; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - inout [15:0] linear_flash_dq_io; - output linear_flash_oen; - output linear_flash_wen; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [16:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - input tx_ref_clk_p; - input tx_ref_clk_n; - input tx_sysref_p; - input tx_sysref_n; - input tx_sync_p; - input tx_sync_n; - output [ 3:0] tx_data_p; - output [ 3:0] tx_data_n; - - input trig_p; - input trig_n; - - inout adc_fdb; - inout adc_fda; - inout dac_irq; - inout [ 1:0] clkd_status; - - inout adc_pd; - inout dac_txen; - inout dac_reset; - inout clkd_sync; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; - output spi_clk; - inout spi_sdio; - output spi_dir; + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); // internal signals diff --git a/projects/daq2/kcu105/system_top.v b/projects/daq2/kcu105/system_top.v index 46331eaa8..a567fb70d 100644 --- a/projects/daq2/kcu105/system_top.v +++ b/projects/daq2/kcu105/system_top.v @@ -39,159 +39,82 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr4_act_n, - ddr4_addr, - ddr4_ba, - ddr4_bg, - ddr4_ck_p, - ddr4_ck_n, - ddr4_cke, - ddr4_cs_n, - ddr4_dm_n, - ddr4_dq, - ddr4_dqs_p, - ddr4_dqs_n, - ddr4_odt, - ddr4_reset_n, + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, - mdio_mdc, - mdio_mdio, - phy_clk_p, - phy_clk_n, - phy_rst_n, - phy_rx_p, - phy_rx_n, - phy_tx_p, - phy_tx_n, + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, - fan_pwm, + output fan_pwm, - gpio_bd, + inout [16:0] gpio_bd, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_sysref_p, - tx_sysref_n, - tx_sync_p, - tx_sync_n, - tx_data_p, - tx_data_n, + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync_p, + input tx_sync_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, - trig_p, - trig_n, + input trig_p, + input trig_n, - adc_fdb, - adc_fda, - dac_irq, - clkd_status, + inout adc_fdb, + inout adc_fda, + inout dac_irq, + inout [ 1:0] clkd_status, - adc_pd, - dac_txen, - dac_reset, - clkd_sync, + inout adc_pd, + inout dac_txen, + inout dac_reset, + inout clkd_sync, - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, - spi_clk, - spi_sdio, - spi_dir); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output ddr4_act_n; - output [16:0] ddr4_addr; - output [ 1:0] ddr4_ba; - output [ 0:0] ddr4_bg; - output ddr4_ck_p; - output ddr4_ck_n; - output [ 0:0] ddr4_cke; - output [ 0:0] ddr4_cs_n; - inout [ 7:0] ddr4_dm_n; - inout [63:0] ddr4_dq; - inout [ 7:0] ddr4_dqs_p; - inout [ 7:0] ddr4_dqs_n; - output [ 0:0] ddr4_odt; - output ddr4_reset_n; - - output mdio_mdc; - inout mdio_mdio; - input phy_clk_p; - input phy_clk_n; - output phy_rst_n; - input phy_rx_p; - input phy_rx_n; - output phy_tx_p; - output phy_tx_n; - - output fan_pwm; - - inout [16:0] gpio_bd; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - input tx_ref_clk_p; - input tx_ref_clk_n; - input tx_sysref_p; - input tx_sysref_n; - input tx_sync_p; - input tx_sync_n; - output [ 3:0] tx_data_p; - output [ 3:0] tx_data_n; - - input trig_p; - input trig_n; - - inout adc_fdb; - inout adc_fda; - inout dac_irq; - inout [ 1:0] clkd_status; - - inout adc_pd; - inout dac_txen; - inout dac_reset; - inout clkd_sync; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; - output spi_clk; - inout spi_sdio; - output spi_dir; + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); // internal signals diff --git a/projects/daq2/vc707/system_top.v b/projects/daq2/vc707/system_top.v index ad633cc7f..7b50c98d1 100644 --- a/projects/daq2/vc707/system_top.v +++ b/projects/daq2/vc707/system_top.v @@ -39,181 +39,93 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_reset_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ras_n, - ddr3_we_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, + output ddr3_reset_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output ddr3_ras_n, + output ddr3_we_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, - sgmii_rxp, - sgmii_rxn, - sgmii_txp, - sgmii_txn, + input sgmii_rxp, + input sgmii_rxn, + output sgmii_txp, + output sgmii_txn, - phy_rstn, - mgt_clk_p, - mgt_clk_n, - mdio_mdc, - mdio_mdio, + output phy_rstn, + input mgt_clk_p, + input mgt_clk_n, + output mdio_mdc, + inout mdio_mdio, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_dq_io, - linear_flash_oen, - linear_flash_wen, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + inout [15:0] linear_flash_dq_io, + output linear_flash_oen, + output linear_flash_wen, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [20:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_sysref_p, - tx_sysref_n, - tx_sync_p, - tx_sync_n, - tx_data_p, - tx_data_n, + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync_p, + input tx_sync_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, - trig_p, - trig_n, + input trig_p, + input trig_n, - adc_fdb, - adc_fda, - dac_irq, - clkd_status, + inout adc_fdb, + inout adc_fda, + inout dac_irq, + inout [ 1:0] clkd_status, - adc_pd, - dac_txen, - dac_reset, - clkd_sync, + inout adc_pd, + inout dac_txen, + inout dac_reset, + inout clkd_sync, - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, - spi_clk, - spi_sdio, - spi_dir); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output ddr3_reset_n; - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output ddr3_ras_n; - output ddr3_we_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - - input sgmii_rxp; - input sgmii_rxn; - output sgmii_txp; - output sgmii_txn; - - output phy_rstn; - input mgt_clk_p; - input mgt_clk_n; - output mdio_mdc; - inout mdio_mdio; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - inout [15:0] linear_flash_dq_io; - output linear_flash_oen; - output linear_flash_wen; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [20:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - input tx_ref_clk_p; - input tx_ref_clk_n; - input tx_sysref_p; - input tx_sysref_n; - input tx_sync_p; - input tx_sync_n; - output [ 3:0] tx_data_p; - output [ 3:0] tx_data_n; - - input trig_p; - input trig_n; - - inout adc_fdb; - inout adc_fda; - inout dac_irq; - inout [ 1:0] clkd_status; - - inout adc_pd; - inout dac_txen; - inout dac_reset; - inout clkd_sync; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; - output spi_clk; - inout spi_sdio; - output spi_dir; + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); // internal signals diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v index e9f01032c..a9c2aa277 100644 --- a/projects/daq2/zc706/system_top.v +++ b/projects/daq2/zc706/system_top.v @@ -39,193 +39,99 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_sysref_p, - tx_sysref_n, - tx_sync_p, - tx_sync_n, - tx_data_p, - tx_data_n, + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync_p, + input tx_sync_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, - trig_p, - trig_n, + input trig_p, + input trig_n, - adc_fdb, - adc_fda, - dac_irq, - clkd_status, + inout adc_fdb, + inout adc_fda, + inout dac_irq, + inout [ 1:0] clkd_status, - adc_pd, - dac_txen, - dac_reset, - clkd_sync, + inout adc_pd, + inout dac_txen, + inout dac_reset, + inout clkd_sync, - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, - spi_clk, - spi_sdio, - spi_dir); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - input tx_ref_clk_p; - input tx_ref_clk_n; - input tx_sysref_p; - input tx_sysref_n; - input tx_sync_p; - input tx_sync_n; - output [ 3:0] tx_data_p; - output [ 3:0] tx_data_n; - - input trig_p; - input trig_n; - - inout adc_fdb; - inout adc_fda; - inout dac_irq; - inout [ 1:0] clkd_status; - - inout adc_pd; - inout dac_txen; - inout dac_reset; - inout clkd_sync; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; - output spi_clk; - inout spi_sdio; - output spi_dir; + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); // internal signals diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v index 488d43065..f653b7e90 100644 --- a/projects/daq3/a10gx/system_top.v +++ b/projects/daq3/a10gx/system_top.v @@ -41,145 +41,74 @@ module system_top ( // clock and resets - sys_clk, - sys_resetn, + input sys_clk, + input sys_resetn, // ddr3 - ddr3_clk_p, - ddr3_clk_n, - ddr3_a, - ddr3_ba, - ddr3_cke, - ddr3_cs_n, - ddr3_odt, - ddr3_reset_n, - ddr3_we_n, - ddr3_ras_n, - ddr3_cas_n, - ddr3_dqs_p, - ddr3_dqs_n, - ddr3_dq, - ddr3_dm, - ddr3_rzq, - ddr3_ref_clk, + output ddr3_clk_p, + output ddr3_clk_n, + output [ 14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_odt, + output ddr3_reset_n, + output ddr3_we_n, + output ddr3_ras_n, + output ddr3_cas_n, + inout [ 7:0] ddr3_dqs_p, + inout [ 7:0] ddr3_dqs_n, + inout [ 63:0] ddr3_dq, + output [ 7:0] ddr3_dm, + input ddr3_rzq, + input ddr3_ref_clk, // ethernet - eth_ref_clk, - eth_rxd, - eth_txd, - eth_mdc, - eth_mdio, - eth_resetn, - eth_intn, + input eth_ref_clk, + input eth_rxd, + output eth_txd, + output eth_mdc, + inout eth_mdio, + output eth_resetn, + input eth_intn, // board gpio - gpio_bd_i, - gpio_bd_o, + input [ 10:0] gpio_bd_i, + output [ 15:0] gpio_bd_o, // lane interface - rx_ref_clk, - rx_sysref, - rx_sync, - rx_data, - tx_ref_clk, - tx_sysref, - tx_sync, - tx_data, + input rx_ref_clk, + input rx_sysref, + output rx_sync, + input [ 3:0] rx_data, + input tx_ref_clk, + input tx_sysref, + input tx_sync, + output [ 3:0] tx_data, // gpio - trig, - adc_fdb, - adc_fda, - dac_irq, - clkd_status, - adc_pd, - dac_txen, - sysref, + input trig, + input adc_fdb, + input adc_fda, + input dac_irq, + input [ 1:0] clkd_status, + output adc_pd, + output dac_txen, + output sysref, // spi - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, - spi_clk, - spi_sdio, - spi_dir); - - // clock and resets - - input sys_clk; - input sys_resetn; - - // ddr3 - - output ddr3_clk_p; - output ddr3_clk_n; - output [ 14:0] ddr3_a; - output [ 2:0] ddr3_ba; - output ddr3_cke; - output ddr3_cs_n; - output ddr3_odt; - output ddr3_reset_n; - output ddr3_we_n; - output ddr3_ras_n; - output ddr3_cas_n; - inout [ 7:0] ddr3_dqs_p; - inout [ 7:0] ddr3_dqs_n; - inout [ 63:0] ddr3_dq; - output [ 7:0] ddr3_dm; - input ddr3_rzq; - input ddr3_ref_clk; - - // ethernet - - input eth_ref_clk; - input eth_rxd; - output eth_txd; - output eth_mdc; - inout eth_mdio; - output eth_resetn; - input eth_intn; - - // board gpio - - input [ 10:0] gpio_bd_i; - output [ 15:0] gpio_bd_o; - - // lane interface - - input rx_ref_clk; - input rx_sysref; - output rx_sync; - input [ 3:0] rx_data; - input tx_ref_clk; - input tx_sysref; - input tx_sync; - output [ 3:0] tx_data; - - // gpio - - input trig; - input adc_fdb; - input adc_fda; - input dac_irq; - input [ 1:0] clkd_status; - output adc_pd; - output dac_txen; - output sysref; - - // spi - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; - output spi_clk; - inout spi_sdio; - output spi_dir; + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); // internal signals diff --git a/projects/daq3/common/daq3_spi.v b/projects/daq3/common/daq3_spi.v index 77f6b2ac1..9a49c23e0 100644 --- a/projects/daq3/common/daq3_spi.v +++ b/projects/daq3/common/daq3_spi.v @@ -39,25 +39,13 @@ module daq3_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input [ 2:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio, - spi_dir); - - // 4 wire - - input [ 2:0] spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; - output spi_dir; + inout spi_sdio, + output spi_dir); // internal registers diff --git a/projects/daq3/kcu105/system_top.v b/projects/daq3/kcu105/system_top.v index 4396a35bf..73d823ffa 100644 --- a/projects/daq3/kcu105/system_top.v +++ b/projects/daq3/kcu105/system_top.v @@ -41,159 +41,82 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr4_act_n, - ddr4_addr, - ddr4_ba, - ddr4_bg, - ddr4_ck_p, - ddr4_ck_n, - ddr4_cke, - ddr4_cs_n, - ddr4_dm_n, - ddr4_dq, - ddr4_dqs_p, - ddr4_dqs_n, - ddr4_odt, - ddr4_reset_n, + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, - mdio_mdc, - mdio_mdio, - phy_clk_p, - phy_clk_n, - phy_rst_n, - phy_rx_p, - phy_rx_n, - phy_tx_p, - phy_tx_n, + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, - fan_pwm, + output fan_pwm, - gpio_bd, + inout [16:0] gpio_bd, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_sysref_p, - tx_sysref_n, - tx_sync_p, - tx_sync_n, - tx_data_p, - tx_data_n, + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync_p, + input tx_sync_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, - trig_p, - trig_n, + input trig_p, + input trig_n, - adc_fdb, - adc_fda, - dac_irq, - clkd_status, + inout adc_fdb, + inout adc_fda, + inout dac_irq, + inout [ 1:0] clkd_status, - adc_pd, - dac_txen, - sysref_p, - sysref_n, + inout adc_pd, + inout dac_txen, + output sysref_p, + output sysref_n, - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, - spi_clk, - spi_sdio, - spi_dir); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output ddr4_act_n; - output [16:0] ddr4_addr; - output [ 1:0] ddr4_ba; - output [ 0:0] ddr4_bg; - output ddr4_ck_p; - output ddr4_ck_n; - output [ 0:0] ddr4_cke; - output [ 0:0] ddr4_cs_n; - inout [ 7:0] ddr4_dm_n; - inout [63:0] ddr4_dq; - inout [ 7:0] ddr4_dqs_p; - inout [ 7:0] ddr4_dqs_n; - output [ 0:0] ddr4_odt; - output ddr4_reset_n; - - output mdio_mdc; - inout mdio_mdio; - input phy_clk_p; - input phy_clk_n; - output phy_rst_n; - input phy_rx_p; - input phy_rx_n; - output phy_tx_p; - output phy_tx_n; - - output fan_pwm; - - inout [16:0] gpio_bd; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - input tx_ref_clk_p; - input tx_ref_clk_n; - input tx_sysref_p; - input tx_sysref_n; - input tx_sync_p; - input tx_sync_n; - output [ 3:0] tx_data_p; - output [ 3:0] tx_data_n; - - input trig_p; - input trig_n; - - inout adc_fdb; - inout adc_fda; - inout dac_irq; - inout [ 1:0] clkd_status; - - inout adc_pd; - inout dac_txen; - output sysref_p; - output sysref_n; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; - output spi_clk; - inout spi_sdio; - output spi_dir; + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); // internal signals diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index 217a9ce2c..bbbc1903f 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -39,193 +39,99 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_sysref_p, - tx_sysref_n, - tx_sync_p, - tx_sync_n, - tx_data_p, - tx_data_n, + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync_p, + input tx_sync_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, - trig_p, - trig_n, + input trig_p, + input trig_n, - adc_fdb, - adc_fda, - dac_irq, - clkd_status, + inout adc_fdb, + inout adc_fda, + inout dac_irq, + inout [ 1:0] clkd_status, - adc_pd, - dac_txen, - sysref_p, - sysref_n, + inout adc_pd, + inout dac_txen, + output sysref_p, + output sysref_n, - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, - spi_clk, - spi_sdio, - spi_dir); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - input tx_ref_clk_p; - input tx_ref_clk_n; - input tx_sysref_p; - input tx_sysref_n; - input tx_sync_p; - input tx_sync_n; - output [ 3:0] tx_data_p; - output [ 3:0] tx_data_n; - - input trig_p; - input trig_n; - - inout adc_fdb; - inout adc_fda; - inout dac_irq; - inout [ 1:0] clkd_status; - - inout adc_pd; - inout dac_txen; - output sysref_p; - output sysref_n; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; - output spi_clk; - inout spi_sdio; - output spi_dir; + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); // internal signals diff --git a/projects/fmcadc2/common/fmcadc2_spi.v b/projects/fmcadc2/common/fmcadc2_spi.v index cb44724cd..3e7b6feb7 100644 --- a/projects/fmcadc2/common/fmcadc2_spi.v +++ b/projects/fmcadc2/common/fmcadc2_spi.v @@ -39,47 +39,22 @@ module fmcadc2_spi ( - spi_adf4355, - spi_adf4355_ce, + input spi_adf4355, + input spi_adf4355_ce, - spi_clk, - spi_csn, - spi_mosi, - spi_miso, + input spi_clk, + input [ 2:0] spi_csn, + input spi_mosi, + output spi_miso, - spi_adc_csn, - spi_adc_clk, - spi_adc_sdio, + output spi_adc_csn, + output spi_adc_clk, + inout spi_adc_sdio, - spi_adf4355_data_or_csn_0, - spi_adf4355_clk_or_csn_1, - spi_adf4355_le_or_clk, - spi_adf4355_ce_or_sdio); - - // select (adf4355 = 0x1), (normal = 0x0) - - input spi_adf4355; - input spi_adf4355_ce; - - // 4 wire - - input spi_clk; - input [ 2:0] spi_csn; - input spi_mosi; - output spi_miso; - - // adc interface (3 wire) - - output spi_adc_csn; - output spi_adc_clk; - inout spi_adc_sdio; - - // adf4355 or normal (AMP/EXT) - - output spi_adf4355_data_or_csn_0; - output spi_adf4355_clk_or_csn_1; - output spi_adf4355_le_or_clk; - inout spi_adf4355_ce_or_sdio; + output spi_adf4355_data_or_csn_0, + output spi_adf4355_clk_or_csn_1, + output spi_adf4355_le_or_clk, + inout spi_adf4355_ce_or_sdio); // internal registers diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v index be9a8bf87..00fa47460 100644 --- a/projects/fmcadc2/vc707/system_top.v +++ b/projects/fmcadc2/vc707/system_top.v @@ -39,147 +39,76 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_reset_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ras_n, - ddr3_we_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, + output ddr3_reset_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output ddr3_ras_n, + output ddr3_we_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, - sgmii_rxp, - sgmii_rxn, - sgmii_txp, - sgmii_txn, + input sgmii_rxp, + input sgmii_rxn, + output sgmii_txp, + output sgmii_txn, - phy_rstn, - mgt_clk_p, - mgt_clk_n, - mdio_mdc, - mdio_mdio, + output phy_rstn, + input mgt_clk_p, + input mgt_clk_n, + output mdio_mdc, + inout mdio_mdio, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_dq_io, - linear_flash_oen, - linear_flash_wen, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + inout [15:0] linear_flash_dq_io, + output linear_flash_oen, + output linear_flash_wen, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [20:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + output rx_sysref_p, + output rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 7:0] rx_data_p, + input [ 7:0] rx_data_n, - adc_irq, - adc_fd, + inout adc_irq, + inout adc_fd, - spi_adc_csn, - spi_adc_clk, - spi_adc_sdio, + output spi_adc_csn, + output spi_adc_clk, + inout spi_adc_sdio, - spi_adf4355_data_or_csn_0, - spi_adf4355_clk_or_csn_1, - spi_adf4355_le_or_clk, - spi_adf4355_ce_or_sdio); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output ddr3_reset_n; - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output ddr3_ras_n; - output ddr3_we_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - - input sgmii_rxp; - input sgmii_rxn; - output sgmii_txp; - output sgmii_txn; - - output phy_rstn; - input mgt_clk_p; - input mgt_clk_n; - output mdio_mdc; - inout mdio_mdio; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - inout [15:0] linear_flash_dq_io; - output linear_flash_oen; - output linear_flash_wen; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [20:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - output rx_sysref_p; - output rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 7:0] rx_data_p; - input [ 7:0] rx_data_n; - - inout adc_irq; - inout adc_fd; - - output spi_adc_csn; - output spi_adc_clk; - inout spi_adc_sdio; - - output spi_adf4355_data_or_csn_0; - output spi_adf4355_clk_or_csn_1; - output spi_adf4355_le_or_clk; - inout spi_adf4355_ce_or_sdio; + output spi_adf4355_data_or_csn_0, + output spi_adf4355_clk_or_csn_1, + output spi_adf4355_le_or_clk, + inout spi_adf4355_ce_or_sdio); // internal signals @@ -199,7 +128,6 @@ module system_top ( assign fan_pwm = 1'b1; assign iic_rstn = 1'b1; - // instantiations IBUFDS_GTE2 i_ibufds_rx_ref_clk ( diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v index 714fdd451..1a7406567 100644 --- a/projects/fmcadc2/zc706/system_top.v +++ b/projects/fmcadc2/zc706/system_top.v @@ -41,159 +41,82 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + output rx_sysref_p, + output rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 7:0] rx_data_p, + input [ 7:0] rx_data_n, - adc_irq, - adc_fd, + inout adc_irq, + inout adc_fd, - spi_adc_csn, - spi_adc_clk, - spi_adc_sdio, + output spi_adc_csn, + output spi_adc_clk, + inout spi_adc_sdio, - spi_adf4355_data_or_csn_0, - spi_adf4355_clk_or_csn_1, - spi_adf4355_le_or_clk, - spi_adf4355_ce_or_sdio); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - output rx_sysref_p; - output rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 7:0] rx_data_p; - input [ 7:0] rx_data_n; - - inout adc_irq; - inout adc_fd; - - output spi_adc_csn; - output spi_adc_clk; - inout spi_adc_sdio; - - output spi_adf4355_data_or_csn_0; - output spi_adf4355_clk_or_csn_1; - output spi_adf4355_le_or_clk; - inout spi_adf4355_ce_or_sdio; + output spi_adf4355_data_or_csn_0, + output spi_adf4355_clk_or_csn_1, + output spi_adf4355_le_or_clk, + inout spi_adf4355_ce_or_sdio); // internal signals diff --git a/projects/fmcadc4/common/fmcadc4_spi.v b/projects/fmcadc4/common/fmcadc4_spi.v index 1491d99f8..469f19258 100644 --- a/projects/fmcadc4/common/fmcadc4_spi.v +++ b/projects/fmcadc4/common/fmcadc4_spi.v @@ -39,23 +39,12 @@ module fmcadc4_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input [ 2:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio); - - // 4 wire - - input [ 2:0] spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; + inout spi_sdio); // internal registers diff --git a/projects/fmcadc4/zc706/system_top.v b/projects/fmcadc4/zc706/system_top.v index 2f89d49b9..04b128ae7 100644 --- a/projects/fmcadc4/zc706/system_top.v +++ b/projects/fmcadc4/zc706/system_top.v @@ -41,173 +41,89 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_0_p, - rx_sync_0_n, - rx_sync_1_p, - rx_sync_1_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_0_p, + output rx_sync_0_n, + output rx_sync_1_p, + output rx_sync_1_n, + input [ 7:0] rx_data_p, + input [ 7:0] rx_data_n, - ad9528_rstn, - ad9528_status, - ad9680_1_fda, - ad9680_1_fdb, - ad9680_2_fda, - ad9680_2_fdb, + inout ad9528_rstn, + inout ad9528_status, + inout ad9680_1_fda, + inout ad9680_1_fdb, + inout ad9680_2_fda, + inout ad9680_2_fdb, - ad9528_csn, - ada4961_1a_csn, - ada4961_1b_csn, - ad9680_1_csn, - ada4961_2a_csn, - ada4961_2b_csn, - ad9680_2_csn, - spi_clk, - spi_sdio); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_0_p; - output rx_sync_0_n; - output rx_sync_1_p; - output rx_sync_1_n; - input [ 7:0] rx_data_p; - input [ 7:0] rx_data_n; - - inout ad9528_rstn; - inout ad9528_status; - inout ad9680_1_fda; - inout ad9680_1_fdb; - inout ad9680_2_fda; - inout ad9680_2_fdb; - - output ad9528_csn; - output ada4961_1a_csn; - output ada4961_1b_csn; - output ad9680_1_csn; - output ada4961_2a_csn; - output ada4961_2b_csn; - output ad9680_2_csn; - output spi_clk; - inout spi_sdio; + output ad9528_csn, + output ada4961_1a_csn, + output ada4961_1b_csn, + output ad9680_1_csn, + output ada4961_2a_csn, + output ada4961_2b_csn, + output ad9680_2_csn, + output spi_clk, + inout spi_sdio); // internal signals diff --git a/projects/fmcadc5/common/fmcadc5_psync.v b/projects/fmcadc5/common/fmcadc5_psync.v index d4a7367fd..94a64a883 100644 --- a/projects/fmcadc5/common/fmcadc5_psync.v +++ b/projects/fmcadc5/common/fmcadc5_psync.v @@ -39,24 +39,15 @@ module fmcadc5_psync ( - up_rstn, - up_clk, + input up_rstn, + input up_clk, - psync_0, - psync_1); - - // 4 wire - - input up_rstn; - input up_clk; - output psync_0; - output psync_1; + output reg psync_0, + output reg psync_1); // internal registers reg [ 7:0] psync_count = 'd0; - reg psync_0 = 'd0; - reg psync_1 = 'd0; // ~602K diff --git a/projects/fmcadc5/common/fmcadc5_spi.v b/projects/fmcadc5/common/fmcadc5_spi.v index 575557c3b..92c634fee 100644 --- a/projects/fmcadc5/common/fmcadc5_spi.v +++ b/projects/fmcadc5/common/fmcadc5_spi.v @@ -39,27 +39,14 @@ module fmcadc5_spi ( - spi_csn_0, - spi_csn_1, - spi_clk, - spi_mosi, - spi_miso, + input spi_csn_0, + input spi_csn_1, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio, - spi_dirn); - - // 4 wire - - input spi_csn_0; - input spi_csn_1; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; - output spi_dirn; + inout spi_sdio, + output spi_dirn); // internal registers diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v b/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v index 2ce55a504..59e51ea76 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v @@ -41,14 +41,12 @@ module fmcjesdadc1_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio); - - // parameters + inout spi_sdio); localparam FMC27X_CPLD = 8'h00; localparam FMC27X_AD9517 = 8'h84; @@ -57,17 +55,6 @@ module fmcjesdadc1_spi ( localparam FMC27X_AD9129_0 = 8'h82; localparam FMC27X_AD9129_1 = 8'h83; - // 4-wire - - input spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3-wire - - inout spi_sdio; - // internal registers reg [ 7:0] spi_devid = 'd0; diff --git a/projects/fmcjesdadc1/kc705/system_top.v b/projects/fmcjesdadc1/kc705/system_top.v index 60fd19c76..ad2233c71 100644 --- a/projects/fmcjesdadc1/kc705/system_top.v +++ b/projects/fmcjesdadc1/kc705/system_top.v @@ -41,135 +41,70 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_1_n, - ddr3_1_p, - ddr3_reset_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ras_n, - ddr3_we_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, + output [ 2:0] ddr3_1_n, + output [ 1:0] ddr3_1_p, + output ddr3_reset_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output ddr3_ras_n, + output ddr3_we_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, - mdio_mdc, - mdio_mdio, - mii_rst_n, - mii_col, - mii_crs, - mii_rx_clk, - mii_rx_er, - mii_rx_dv, - mii_rxd, - mii_tx_clk, - mii_tx_en, - mii_txd, + output mdio_mdc, + inout mdio_mdio, + output mii_rst_n, + input mii_col, + input mii_crs, + input mii_rx_clk, + input mii_rx_er, + input mii_rx_dv, + input [ 3:0] mii_rxd, + input mii_tx_clk, + output mii_tx_en, + output [ 3:0] mii_txd, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_dq_io, - linear_flash_oen, - linear_flash_wen, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + inout [15:0] linear_flash_dq_io, + output linear_flash_oen, + output linear_flash_wen, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [16:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref, - rx_sync, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + output rx_sysref, + output rx_sync, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - spi_csn_0, - spi_clk, - spi_sdio); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [ 2:0] ddr3_1_n; - output [ 1:0] ddr3_1_p; - output ddr3_reset_n; - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output ddr3_ras_n; - output ddr3_we_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - - output mdio_mdc; - inout mdio_mdio; - output mii_rst_n; - input mii_col; - input mii_crs; - input mii_rx_clk; - input mii_rx_er; - input mii_rx_dv; - input [ 3:0] mii_rxd; - input mii_tx_clk; - output mii_tx_en; - output [ 3:0] mii_txd; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - inout [15:0] linear_flash_dq_io; - output linear_flash_oen; - output linear_flash_wen; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [16:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - output rx_sysref; - output rx_sync; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - output spi_csn_0; - output spi_clk; - inout spi_sdio; + output spi_csn_0, + output spi_clk, + inout spi_sdio); // internal signals diff --git a/projects/fmcjesdadc1/vc707/system_top.v b/projects/fmcjesdadc1/vc707/system_top.v index 5fabc10d3..62b527de9 100644 --- a/projects/fmcjesdadc1/vc707/system_top.v +++ b/projects/fmcjesdadc1/vc707/system_top.v @@ -41,127 +41,66 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - sgmii_rxp, - sgmii_rxn, - sgmii_txp, - sgmii_txn, + input sgmii_rxp, + input sgmii_rxn, + output sgmii_txp, + output sgmii_txn, - phy_rstn, - mgt_clk_p, - mgt_clk_n, - mdio_mdc, - mdio_mdio, + output phy_rstn, + input mgt_clk_p, + input mgt_clk_n, + output mdio_mdc, + inout mdio_mdio, - fan_pwm, + output fan_pwm, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_oen, - linear_flash_wen, - linear_flash_dq_io, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + output linear_flash_oen, + output linear_flash_wen, + inout [15:0] linear_flash_dq_io, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [20:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref, - rx_sync, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + output rx_sysref, + output rx_sync, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - spi_csn_0, - spi_clk, - spi_sdio); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - input sgmii_rxp; - input sgmii_rxn; - output sgmii_txp; - output sgmii_txn; - - output phy_rstn; - input mgt_clk_p; - input mgt_clk_n; - output mdio_mdc; - inout mdio_mdio; - - output fan_pwm; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - output linear_flash_oen; - output linear_flash_wen; - inout [15:0] linear_flash_dq_io; - - inout [ 6:0] gpio_lcd; - inout [20:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - output rx_sysref; - output rx_sync; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - output spi_csn_0; - output spi_clk; - inout spi_sdio; + output spi_csn_0, + output spi_clk, + inout spi_sdio); // internal signals diff --git a/projects/fmcjesdadc1/zc706/system_top.v b/projects/fmcjesdadc1/zc706/system_top.v index d41fc4b96..81779c6f3 100644 --- a/projects/fmcjesdadc1/zc706/system_top.v +++ b/projects/fmcjesdadc1/zc706/system_top.v @@ -41,99 +41,52 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref, - rx_sync, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + output rx_sysref, + output rx_sync, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - spi_csn, - spi_clk, - spi_sdio); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - output rx_sysref; - output rx_sync; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - output spi_csn; - output spi_clk; - inout spi_sdio; + output spi_csn, + output spi_clk, + inout spi_sdio); // internal signals diff --git a/projects/fmcomms2/a10gx/system_top.v b/projects/fmcomms2/a10gx/system_top.v index b326ff43a..061c050c4 100644 --- a/projects/fmcomms2/a10gx/system_top.v +++ b/projects/fmcomms2/a10gx/system_top.v @@ -41,129 +41,66 @@ module system_top ( // clock and resets - sys_clk, - sys_resetn, + input sys_clk, + input sys_resetn, // ddr3 - ddr3_clk_p, - ddr3_clk_n, - ddr3_a, - ddr3_ba, - ddr3_cke, - ddr3_cs_n, - ddr3_odt, - ddr3_reset_n, - ddr3_we_n, - ddr3_ras_n, - ddr3_cas_n, - ddr3_dqs_p, - ddr3_dqs_n, - ddr3_dq, - ddr3_dm, - ddr3_rzq, - ddr3_ref_clk, + output ddr3_clk_p, + output ddr3_clk_n, + output [ 14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_odt, + output ddr3_reset_n, + output ddr3_we_n, + output ddr3_ras_n, + output ddr3_cas_n, + inout [ 7:0] ddr3_dqs_p, + inout [ 7:0] ddr3_dqs_n, + inout [ 63:0] ddr3_dq, + output [ 7:0] ddr3_dm, + input ddr3_rzq, + input ddr3_ref_clk, // ethernet - eth_ref_clk, - eth_rxd, - eth_txd, - eth_mdc, - eth_mdio, - eth_resetn, - eth_intn, + input eth_ref_clk, + input eth_rxd, + output eth_txd, + output eth_mdc, + inout eth_mdio, + output eth_resetn, + input eth_intn, // board gpio - gpio_bd_i, - gpio_bd_o, + input [ 10:0] gpio_bd_i, + output [ 15:0] gpio_bd_o, // ad9361-interface - rx_clk_in, - rx_frame_in, - rx_data_in, - tx_clk_out, - tx_frame_out, - tx_data_out, + input rx_clk_in, + input rx_frame_in, + input [ 5:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [ 5:0] tx_data_out, - enable, - txnrx, + output enable, + output txnrx, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + output gpio_resetb, + output gpio_sync, + output gpio_en_agc, + output [ 3:0] gpio_ctl, + input [ 7:0] gpio_status, - spi_csn, - spi_clk, - spi_mosi, - spi_miso); - - - // clock and resets - - input sys_clk; - input sys_resetn; - - // ddr3 - - output ddr3_clk_p; - output ddr3_clk_n; - output [ 14:0] ddr3_a; - output [ 2:0] ddr3_ba; - output ddr3_cke; - output ddr3_cs_n; - output ddr3_odt; - output ddr3_reset_n; - output ddr3_we_n; - output ddr3_ras_n; - output ddr3_cas_n; - inout [ 7:0] ddr3_dqs_p; - inout [ 7:0] ddr3_dqs_n; - inout [ 63:0] ddr3_dq; - output [ 7:0] ddr3_dm; - input ddr3_rzq; - input ddr3_ref_clk; - - // ethernet - - input eth_ref_clk; - input eth_rxd; - output eth_txd; - output eth_mdc; - inout eth_mdio; - output eth_resetn; - input eth_intn; - - // board gpio - - input [ 10:0] gpio_bd_i; - output [ 15:0] gpio_bd_o; - - // ad9361-interface - - input rx_clk_in; - input rx_frame_in; - input [ 5:0] rx_data_in; - output tx_clk_out; - output tx_frame_out; - output [ 5:0] tx_data_out; - output enable; - output txnrx; - - output gpio_resetb; - output gpio_sync; - output gpio_en_agc; - output [ 3:0] gpio_ctl; - input [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); // internal signals @@ -245,6 +182,5 @@ module system_top ( endmodule - // *************************************************************************** // *************************************************************************** diff --git a/projects/fmcomms2/ac701/system_top.v b/projects/fmcomms2/ac701/system_top.v index f8e47eb8f..7c46f3223 100644 --- a/projects/fmcomms2/ac701/system_top.v +++ b/projects/fmcomms2/ac701/system_top.v @@ -41,146 +41,75 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - phy_reset_n, - phy_mdc, - phy_mdio, - phy_tx_clk, - phy_tx_ctrl, - phy_tx_data, - phy_rx_clk, - phy_rx_ctrl, - phy_rx_data, + output phy_reset_n, + output phy_mdc, + inout phy_mdio, + output phy_tx_clk, + output phy_tx_ctrl, + output [ 3:0] phy_tx_data, + input phy_rx_clk, + input phy_rx_ctrl, + input [ 3:0] phy_rx_data, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [12:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - txnrx, - enable, + output txnrx, + output enable, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn_0, - spi_clk, - spi_mosi, - spi_miso - ); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - output phy_reset_n; - output phy_mdc; - inout phy_mdio; - output phy_tx_clk; - output phy_tx_ctrl; - output [ 3:0] phy_tx_data; - input phy_rx_clk; - input phy_rx_ctrl; - input [ 3:0] phy_rx_data; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [12:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output txnrx; - output enable; - - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn_0; - output spi_clk; - output spi_mosi; - input spi_miso; + output spi_csn_0, + output spi_clk, + output spi_mosi, + input spi_miso ); // internal signals diff --git a/projects/fmcomms2/common/prcfg.v b/projects/fmcomms2/common/prcfg.v index 532ced00b..de0a21f24 100644 --- a/projects/fmcomms2/common/prcfg.v +++ b/projects/fmcomms2/common/prcfg.v @@ -39,135 +39,70 @@ module prcfg ( - clk, + input clk, // gpio - dac_gpio_input, - dac_gpio_output, - adc_gpio_input, - adc_gpio_output, + input [31:0] dac_gpio_input, + output [31:0] dac_gpio_output, + input [31:0] adc_gpio_input, + output [31:0] adc_gpio_output, // tx side - dma_dac_i0_enable, - dma_dac_i0_data, - dma_dac_i0_valid, - dma_dac_q0_enable, - dma_dac_q0_data, - dma_dac_q0_valid, - dma_dac_i1_enable, - dma_dac_i1_data, - dma_dac_i1_valid, - dma_dac_q1_enable, - dma_dac_q1_data, - dma_dac_q1_valid, + input dma_dac_i0_enable, + output [15:0] dma_dac_i0_data, + input dma_dac_i0_valid, + input dma_dac_q0_enable, + output [15:0] dma_dac_q0_data, + input dma_dac_q0_valid, + input dma_dac_i1_enable, + output [15:0] dma_dac_i1_data, + input dma_dac_i1_valid, + input dma_dac_q1_enable, + output [15:0] dma_dac_q1_data, + input dma_dac_q1_valid, - core_dac_i0_enable, - core_dac_i0_data, - core_dac_i0_valid, - core_dac_q0_enable, - core_dac_q0_data, - core_dac_q0_valid, - core_dac_i1_enable, - core_dac_i1_data, - core_dac_i1_valid, - core_dac_q1_enable, - core_dac_q1_data, - core_dac_q1_valid, + output core_dac_i0_enable, + input [15:0] core_dac_i0_data, + output core_dac_i0_valid, + output core_dac_q0_enable, + input [15:0] core_dac_q0_data, + output core_dac_q0_valid, + output core_dac_i1_enable, + input [15:0] core_dac_i1_data, + output core_dac_i1_valid, + output core_dac_q1_enable, + input [15:0] core_dac_q1_data, + output core_dac_q1_valid, // rx side - dma_adc_i0_enable, - dma_adc_i0_data, - dma_adc_i0_valid, - dma_adc_q0_enable, - dma_adc_q0_data, - dma_adc_q0_valid, - dma_adc_i1_enable, - dma_adc_i1_data, - dma_adc_i1_valid, - dma_adc_q1_enable, - dma_adc_q1_data, - dma_adc_q1_valid, + input dma_adc_i0_enable, + input [15:0] dma_adc_i0_data, + input dma_adc_i0_valid, + input dma_adc_q0_enable, + input [15:0] dma_adc_q0_data, + input dma_adc_q0_valid, + input dma_adc_i1_enable, + input [15:0] dma_adc_i1_data, + input dma_adc_i1_valid, + input dma_adc_q1_enable, + input [15:0] dma_adc_q1_data, + input dma_adc_q1_valid, - core_adc_i0_enable, - core_adc_i0_data, - core_adc_i0_valid, - core_adc_q0_enable, - core_adc_q0_data, - core_adc_q0_valid, - core_adc_i1_enable, - core_adc_i1_data, - core_adc_i1_valid, - core_adc_q1_enable, - core_adc_q1_data, - core_adc_q1_valid); - - input clk; - - // gpio - - input [31:0] adc_gpio_input; - output [31:0] adc_gpio_output; - input [31:0] dac_gpio_input; - output [31:0] dac_gpio_output; - - // tx side - - input dma_dac_i0_enable; - output [15:0] dma_dac_i0_data; - input dma_dac_i0_valid; - input dma_dac_q0_enable; - output [15:0] dma_dac_q0_data; - input dma_dac_q0_valid; - input dma_dac_i1_enable; - output [15:0] dma_dac_i1_data; - input dma_dac_i1_valid; - input dma_dac_q1_enable; - output [15:0] dma_dac_q1_data; - input dma_dac_q1_valid; - - output core_dac_i0_enable; - input [15:0] core_dac_i0_data; - output core_dac_i0_valid; - output core_dac_q0_enable; - input [15:0] core_dac_q0_data; - output core_dac_q0_valid; - output core_dac_i1_enable; - input [15:0] core_dac_i1_data; - output core_dac_i1_valid; - output core_dac_q1_enable; - input [15:0] core_dac_q1_data; - output core_dac_q1_valid; - - // rx side - - input dma_adc_i0_enable; - input [15:0] dma_adc_i0_data; - input dma_adc_i0_valid; - input dma_adc_q0_enable; - input [15:0] dma_adc_q0_data; - input dma_adc_q0_valid; - input dma_adc_i1_enable; - input [15:0] dma_adc_i1_data; - input dma_adc_i1_valid; - input dma_adc_q1_enable; - input [15:0] dma_adc_q1_data; - input dma_adc_q1_valid; - - output core_adc_i0_enable; - output [15:0] core_adc_i0_data; - output core_adc_i0_valid; - output core_adc_q0_enable; - output [15:0] core_adc_q0_data; - output core_adc_q0_valid; - output core_adc_i1_enable; - output [15:0] core_adc_i1_data; - output core_adc_i1_valid; - output core_adc_q1_enable; - output [15:0] core_adc_q1_data; - output core_adc_q1_valid; + output core_adc_i0_enable, + output [15:0] core_adc_i0_data, + output core_adc_i0_valid, + output core_adc_q0_enable, + output [15:0] core_adc_q0_data, + output core_adc_q0_valid, + output core_adc_i1_enable, + output [15:0] core_adc_i1_data, + output core_adc_i1_valid, + output core_adc_q1_enable, + output [15:0] core_adc_q1_data, + output core_adc_q1_valid); // fmcomms2 configuration diff --git a/projects/fmcomms2/kc705/system_top.v b/projects/fmcomms2/kc705/system_top.v index 0e8f942c8..3ce6fd873 100644 --- a/projects/fmcomms2/kc705/system_top.v +++ b/projects/fmcomms2/kc705/system_top.v @@ -41,169 +41,87 @@ module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_1_n, - ddr3_1_p, - ddr3_reset_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ras_n, - ddr3_we_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, + output [ 2:0] ddr3_1_n, + output [ 1:0] ddr3_1_p, + output ddr3_reset_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output ddr3_ras_n, + output ddr3_we_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, - mdio_mdc, - mdio_mdio, - mii_rst_n, - mii_col, - mii_crs, - mii_rx_clk, - mii_rx_er, - mii_rx_dv, - mii_rxd, - mii_tx_clk, - mii_tx_en, - mii_txd, + output mdio_mdc, + inout mdio_mdio, + output mii_rst_n, + input mii_col, + input mii_crs, + input mii_rx_clk, + input mii_rx_er, + input mii_rx_dv, + input [ 3:0] mii_rxd, + input mii_tx_clk, + output mii_tx_en, + output [ 3:0] mii_txd, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_dq_io, - linear_flash_oen, - linear_flash_wen, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + inout [15:0] linear_flash_dq_io, + output linear_flash_oen, + output linear_flash_wen, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [16:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - txnrx, - enable, + output txnrx, + output enable, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn_0, - spi_clk, - spi_mosi, - spi_miso); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [ 2:0] ddr3_1_n; - output [ 1:0] ddr3_1_p; - output ddr3_reset_n; - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output ddr3_ras_n; - output ddr3_we_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - - output mdio_mdc; - inout mdio_mdio; - output mii_rst_n; - input mii_col; - input mii_crs; - input mii_rx_clk; - input mii_rx_er; - input mii_rx_dv; - input [ 3:0] mii_rxd; - input mii_tx_clk; - output mii_tx_en; - output [ 3:0] mii_txd; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - inout [15:0] linear_flash_dq_io; - output linear_flash_oen; - output linear_flash_wen; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [16:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output txnrx; - output enable; - - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn_0; - output spi_clk; - output spi_mosi; - input spi_miso; + output spi_csn_0, + output spi_clk, + output spi_mosi, + input spi_miso); // internal signals diff --git a/projects/fmcomms2/mitx045/system_top.v b/projects/fmcomms2/mitx045/system_top.v index cafefbf18..a0bb8af30 100644 --- a/projects/fmcomms2/mitx045/system_top.v +++ b/projects/fmcomms2/mitx045/system_top.v @@ -41,143 +41,74 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [11:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - spdif, + output spdif, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - txnrx, - enable, + output txnrx, + output enable, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn, - spi_clk, - spi_mosi, - spi_miso); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [11:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output txnrx; - output enable; - - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); // internal signals diff --git a/projects/fmcomms2/vc707/system_top.v b/projects/fmcomms2/vc707/system_top.v index 6a56953db..98fb9625e 100644 --- a/projects/fmcomms2/vc707/system_top.v +++ b/projects/fmcomms2/vc707/system_top.v @@ -40,161 +40,83 @@ `timescale 1ns/100ps module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_oen, - linear_flash_wen, - linear_flash_dq_io, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + output linear_flash_oen, + output linear_flash_wen, + inout [15:0] linear_flash_dq_io, - sgmii_rxp, - sgmii_rxn, - sgmii_txp, - sgmii_txn, + input sgmii_rxp, + input sgmii_rxn, + output sgmii_txp, + output sgmii_txn, - phy_rstn, - mgt_clk_p, - mgt_clk_n, - mdio_mdc, - mdio_mdio, + output phy_rstn, + input mgt_clk_p, + input mgt_clk_n, + output mdio_mdc, + inout mdio_mdio, - fan_pwm, + output fan_pwm, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [20:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - txnrx, - enable, + output txnrx, + output enable, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn_0, - spi_clk, - spi_mosi, - spi_miso - ); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - input sgmii_rxp; - input sgmii_rxn; - output sgmii_txp; - output sgmii_txn; - - output phy_rstn; - input mgt_clk_p; - input mgt_clk_n; - output mdio_mdc; - inout mdio_mdio; - - output fan_pwm; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - output linear_flash_oen; - output linear_flash_wen; - inout [15:0] linear_flash_dq_io; - - inout [ 6:0] gpio_lcd; - inout [20:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output txnrx; - output enable; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn_0; - output spi_clk; - output spi_mosi; - input spi_miso; + output spi_csn_0, + output spi_clk, + output spi_mosi, + input spi_miso ); // internal signals diff --git a/projects/fmcomms2/zc702/system_top.v b/projects/fmcomms2/zc702/system_top.v index c82806b46..57b279928 100644 --- a/projects/fmcomms2/zc702/system_top.v +++ b/projects/fmcomms2/zc702/system_top.v @@ -41,145 +41,75 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [15:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - txnrx, - enable, + output txnrx, + output enable, - gpio_muxout_tx, - gpio_muxout_rx, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_muxout_tx, + inout gpio_muxout_rx, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, - spi_udc_csn_tx, - spi_udc_csn_rx, - spi_udc_sclk, - spi_udc_data); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [15:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output txnrx; - output enable; - - inout gpio_muxout_tx; - inout gpio_muxout_rx; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - output spi_udc_csn_tx; - output spi_udc_csn_rx; - output spi_udc_sclk; - output spi_udc_data; + output spi_udc_csn_tx, + output spi_udc_csn_rx, + output spi_udc_sclk, + output spi_udc_data); // internal signals diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v index 7f6b166b7..e3bf8046d 100644 --- a/projects/fmcomms2/zc706/system_top.v +++ b/projects/fmcomms2/zc706/system_top.v @@ -39,149 +39,77 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - enable, - txnrx, + output enable, + output txnrx, - tdd_sync, + inout tdd_sync, - gpio_muxout_tx, - gpio_muxout_rx, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_muxout_tx, + inout gpio_muxout_rx, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, - spi_udc_csn_tx, - spi_udc_csn_rx, - spi_udc_sclk, - spi_udc_data); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output enable; - output txnrx; - - inout tdd_sync; - - inout gpio_muxout_tx; - inout gpio_muxout_rx; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - output spi_udc_csn_tx; - output spi_udc_csn_rx; - output spi_udc_sclk; - output spi_udc_data; + output spi_udc_csn_tx, + output spi_udc_csn_rx, + output spi_udc_sclk, + output spi_udc_data); // internal signals diff --git a/projects/fmcomms2/zc706pr/system_top.v b/projects/fmcomms2/zc706pr/system_top.v index 8ebbb1671..d2c794723 100644 --- a/projects/fmcomms2/zc706pr/system_top.v +++ b/projects/fmcomms2/zc706pr/system_top.v @@ -39,149 +39,77 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - enable, - txnrx, + output enable, + output txnrx, - tdd_sync, + inout tdd_sync, - gpio_muxout_tx, - gpio_muxout_rx, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_muxout_tx, + inout gpio_muxout_rx, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, - spi_udc_csn_tx, - spi_udc_csn_rx, - spi_udc_sclk, - spi_udc_data); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output enable; - output txnrx; - - inout tdd_sync; - - inout gpio_muxout_tx; - inout gpio_muxout_rx; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - output spi_udc_csn_tx; - output spi_udc_csn_rx; - output spi_udc_sclk; - output spi_udc_data; + output spi_udc_csn_tx, + output spi_udc_csn_rx, + output spi_udc_sclk, + output spi_udc_data); // internal signals diff --git a/projects/fmcomms2/zed/system_top.v b/projects/fmcomms2/zed/system_top.v index 3e1824def..e3297ad46 100644 --- a/projects/fmcomms2/zed/system_top.v +++ b/projects/fmcomms2/zed/system_top.v @@ -41,165 +41,85 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - otg_vbusoc, + input otg_vbusoc, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - txnrx, - enable, + output txnrx, + output enable, - gpio_muxout_tx, - gpio_muxout_rx, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_muxout_tx, + inout gpio_muxout_rx, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, - spi_udc_csn_tx, - spi_udc_csn_rx, - spi_udc_sclk, - spi_udc_data); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - input otg_vbusoc; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output txnrx; - output enable; - - inout gpio_muxout_tx; - inout gpio_muxout_rx; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - output spi_udc_csn_tx; - output spi_udc_csn_rx; - output spi_udc_sclk; - output spi_udc_data; + output spi_udc_csn_tx, + output spi_udc_csn_rx, + output spi_udc_sclk, + output spi_udc_data); // internal signals diff --git a/projects/fmcomms5/zc702/system_top.v b/projects/fmcomms5/zc702/system_top.v index 5be51a548..29128e32b 100644 --- a/projects/fmcomms5/zc702/system_top.v +++ b/projects/fmcomms5/zc702/system_top.v @@ -41,200 +41,104 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [ 14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [ 31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [ 53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [ 15:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [ 15:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_clk_in_0_p, - rx_clk_in_0_n, - rx_frame_in_0_p, - rx_frame_in_0_n, - rx_data_in_0_p, - rx_data_in_0_n, - tx_clk_out_0_p, - tx_clk_out_0_n, - tx_frame_out_0_p, - tx_frame_out_0_n, - tx_data_out_0_p, - tx_data_out_0_n, - gpio_status_0, - gpio_ctl_0, - gpio_en_agc_0, - mcs_sync, - gpio_resetb_0, - enable_0, - txnrx_0, - gpio_debug_1_0, - gpio_debug_2_0, - gpio_calsw_1_0, - gpio_calsw_2_0, - gpio_ad5355_rfen, - gpio_ad5355_lock, + input rx_clk_in_0_p, + input rx_clk_in_0_n, + input rx_frame_in_0_p, + input rx_frame_in_0_n, + input [ 5:0] rx_data_in_0_p, + input [ 5:0] rx_data_in_0_n, + output tx_clk_out_0_p, + output tx_clk_out_0_n, + output tx_frame_out_0_p, + output tx_frame_out_0_n, + output [ 5:0] tx_data_out_0_p, + output [ 5:0] tx_data_out_0_n, + inout [ 7:0] gpio_status_0, + inout [ 3:0] gpio_ctl_0, + inout gpio_en_agc_0, + output reg mcs_sync, + inout gpio_resetb_0, + output enable_0, + output txnrx_0, + inout gpio_debug_1_0, + inout gpio_debug_2_0, + inout gpio_calsw_1_0, + inout gpio_calsw_2_0, + inout gpio_ad5355_rfen, + inout gpio_ad5355_lock, - rx_clk_in_1_p, - rx_clk_in_1_n, - rx_frame_in_1_p, - rx_frame_in_1_n, - rx_data_in_1_p, - rx_data_in_1_n, - tx_clk_out_1_p, - tx_clk_out_1_n, - tx_frame_out_1_p, - tx_frame_out_1_n, - tx_data_out_1_p, - tx_data_out_1_n, - gpio_status_1, - gpio_ctl_1, - gpio_en_agc_1, - gpio_resetb_1, - enable_1, - txnrx_1, - gpio_debug_3_1, - gpio_debug_4_1, - gpio_calsw_3_1, - gpio_calsw_4_1, + input rx_clk_in_1_p, + input rx_clk_in_1_n, + input rx_frame_in_1_p, + input rx_frame_in_1_n, + input [ 5:0] rx_data_in_1_p, + input [ 5:0] rx_data_in_1_n, + output tx_clk_out_1_p, + output tx_clk_out_1_n, + output tx_frame_out_1_p, + output tx_frame_out_1_n, + output [ 5:0] tx_data_out_1_p, + output [ 5:0] tx_data_out_1_n, + inout [ 7:0] gpio_status_1, + inout [ 3:0] gpio_ctl_1, + inout gpio_en_agc_1, + inout gpio_resetb_1, + output enable_1, + output txnrx_1, + inout gpio_debug_3_1, + inout gpio_debug_4_1, + inout gpio_calsw_3_1, + inout gpio_calsw_4_1, - spi_ad9361_0, - spi_ad9361_1, - spi_ad5355, - spi_clk, - spi_mosi, - spi_miso, + output spi_ad9361_0, + output spi_ad9361_1, + output spi_ad5355, + output spi_clk, + output spi_mosi, + input spi_miso, - ref_clk_p, - ref_clk_n); - - inout [ 14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [ 31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [ 53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [ 15:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [ 15:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input rx_clk_in_0_p; - input rx_clk_in_0_n; - input rx_frame_in_0_p; - input rx_frame_in_0_n; - input [ 5:0] rx_data_in_0_p; - input [ 5:0] rx_data_in_0_n; - output tx_clk_out_0_p; - output tx_clk_out_0_n; - output tx_frame_out_0_p; - output tx_frame_out_0_n; - output [ 5:0] tx_data_out_0_p; - output [ 5:0] tx_data_out_0_n; - inout [ 7:0] gpio_status_0; - inout [ 3:0] gpio_ctl_0; - inout gpio_en_agc_0; - output mcs_sync; - inout gpio_resetb_0; - output enable_0; - output txnrx_0; - inout gpio_debug_1_0; - inout gpio_debug_2_0; - inout gpio_calsw_1_0; - inout gpio_calsw_2_0; - inout gpio_ad5355_rfen; - inout gpio_ad5355_lock; - - input rx_clk_in_1_p; - input rx_clk_in_1_n; - input rx_frame_in_1_p; - input rx_frame_in_1_n; - input [ 5:0] rx_data_in_1_p; - input [ 5:0] rx_data_in_1_n; - output tx_clk_out_1_p; - output tx_clk_out_1_n; - output tx_frame_out_1_p; - output tx_frame_out_1_n; - output [ 5:0] tx_data_out_1_p; - output [ 5:0] tx_data_out_1_n; - inout [ 7:0] gpio_status_1; - inout [ 3:0] gpio_ctl_1; - inout gpio_en_agc_1; - inout gpio_resetb_1; - output enable_1; - output txnrx_1; - inout gpio_debug_3_1; - inout gpio_debug_4_1; - inout gpio_calsw_3_1; - inout gpio_calsw_4_1; - - output spi_ad9361_0; - output spi_ad9361_1; - output spi_ad5355; - output spi_clk; - output spi_mosi; - input spi_miso; - - input ref_clk_p; - input ref_clk_n; + input ref_clk_p, + input ref_clk_n); // internal registers reg [ 2:0] mcs_sync_m = 'd0; - reg mcs_sync = 'd0; // internal signals diff --git a/projects/fmcomms5/zc706/system_top.v b/projects/fmcomms5/zc706/system_top.v index a708788d5..27f927f69 100644 --- a/projects/fmcomms5/zc706/system_top.v +++ b/projects/fmcomms5/zc706/system_top.v @@ -41,200 +41,104 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [ 14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [ 31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [ 53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [ 14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [ 23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_clk_in_0_p, - rx_clk_in_0_n, - rx_frame_in_0_p, - rx_frame_in_0_n, - rx_data_in_0_p, - rx_data_in_0_n, - tx_clk_out_0_p, - tx_clk_out_0_n, - tx_frame_out_0_p, - tx_frame_out_0_n, - tx_data_out_0_p, - tx_data_out_0_n, - gpio_status_0, - gpio_ctl_0, - gpio_en_agc_0, - mcs_sync, - gpio_resetb_0, - enable_0, - txnrx_0, - gpio_debug_1_0, - gpio_debug_2_0, - gpio_calsw_1_0, - gpio_calsw_2_0, - gpio_ad5355_rfen, - gpio_ad5355_lock, + input rx_clk_in_0_p, + input rx_clk_in_0_n, + input rx_frame_in_0_p, + input rx_frame_in_0_n, + input [ 5:0] rx_data_in_0_p, + input [ 5:0] rx_data_in_0_n, + output tx_clk_out_0_p, + output tx_clk_out_0_n, + output tx_frame_out_0_p, + output tx_frame_out_0_n, + output [ 5:0] tx_data_out_0_p, + output [ 5:0] tx_data_out_0_n, + inout [ 7:0] gpio_status_0, + inout [ 3:0] gpio_ctl_0, + inout gpio_en_agc_0, + output reg mcs_sync, + inout gpio_resetb_0, + output enable_0, + output txnrx_0, + inout gpio_debug_1_0, + inout gpio_debug_2_0, + inout gpio_calsw_1_0, + inout gpio_calsw_2_0, + inout gpio_ad5355_rfen, + inout gpio_ad5355_lock, - rx_clk_in_1_p, - rx_clk_in_1_n, - rx_frame_in_1_p, - rx_frame_in_1_n, - rx_data_in_1_p, - rx_data_in_1_n, - tx_clk_out_1_p, - tx_clk_out_1_n, - tx_frame_out_1_p, - tx_frame_out_1_n, - tx_data_out_1_p, - tx_data_out_1_n, - gpio_status_1, - gpio_ctl_1, - gpio_en_agc_1, - gpio_resetb_1, - enable_1, - txnrx_1, - gpio_debug_3_1, - gpio_debug_4_1, - gpio_calsw_3_1, - gpio_calsw_4_1, + input rx_clk_in_1_p, + input rx_clk_in_1_n, + input rx_frame_in_1_p, + input rx_frame_in_1_n, + input [ 5:0] rx_data_in_1_p, + input [ 5:0] rx_data_in_1_n, + output tx_clk_out_1_p, + output tx_clk_out_1_n, + output tx_frame_out_1_p, + output tx_frame_out_1_n, + output [ 5:0] tx_data_out_1_p, + output [ 5:0] tx_data_out_1_n, + inout [ 7:0] gpio_status_1, + inout [ 3:0] gpio_ctl_1, + inout gpio_en_agc_1, + inout gpio_resetb_1, + output enable_1, + output txnrx_1, + inout gpio_debug_3_1, + inout gpio_debug_4_1, + inout gpio_calsw_3_1, + inout gpio_calsw_4_1, - spi_ad9361_0, - spi_ad9361_1, - spi_ad5355, - spi_clk, - spi_mosi, - spi_miso, + output spi_ad9361_0, + output spi_ad9361_1, + output spi_ad5355, + output spi_clk, + output spi_mosi, + input spi_miso, - ref_clk_p, - ref_clk_n); - - inout [ 14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [ 31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [ 53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [ 14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [ 23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input rx_clk_in_0_p; - input rx_clk_in_0_n; - input rx_frame_in_0_p; - input rx_frame_in_0_n; - input [ 5:0] rx_data_in_0_p; - input [ 5:0] rx_data_in_0_n; - output tx_clk_out_0_p; - output tx_clk_out_0_n; - output tx_frame_out_0_p; - output tx_frame_out_0_n; - output [ 5:0] tx_data_out_0_p; - output [ 5:0] tx_data_out_0_n; - inout [ 7:0] gpio_status_0; - inout [ 3:0] gpio_ctl_0; - inout gpio_en_agc_0; - output mcs_sync; - inout gpio_resetb_0; - output enable_0; - output txnrx_0; - inout gpio_debug_1_0; - inout gpio_debug_2_0; - inout gpio_calsw_1_0; - inout gpio_calsw_2_0; - inout gpio_ad5355_rfen; - inout gpio_ad5355_lock; - - input rx_clk_in_1_p; - input rx_clk_in_1_n; - input rx_frame_in_1_p; - input rx_frame_in_1_n; - input [ 5:0] rx_data_in_1_p; - input [ 5:0] rx_data_in_1_n; - output tx_clk_out_1_p; - output tx_clk_out_1_n; - output tx_frame_out_1_p; - output tx_frame_out_1_n; - output [ 5:0] tx_data_out_1_p; - output [ 5:0] tx_data_out_1_n; - inout [ 7:0] gpio_status_1; - inout [ 3:0] gpio_ctl_1; - inout gpio_en_agc_1; - inout gpio_resetb_1; - output enable_1; - output txnrx_1; - inout gpio_debug_3_1; - inout gpio_debug_4_1; - inout gpio_calsw_3_1; - inout gpio_calsw_4_1; - - output spi_ad9361_0; - output spi_ad9361_1; - output spi_ad5355; - output spi_clk; - output spi_mosi; - input spi_miso; - - input ref_clk_p; - input ref_clk_n; + input ref_clk_p, + input ref_clk_n); // internal registers reg [ 2:0] mcs_sync_m = 'd0; - reg mcs_sync = 'd0; // internal signals diff --git a/projects/fmcomms5/zcu102/system_top.v b/projects/fmcomms5/zcu102/system_top.v index 5c665f94e..3804e9f59 100644 --- a/projects/fmcomms5/zcu102/system_top.v +++ b/projects/fmcomms5/zcu102/system_top.v @@ -41,134 +41,71 @@ module system_top ( - gpio_bd_i, - gpio_bd_o, + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, - rx_clk_in_0_p, - rx_clk_in_0_n, - rx_frame_in_0_p, - rx_frame_in_0_n, - rx_data_in_0_p, - rx_data_in_0_n, - tx_clk_out_0_p, - tx_clk_out_0_n, - tx_frame_out_0_p, - tx_frame_out_0_n, - tx_data_out_0_p, - tx_data_out_0_n, - gpio_status_0, - gpio_ctl_0, - gpio_en_agc_0, - mcs_sync, - gpio_resetb_0, - enable_0, - txnrx_0, - gpio_debug_1_0, - gpio_debug_2_0, - gpio_calsw_1_0, - gpio_calsw_2_0, - gpio_ad5355_rfen, - gpio_ad5355_lock, + input rx_clk_in_0_p, + input rx_clk_in_0_n, + input rx_frame_in_0_p, + input rx_frame_in_0_n, + input [ 5:0] rx_data_in_0_p, + input [ 5:0] rx_data_in_0_n, + output tx_clk_out_0_p, + output tx_clk_out_0_n, + output tx_frame_out_0_p, + output tx_frame_out_0_n, + output [ 5:0] tx_data_out_0_p, + output [ 5:0] tx_data_out_0_n, + input [ 7:0] gpio_status_0, + output [ 3:0] gpio_ctl_0, + output gpio_en_agc_0, + output reg mcs_sync, + output gpio_resetb_0, + output enable_0, + output txnrx_0, + output gpio_debug_1_0, + output gpio_debug_2_0, + output gpio_calsw_1_0, + output gpio_calsw_2_0, + output gpio_ad5355_rfen, + input gpio_ad5355_lock, - rx_clk_in_1_p, - rx_clk_in_1_n, - rx_frame_in_1_p, - rx_frame_in_1_n, - rx_data_in_1_p, - rx_data_in_1_n, - tx_clk_out_1_p, - tx_clk_out_1_n, - tx_frame_out_1_p, - tx_frame_out_1_n, - tx_data_out_1_p, - tx_data_out_1_n, - gpio_status_1, - gpio_ctl_1, - gpio_en_agc_1, - gpio_resetb_1, - enable_1, - txnrx_1, - gpio_debug_3_1, - gpio_debug_4_1, - gpio_calsw_3_1, - gpio_calsw_4_1, + input rx_clk_in_1_p, + input rx_clk_in_1_n, + input rx_frame_in_1_p, + input rx_frame_in_1_n, + input [ 5:0] rx_data_in_1_p, + input [ 5:0] rx_data_in_1_n, + output tx_clk_out_1_p, + output tx_clk_out_1_n, + output tx_frame_out_1_p, + output tx_frame_out_1_n, + output [ 5:0] tx_data_out_1_p, + output [ 5:0] tx_data_out_1_n, + input [ 7:0] gpio_status_1, + output [ 3:0] gpio_ctl_1, + output gpio_en_agc_1, + output gpio_resetb_1, + output enable_1, + output txnrx_1, + output gpio_debug_3_1, + output gpio_debug_4_1, + output gpio_calsw_3_1, + output gpio_calsw_4_1, - spi_ad9361_0, - spi_ad9361_1, - spi_ad5355, - spi_clk, - spi_mosi, - spi_miso, + output spi_ad9361_0, + output spi_ad9361_1, + output spi_ad5355, + output spi_clk, + output spi_mosi, + input spi_miso, - ref_clk_p, - ref_clk_n); - - input [12:0] gpio_bd_i; - output [ 7:0] gpio_bd_o; - - input rx_clk_in_0_p; - input rx_clk_in_0_n; - input rx_frame_in_0_p; - input rx_frame_in_0_n; - input [ 5:0] rx_data_in_0_p; - input [ 5:0] rx_data_in_0_n; - output tx_clk_out_0_p; - output tx_clk_out_0_n; - output tx_frame_out_0_p; - output tx_frame_out_0_n; - output [ 5:0] tx_data_out_0_p; - output [ 5:0] tx_data_out_0_n; - input [ 7:0] gpio_status_0; - output [ 3:0] gpio_ctl_0; - output gpio_en_agc_0; - output mcs_sync; - output gpio_resetb_0; - output enable_0; - output txnrx_0; - output gpio_debug_1_0; - output gpio_debug_2_0; - output gpio_calsw_1_0; - output gpio_calsw_2_0; - output gpio_ad5355_rfen; - input gpio_ad5355_lock; - - input rx_clk_in_1_p; - input rx_clk_in_1_n; - input rx_frame_in_1_p; - input rx_frame_in_1_n; - input [ 5:0] rx_data_in_1_p; - input [ 5:0] rx_data_in_1_n; - output tx_clk_out_1_p; - output tx_clk_out_1_n; - output tx_frame_out_1_p; - output tx_frame_out_1_n; - output [ 5:0] tx_data_out_1_p; - output [ 5:0] tx_data_out_1_n; - input [ 7:0] gpio_status_1; - output [ 3:0] gpio_ctl_1; - output gpio_en_agc_1; - output gpio_resetb_1; - output enable_1; - output txnrx_1; - output gpio_debug_3_1; - output gpio_debug_4_1; - output gpio_calsw_3_1; - output gpio_calsw_4_1; - - output spi_ad9361_0; - output spi_ad9361_1; - output spi_ad5355; - output spi_clk; - output spi_mosi; - input spi_miso; - - input ref_clk_p; - input ref_clk_n; + input ref_clk_p, + input ref_clk_n); // internal registers reg [ 2:0] mcs_sync_m = 'd0; - reg mcs_sync = 'd0; // internal signals diff --git a/projects/fmcomms7/common/fmcomms7_spi.v b/projects/fmcomms7/common/fmcomms7_spi.v index 56a5fd557..7fac1897a 100644 --- a/projects/fmcomms7/common/fmcomms7_spi.v +++ b/projects/fmcomms7/common/fmcomms7_spi.v @@ -39,25 +39,13 @@ module fmcomms7_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input [ 2:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_sdio, - spi_dir); - - // 4 wire - - input [ 2:0] spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; - output spi_dir; + inout spi_sdio, + output spi_dir); // internal registers diff --git a/projects/fmcomms7/zc706/system_top.v b/projects/fmcomms7/zc706/system_top.v index 2bd1e4b40..ceb256cf7 100644 --- a/projects/fmcomms7/zc706/system_top.v +++ b/projects/fmcomms7/zc706/system_top.v @@ -41,239 +41,122 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [ 14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [ 31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [ 53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [ 14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [ 23:0] hdmi_data, - spdif, + output spdif, - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [ 13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [ 63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_sysref_p, - tx_sysref_n, - tx_sync0_p, - tx_sync0_n, - tx_sync1_p, - tx_sync1_n, - tx_data_p, - tx_data_n, + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync0_p, + input tx_sync0_n, + input tx_sync1_p, + input tx_sync1_n, + output [ 7:0] tx_data_p, + output [ 7:0] tx_data_n, - trig_p, - trig_n, + input trig_p, + input trig_n, - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, - spi_clk, - spi_sdio, - spi_dir, + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir, - spi2_csn_adf4355_1, - spi2_csn_adf4355_2, - spi2_csn_hmc1044_1, - spi2_csn_hmc1044_2, - spi2_csn_hmc1044_3, - spi2_csn_adl5240_1, - spi2_csn_adl5240_2, - spi2_csn_hmc271_1, - spi2_csn_hmc271_2, - spi2_clk, - spi2_sdo, - spi2_sdi_hmc271_1, - spi2_sdi_hmc271_2, + output spi2_csn_adf4355_1, + output spi2_csn_adf4355_2, + output spi2_csn_hmc1044_1, + output spi2_csn_hmc1044_2, + output spi2_csn_hmc1044_3, + output spi2_csn_adl5240_1, + output spi2_csn_adl5240_2, + output spi2_csn_hmc271_1, + output spi2_csn_hmc271_2, + output spi2_clk, + output spi2_sdo, + input spi2_sdi_hmc271_1, + input spi2_sdi_hmc271_2, - clk_gpio, - adc_fda, - adc_fdb, - dac_irq, - adf4355_1_ld, - adf4355_2_ld, - xo_en, - clk_sync, - adf4355_2_pd, - dac_txen0, - dac_txen1, - hmc271_1_reset, - hmc271_2_reset, - hmc349_sel, - hmc922_a, - hmc922_b); - - inout [ 14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [ 31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [ 53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [ 14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [ 23:0] hdmi_data; - - output spdif; - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - output [ 13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [ 63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; - - input tx_ref_clk_p; - input tx_ref_clk_n; - input tx_sysref_p; - input tx_sysref_n; - input tx_sync0_p; - input tx_sync0_n; - input tx_sync1_p; - input tx_sync1_n; - output [ 7:0] tx_data_p; - output [ 7:0] tx_data_n; - - input trig_p; - input trig_n; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; - output spi_clk; - inout spi_sdio; - output spi_dir; - - output spi2_csn_adf4355_1; - output spi2_csn_adf4355_2; - output spi2_csn_hmc1044_1; - output spi2_csn_hmc1044_2; - output spi2_csn_hmc1044_3; - output spi2_csn_adl5240_1; - output spi2_csn_adl5240_2; - output spi2_csn_hmc271_1; - output spi2_csn_hmc271_2; - output spi2_clk; - output spi2_sdo; - input spi2_sdi_hmc271_1; - input spi2_sdi_hmc271_2; - - inout [ 3:0] clk_gpio; - inout adc_fda; - inout adc_fdb; - inout dac_irq; - inout adf4355_1_ld; - inout adf4355_2_ld; - inout xo_en; - inout clk_sync; - inout adf4355_2_pd; - inout dac_txen0; - inout dac_txen1; - inout hmc271_1_reset; - inout hmc271_2_reset; - inout hmc349_sel; - inout hmc922_a; - inout hmc922_b; + inout [ 3:0] clk_gpio, + inout adc_fda, + inout adc_fdb, + inout dac_irq, + inout adf4355_1_ld, + inout adf4355_2_ld, + inout xo_en, + inout clk_sync, + inout adf4355_2_pd, + inout dac_txen0, + inout dac_txen1, + inout hmc271_1_reset, + inout hmc271_2_reset, + inout hmc349_sel, + inout hmc922_a, + inout hmc922_b); // internal registers diff --git a/projects/imageon/zc706/system_top.v b/projects/imageon/zc706/system_top.v index 6d3b3318e..40c28ae7e 100644 --- a/projects/imageon/zc706/system_top.v +++ b/projects/imageon/zc706/system_top.v @@ -39,87 +39,46 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - hdmi_rx_clk, - hdmi_rx_data, - hdmi_rx_int, - hdmi_rx_spdif, + input hdmi_rx_clk, + input [15:0] hdmi_rx_data, + inout hdmi_rx_int, + input hdmi_rx_spdif, - hdmi_tx_clk, - hdmi_tx_data, - hdmi_tx_spdif, + output hdmi_tx_clk, + output [15:0] hdmi_tx_data, + output hdmi_tx_spdif, - hdmi_iic_scl, - hdmi_iic_sda, - hdmi_iic_rstn); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - inout iic_scl; - inout iic_sda; - - input hdmi_rx_clk; - input [15:0] hdmi_rx_data; - inout hdmi_rx_int; - input hdmi_rx_spdif; - - output hdmi_tx_clk; - output [15:0] hdmi_tx_data; - output hdmi_tx_spdif; - - inout hdmi_iic_rstn; - inout hdmi_iic_scl; - inout hdmi_iic_sda; + inout hdmi_iic_scl, + inout hdmi_iic_sda, + inout hdmi_iic_rstn); // internal signals diff --git a/projects/imageon/zed/system_top.v b/projects/imageon/zed/system_top.v index 79a80762d..718f0c467 100644 --- a/projects/imageon/zed/system_top.v +++ b/projects/imageon/zed/system_top.v @@ -41,108 +41,56 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - hdmi_rx_clk, - hdmi_rx_data, - hdmi_rx_int, - hdmi_rx_spdif, + input hdmi_rx_clk, + input [15:0] hdmi_rx_data, + inout hdmi_rx_int, + input hdmi_rx_spdif, - hdmi_tx_clk, - hdmi_tx_data, - hdmi_tx_spdif, + output hdmi_tx_clk, + output [15:0] hdmi_tx_data, + output hdmi_tx_spdif, - hdmi_iic_scl, - hdmi_iic_sda, - hdmi_iic_rstn, + inout hdmi_iic_scl, + inout hdmi_iic_sda, + inout hdmi_iic_rstn, - otg_vbusoc); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - input hdmi_rx_clk; - input [15:0] hdmi_rx_data; - inout hdmi_rx_int; - input hdmi_rx_spdif; - - output hdmi_tx_clk; - output [15:0] hdmi_tx_data; - output hdmi_tx_spdif; - - inout hdmi_iic_rstn; - inout hdmi_iic_scl; - inout hdmi_iic_sda; - - input otg_vbusoc; + input otg_vbusoc); // internal signals diff --git a/projects/motcon2_fmc/zed/system_top.v b/projects/motcon2_fmc/zed/system_top.v index 348b3deb8..1c60064a9 100644 --- a/projects/motcon2_fmc/zed/system_top.v +++ b/projects/motcon2_fmc/zed/system_top.v @@ -41,226 +41,117 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - eth1_rgmii_rd, - eth1_rgmii_rx_ctl, - eth1_rgmii_rxc, - eth1_rgmii_td, - eth1_rgmii_tx_ctl, - eth1_rgmii_txc, + input [3:0] eth1_rgmii_rd, + input eth1_rgmii_rx_ctl, + input eth1_rgmii_rxc, + output [3:0] eth1_rgmii_td, + output eth1_rgmii_tx_ctl, + output eth1_rgmii_txc, - eth2_rgmii_rd, - eth2_rgmii_rx_ctl, - eth2_rgmii_rxc, - eth2_rgmii_td, - eth2_rgmii_tx_ctl, - eth2_rgmii_txc, + input [3:0] eth2_rgmii_rd, + input eth2_rgmii_rx_ctl, + input eth2_rgmii_rxc, + output [3:0] eth2_rgmii_td, + output eth2_rgmii_tx_ctl, + output eth2_rgmii_txc, - eth_mdio_p, - eth_mdio_mdc, - eth_phy_rst_n, + inout eth_mdio_p, + output eth_mdio_mdc, + output eth_phy_rst_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [31:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, - position_m1_i, - position_m2_i, - adc_clk_o, - adc_m1_ia_dat_i, - adc_m1_ib_dat_i, - adc_m1_vbus_dat_i, - fmc_m1_en_o, - fmc_m2_en_o, - adc_m2_ia_dat_i, - adc_m2_ib_dat_i, - adc_m2_vbus_dat_i, - pwm_m1_ah_o, - pwm_m1_al_o, - pwm_m1_bh_o, - pwm_m1_bl_o, - pwm_m1_ch_o, - pwm_m1_cl_o, - pwm_m1_dh_o, - pwm_m1_dl_o, - pwm_m2_ah_o, - pwm_m2_al_o, - pwm_m2_bh_o, - pwm_m2_bl_o, - pwm_m2_ch_o, - pwm_m2_cl_o, - pwm_m2_dh_o, - pwm_m2_dl_o, - vt_enable, - vauxn0, - vauxn8, - vauxp0, - vauxp8, + input [2:0] position_m1_i, + input [2:0] position_m2_i, + output adc_clk_o, + input adc_m1_ia_dat_i, + input adc_m1_ib_dat_i, + input adc_m1_vbus_dat_i, + output fmc_m1_en_o, + output fmc_m2_en_o, + input adc_m2_ia_dat_i, + input adc_m2_ib_dat_i, + input adc_m2_vbus_dat_i, + output pwm_m1_ah_o, + output pwm_m1_al_o, + output pwm_m1_bh_o, + output pwm_m1_bl_o, + output pwm_m1_ch_o, + output pwm_m1_cl_o, + output pwm_m1_dh_o, + output pwm_m1_dl_o, + output pwm_m2_ah_o, + output pwm_m2_al_o, + output pwm_m2_bh_o, + output pwm_m2_bl_o, + output pwm_m2_ch_o, + output pwm_m2_cl_o, + output pwm_m2_dh_o, + output pwm_m2_dl_o, + output vt_enable, + input vauxn0, + input vauxn8, + input vauxp0, + input vauxp8, /* muxaddr_out,*/ - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - spdif, + output spdif, - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, - iic_ee2_scl_io, - iic_ee2_sda_io, + inout iic_ee2_scl_io, + inout iic_ee2_sda_io, - fmc_spi1_sel1_rdc, - fmc_spi1_miso, - fmc_spi1_mosi, - fmc_spi1_sck, - fmc_sample_n, - gpo, - gpi, + output fmc_spi1_sel1_rdc, + input fmc_spi1_miso, + output fmc_spi1_mosi, + output fmc_spi1_sck, + output fmc_sample_n, + output [ 3:0] gpo, + input [ 1:0] gpi, - otg_vbusoc); + input otg_vbusoc); - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - input [3:0] eth1_rgmii_rd; - input eth1_rgmii_rx_ctl; - input eth1_rgmii_rxc; - output [3:0] eth1_rgmii_td; - output eth1_rgmii_tx_ctl; - output eth1_rgmii_txc; - - input [3:0] eth2_rgmii_rd; - input eth2_rgmii_rx_ctl; - input eth2_rgmii_rxc; - output [3:0] eth2_rgmii_td; - output eth2_rgmii_tx_ctl; - output eth2_rgmii_txc; - - inout eth_mdio_p; - output eth_mdio_mdc; - output eth_phy_rst_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - input [2:0] position_m1_i; - input [2:0] position_m2_i; - output adc_clk_o; - output fmc_m1_en_o; - input adc_m1_ia_dat_i; - input adc_m1_ib_dat_i; - input adc_m1_vbus_dat_i; - output fmc_m2_en_o; - input adc_m2_ia_dat_i; - input adc_m2_ib_dat_i; - input adc_m2_vbus_dat_i; - output pwm_m1_ah_o; - output pwm_m1_al_o; - output pwm_m1_bh_o; - output pwm_m1_bl_o; - output pwm_m1_ch_o; - output pwm_m1_cl_o; - output pwm_m1_dh_o; - output pwm_m1_dl_o; - output pwm_m2_ah_o; - output pwm_m2_al_o; - output pwm_m2_bh_o; - output pwm_m2_bl_o; - output pwm_m2_ch_o; - output pwm_m2_cl_o; - output pwm_m2_dh_o; - output pwm_m2_dl_o; - - output vt_enable; - - input vauxn0; - input vauxn8; - input vauxp0; - input vauxp8; /* output [ 3:0] muxaddr_out;*/ - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - inout iic_ee2_scl_io; - inout iic_ee2_sda_io; - - output fmc_spi1_sel1_rdc; - input fmc_spi1_miso; - output fmc_spi1_mosi; - output fmc_spi1_sck; - output fmc_sample_n; - output [ 3:0] gpo; - input [ 1:0] gpi; - - input otg_vbusoc; - // internal signals wire [63:0] gpio_i; @@ -277,7 +168,6 @@ module system_top ( wire eth_mdio_i; wire eth_mdio_t; - // assignments assign fmc_sample_n = gpio_o[32]; diff --git a/projects/usdrx1/common/usdrx1_spi.v b/projects/usdrx1/common/usdrx1_spi.v index 4c49e975d..18cac265b 100644 --- a/projects/usdrx1/common/usdrx1_spi.v +++ b/projects/usdrx1/common/usdrx1_spi.v @@ -39,27 +39,14 @@ module usdrx1_spi ( - spi_afe_csn, - spi_clk_csn, - spi_clk, - spi_mosi, - spi_miso, + input [ 3:0] spi_afe_csn, + input spi_clk_csn, + input spi_clk, + input spi_mosi, + output spi_miso, - spi_afe_sdio, - spi_clk_sdio); - - // 4 wire - - input [ 3:0] spi_afe_csn; - input spi_clk_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_afe_sdio; - inout spi_clk_sdio; + inout spi_afe_sdio, + inout spi_clk_sdio); // internal registers diff --git a/projects/usdrx1/cpld/usdrx1_cpld.v b/projects/usdrx1/cpld/usdrx1_cpld.v index c3a13923f..beb365776 100644 --- a/projects/usdrx1/cpld/usdrx1_cpld.v +++ b/projects/usdrx1/cpld/usdrx1_cpld.v @@ -42,14 +42,14 @@ module usdrx1_cpld ( // Bank 1.8 V - fmc_dac_db, - fmc_dac_sleep, - fmc_clkd_spi_sclk, - fmc_clkd_spi_csb, - fmc_clkd_spi_sdio, + input [13:0] fmc_dac_db, + input fmc_dac_sleep, + input fmc_clkd_spi_sclk, + input fmc_clkd_spi_csb, + inout fmc_clkd_spi_sdio, - fmc_clkd_syncn, - fmc_clkd_resetn, + input fmc_clkd_syncn, + input fmc_clkd_resetn, //fmc_clkd_status, //tbd1 @@ -57,42 +57,15 @@ module usdrx1_cpld ( //tbd3 // Bank 3.3 V - dac_db, - dac_sleep, + output [13:0] dac_db, + output dac_sleep, - clkd_spi_sclk, - clkd_spi_csb, - clkd_spi_sdio, + output clkd_spi_sclk, + output clkd_spi_csb, + inout clkd_spi_sdio, //clkd_status, - clkd_syncn, - clkd_resetn -); - -// Bank 1.8 V - input [13:0] fmc_dac_db; - input fmc_dac_sleep; - input fmc_clkd_spi_sclk; - input fmc_clkd_spi_csb; - inout fmc_clkd_spi_sdio; - - input fmc_clkd_syncn; - input fmc_clkd_resetn; - //output fmc_clkd_status; - - //tbd1; - //tbd2; - //tbd3; - - // Bank 3.3 V - output [13:0] dac_db; - output dac_sleep; - - output clkd_spi_sclk; - output clkd_spi_csb; - inout clkd_spi_sdio; - //input clkd_status; - output clkd_syncn; - output clkd_resetn; + output clkd_syncn, + output clkd_resetn); reg [15:0] cnt ; reg fpga_to_clkd ; // 1 if fpga sends data to ad9517, 0 if fpga reads data from ad9517 diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index 334e6b354..73d4a4eb1 100644 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -41,201 +41,103 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + input rx_ref_clk_p, + input rx_ref_clk_n, + output rx_sysref_p, + output rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 7:0] rx_data_p, + input [ 7:0] rx_data_n, - spi_fout_enb_clk, - spi_fout_enb_mlo, - spi_fout_enb_rst, - spi_fout_enb_sync, - spi_fout_enb_sysref, - spi_fout_enb_trig, - spi_fout_clk, - spi_fout_sdio, - spi_afe_csn, - spi_afe_clk, - spi_afe_sdio, - spi_clk_csn, - spi_clk_clk, - spi_clk_sdio, + output spi_fout_enb_clk, + output spi_fout_enb_mlo, + output spi_fout_enb_rst, + output spi_fout_enb_sync, + output spi_fout_enb_sysref, + output spi_fout_enb_trig, + output spi_fout_clk, + output spi_fout_sdio, + output [ 3:0] spi_afe_csn, + output spi_afe_clk, + inout spi_afe_sdio, + output spi_clk_csn, + output spi_clk_clk, + inout spi_clk_sdio, - afe_rst_p, - afe_rst_n, - afe_trig_p, - afe_trig_n, + output afe_rst_p, + output afe_rst_n, + output afe_trig_p, + output afe_trig_n, - dac_sleep, - dac_data, - afe_pdn, - afe_stby, - clk_resetn, - clk_syncn, - clk_status, - amp_disbn, - prc_sck, - prc_cnv, - prc_sdo_i, - prc_sdo_q); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - output rx_sysref_p; - output rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 7:0] rx_data_p; - input [ 7:0] rx_data_n; - - output spi_fout_enb_clk; - output spi_fout_enb_mlo; - output spi_fout_enb_rst; - output spi_fout_enb_sync; - output spi_fout_enb_sysref; - output spi_fout_enb_trig; - output spi_fout_clk; - output spi_fout_sdio; - output [ 3:0] spi_afe_csn; - output spi_afe_clk; - inout spi_afe_sdio; - output spi_clk_csn; - output spi_clk_clk; - inout spi_clk_sdio; - - output afe_rst_p; - output afe_rst_n; - output afe_trig_p; - output afe_trig_n; - - output dac_sleep; - output [13:0] dac_data; - output afe_pdn; - output afe_stby; - output clk_resetn; - output clk_syncn; - input clk_status; - output amp_disbn; - inout prc_sck; - inout prc_cnv; - inout prc_sdo_i; - inout prc_sdo_q; + output dac_sleep, + output [13:0] dac_data, + output afe_pdn, + output afe_stby, + output clk_resetn, + output clk_syncn, + input clk_status, + output amp_disbn, + inout prc_sck, + inout prc_cnv, + inout prc_sdo_i, + inout prc_sdo_q); // internal signals