zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

all: Update verilog files to verilog-2001

main
Istvan Csomortani 2017-04-13 11:45:54 +03:00
parent 04a4001dba
commit 1c23cf4621
264 changed files with 8090 additions and 18421 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
library/altera/common/ad_cmos_clk.v
View File

@ -37,21 +37,16 @@
`timescale 1ns/100ps
module ad_cmos_clk (
module ad_cmos_clk #(
rst,
locked,
parameter DEVICE_TYPE = 0) (
clk_in,
clk);
input rst,
output locked,
parameter DEVICE_TYPE = 0;
input clk_in,
output clk);
input rst;
output locked;
input clk_in;
output clk;
// instantiations

58
library/altera/common/ad_cmos_in.v
View File

@ -37,60 +37,36 @@
`timescale 1ns/100ps
module ad_cmos_in (
module ad_cmos_in #(
parameter SINGLE_ENDED = 0,
parameter DEVICE_TYPE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
rx_clk,
rx_data_in,
rx_data_p,
rx_data_n,
input rx_clk,
input rx_data_in,
output reg rx_data_p,
output reg rx_data_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
input delay_clk,
input delay_rst,
output delay_locked);
// parameters
parameter SINGLE_ENDED = 0;
parameter DEVICE_TYPE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
// data interface
input rx_clk;
input rx_data_in;
output rx_data_p;
output rx_data_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg rx_data_p = 'd0;
reg rx_data_n = 'd0;
// internal signals
wire rx_data_p_s;

19
library/altera/common/ad_lvds_clk.v
View File

@ -37,23 +37,18 @@
`timescale 1ns/100ps
module ad_lvds_clk (
module ad_lvds_clk #(
rst,
locked,
parameter DEVICE_TYPE = 0) (
clk_in_p,
clk_in_n,
clk);
input rst,
output locked,
parameter DEVICE_TYPE = 0;
input clk_in_p,
input clk_in_n,
output clk);
input rst;
output locked;
input clk_in_p;
input clk_in_n;
output clk;
// instantiations

61
library/altera/common/ad_lvds_in.v
View File

@ -37,62 +37,37 @@
`timescale 1ns/100ps
module ad_lvds_in (
module ad_lvds_in #(
parameter SINGLE_ENDED = 0,
parameter DEVICE_TYPE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
rx_clk,
rx_data_in_p,
rx_data_in_n,
rx_data_p,
rx_data_n,
input rx_clk,
input rx_data_in_p,
input rx_data_in_n,
output reg rx_data_p,
output reg rx_data_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
input delay_clk,
input delay_rst,
output delay_locked);
// parameters
parameter SINGLE_ENDED = 0;
parameter DEVICE_TYPE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
// data interface
input rx_clk;
input rx_data_in_p;
input rx_data_in_n;
output rx_data_p;
output rx_data_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg rx_data_p = 'd0;
reg rx_data_n = 'd0;
// internal signals
wire rx_data_p_s;

60
library/altera/common/ad_lvds_out.v
View File

@ -37,57 +37,35 @@
`timescale 1ns/100ps
module ad_lvds_out (
module ad_lvds_out #(
parameter DEVICE_TYPE = 0,
parameter SINGLE_ENDED = 0,
parameter IODELAY_ENABLE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
tx_clk,
tx_data_p,
tx_data_n,
tx_data_out_p,
tx_data_out_n,
input tx_clk,
input tx_data_p,
input tx_data_n,
output tx_data_out_p,
output tx_data_out_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
input delay_clk,
input delay_rst,
output delay_locked);
// parameters
parameter DEVICE_TYPE = 0;
parameter SINGLE_ENDED = 0;
parameter IODELAY_ENABLE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
// data interface
input tx_clk;
input tx_data_p;
input tx_data_n;
output tx_data_out_p;
output tx_data_out_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// defaults

32
library/altera/common/ad_mul.v
View File

@ -39,41 +39,27 @@
`timescale 1ps/1ps
module ad_mul (
module ad_mul #(
parameter DELAY_DATA_WIDTH = 16) (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
input clk,
input [16:0] data_a,
input [16:0] data_b,
output [33:0] data_p,
// delay interface
ddata_in,
ddata_out);
input [(DELAY_DATA_WIDTH-1):0] ddata_in,
output reg [(DELAY_DATA_WIDTH-1):0] ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
// data_p = data_a * data_b;
input clk;
input [16:0] data_a;
input [16:0] data_b;
output [33:0] data_p;
// delay interface
input [(DELAY_DATA_WIDTH-1):0] ddata_in;
output [(DELAY_DATA_WIDTH-1):0] ddata_out;
// internal registers
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] ddata_out = 'd0;
// a/b reg, m-reg, p-reg delay match

128
library/axi_ad6676/axi_ad6676.v
View File

@ -39,103 +39,57 @@
`timescale 1ns/100ps
module axi_ad6676 (
module axi_ad6676 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_valid,
rx_ready,
rx_data,
input rx_clk,
input [ 3:0] rx_sof,
input rx_valid,
output rx_ready,
input [63:0] rx_data,
// dma interface
adc_clk,
adc_rst,
adc_valid_0,
adc_enable_0,
adc_data_0,
adc_valid_1,
adc_enable_1,
adc_data_1,
adc_dovf,
adc_dunf,
output adc_clk,
output adc_rst,
output adc_valid_0,
output adc_enable_0,
output [31:0] adc_data_0,
output adc_valid_1,
output adc_enable_1,
output [31:0] adc_data_1,
input adc_dovf,
input adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input rx_valid;
output rx_ready;
input [63:0] rx_data;
// dma interface
output adc_clk;
output adc_rst;
output adc_valid_0;
output adc_enable_0;
output [31:0] adc_data_0;
output adc_valid_1;
output adc_enable_1;
output [31:0] adc_data_1;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal registers

75
library/axi_ad6676/axi_ad6676_channel.v
View File

@ -40,68 +40,39 @@
`timescale 1ns/100ps
module axi_ad6676_channel (
module axi_ad6676_channel #(
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0) (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input [31:0] adc_data,
input adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [31:0] adc_dfmt_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [31:0] adc_data;
input adc_or;
// channel interface
output [31:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

45
library/axi_ad6676/axi_ad6676_if.v
View File

@ -39,49 +39,30 @@
`timescale 1ns/100ps
module axi_ad6676_if (
module axi_ad6676_if #(
parameter DEVICE_TYPE = 0) (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_data,
input rx_clk,
input [ 3:0] rx_sof,
input [63:0] rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status);
output adc_clk,
input adc_rst,
output [31:0] adc_data_a,
output [31:0] adc_data_b,
output adc_or_a,
output adc_or_b,
output reg adc_status);
// parameters
parameter DEVICE_TYPE = 0;
// jesd interface
input rx_clk;
input [ 3:0] rx_sof;
input [63:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [31:0] adc_data_a;
output [31:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s1_s;

24
library/axi_ad6676/axi_ad6676_pnmon.v
View File

@ -44,31 +44,17 @@ module axi_ad6676_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [31:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
output adc_pn_oos,
output adc_pn_err,
// processor interface
adc_pnseq_sel);
// adc interface
input adc_clk;
input [31:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
input [ 3:0] adc_pnseq_sel);
// internal registers

132
library/axi_ad7616/axi_ad7616.v
View File

@ -39,66 +39,62 @@
`timescale 1ns/100ps
module axi_ad7616 (
module axi_ad7616 #(
parameter ID = 0,
parameter IF_TYPE = 1) (
// physical data interface
rx_sclk,
rx_cs_n,
rx_sdo,
rx_sdi_0,
rx_sdi_1,
output rx_sclk,
output rx_cs_n,
output rx_sdo,
input rx_sdi_0,
input rx_sdi_1,
rx_db_o,
rx_db_i,
rx_db_t,
rx_rd_n,
rx_wr_n,
output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
output rx_rd_n,
output rx_wr_n,
// physical control interface
rx_cnvst,
rx_busy,
output rx_cnvst,
input rx_busy,
// AXI Slave Memory Map
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
// Write FIFO interface
adc_valid,
adc_data,
adc_sync,
output adc_valid,
output [15:0] adc_data,
output adc_sync,
irq
);
output irq);
// parameters
parameter ID = 0;
parameter IF_TYPE = 1;
// local parameters
localparam NUM_OF_SDI = 2;
localparam SERIAL = 0;
@ -106,52 +102,6 @@ module axi_ad7616 (
localparam NEG_EDGE = 1;
localparam UP_ADDRESS_WIDTH = 14;
// IO definitions
output rx_sclk;
output rx_cs_n;
output rx_sdo;
input rx_sdi_0;
input rx_sdi_1;
output [15:0] rx_db_o;
input [15:0] rx_db_i;
output rx_db_t;
output rx_rd_n;
output rx_wr_n;
output rx_cnvst;
input rx_busy;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
output adc_valid;
output [15:0] adc_data;
output adc_sync;
output irq;
// internal registers
reg up_wack = 1'b0;

76
library/axi_ad7616/axi_ad7616_control.v
View File

@ -39,39 +39,39 @@
`timescale 1ns/100ps
module axi_ad7616_control (
module axi_ad7616_control #(
parameter ID = 0,
parameter IF_TYPE = 0) (
// control signals
cnvst,
busy,
output cnvst,
input busy,
up_read_data,
up_read_valid,
up_write_data,
up_read_req,
up_write_req,
input [15:0] up_read_data,
input up_read_valid,
output reg [15:0] up_write_data,
output up_read_req,
output up_write_req,
up_burst_length,
end_of_conv,
output reg [ 4:0] up_burst_length,
output end_of_conv,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack
);
parameter ID = 0;
parameter IF_TYPE = 0;
localparam PCORE_VERSION = 'h0001001;
localparam POS_EDGE = 0;
@ -79,42 +79,12 @@ module axi_ad7616_control (
localparam SERIAL = 0;
localparam PARALLEL = 1;
output cnvst;
input busy;
output end_of_conv;
output [ 4:0] up_burst_length;
input [15:0] up_read_data;
input up_read_valid;
output [15:0] up_write_data;
output up_read_req;
output up_write_req;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
reg [31:0] up_scratch = 32'b0;
reg up_resetn = 1'b0;
reg up_cnvst_en = 1'b0;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_conv_rate = 32'b0;
reg [ 4:0] up_burst_length = 5'h0;
reg [15:0] up_write_data = 16'h0;
reg [31:0] cnvst_counter = 32'b0;
reg [ 3:0] pulse_counter = 8'b0;

48
library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
View File

@ -39,49 +39,29 @@
`timescale 1ns/100ps
module axi_ad7616_maxis2wrfifo (
module axi_ad7616_maxis2wrfifo #(
clk,
rstn,
sync_in,
parameter DATA_WIDTH = 16) (
input clk,
input rstn,
input sync_in,
// m_axis interface
m_axis_data,
m_axis_ready,
m_axis_valid,
m_axis_xfer_req,
input [DATA_WIDTH-1:0] m_axis_data,
output reg m_axis_ready,
input m_axis_valid,
output reg m_axis_xfer_req,
// write fifo interface
fifo_wr_en,
fifo_wr_data,
fifo_wr_sync,
fifo_wr_xfer_req
output reg fifo_wr_en,
output reg [DATA_WIDTH-1:0] fifo_wr_data,
output reg fifo_wr_sync,
input fifo_wr_xfer_req
);
parameter DATA_WIDTH = 16;
input clk;
input rstn;
input sync_in;
input [DATA_WIDTH-1:0] m_axis_data;
output m_axis_ready;
input m_axis_valid;
output m_axis_xfer_req;
output fifo_wr_en;
output [DATA_WIDTH-1:0] fifo_wr_data;
output fifo_wr_sync;
input fifo_wr_xfer_req;
reg m_axis_ready = 1'b0;
reg m_axis_xfer_req = 1'b0;
reg fifo_wr_en = 1'b0;
reg [DATA_WIDTH-1:0] fifo_wr_data = 'b0;
reg fifo_wr_sync = 1'b0;
always @(posedge clk) begin
if (rstn == 1'b0) begin

69
library/axi_ad7616/axi_ad7616_pif.v
View File

@ -39,64 +39,40 @@
`timescale 1ns/100ps
module axi_ad7616_pif (
module axi_ad7616_pif #(
parameter UP_ADDRESS_WIDTH = 14) (
// physical interface
cs_n,
db_o,
db_i,
db_t,
rd_n,
wr_n,
output cs_n,
output [15:0] db_o,
input [15:0] db_i,
output db_t,
output rd_n,
output wr_n,
// FIFO interface
adc_data,
adc_valid,
adc_sync,
output [15:0] adc_data,
output adc_valid,
output reg adc_sync,
// end of convertion
end_of_conv,
burst_length,
input end_of_conv,
input [ 4:0] burst_length,
// register access
clk,
rstn,
rd_req,
wr_req,
wr_data,
rd_data,
rd_valid
);
input clk,
input rstn,
input rd_req,
input wr_req,
input [15:0] wr_data,
output reg [15:0] rd_data,
output reg rd_valid);
parameter UP_ADDRESS_WIDTH = 14;
// IO definitions
output cs_n;
output [15:0] db_o;
input [15:0] db_i;
output db_t;
output rd_n;
output wr_n;
input end_of_conv;
input [ 4:0] burst_length;
input clk;
input rstn;
input rd_req;
input wr_req;
input [15:0] wr_data;
output [15:0] rd_data;
output rd_valid;
output [15:0] adc_data;
output adc_valid;
output adc_sync;
// state registers
@ -121,10 +97,7 @@ module axi_ad7616_pif (
reg xfer_req_d = 1'h0;
reg adc_sync = 1'h0;
reg rd_valid = 1'h0;
reg rd_valid_d = 1'h0;
reg [15:0] rd_data = 16'h0;
// internal wires

160
library/axi_ad9122/axi_ad9122.v
View File

@ -37,125 +37,71 @@
`timescale 1ns/100ps
module axi_ad9122 (
module axi_ad9122 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter SERDES_OR_DDR_N = 1,
parameter MMCM_OR_BUFIO_N = 1,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 2,
parameter MMCM_VCO_MUL = 4,
parameter MMCM_CLK0_DIV = 2,
parameter MMCM_CLK1_DIV = 8,
parameter DAC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
input dac_clk_in_p,
input dac_clk_in_n,
output dac_clk_out_p,
output dac_clk_out_n,
output dac_frame_out_p,
output dac_frame_out_n,
output [15:0] dac_data_out_p,
output [15:0] dac_data_out_n,
// master/slave
dac_sync_out,
dac_sync_in,
output dac_sync_out,
input dac_sync_in,
// dma interface
dac_div_clk,
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
output dac_div_clk,
output dac_valid_0,
output dac_enable_0,
input [63:0] dac_ddata_0,
output dac_valid_1,
output dac_enable_1,
input [63:0] dac_ddata_1,
input dac_dovf,
input dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFIO_N = 1;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 2;
parameter MMCM_VCO_MUL = 4;
parameter MMCM_CLK0_DIV = 2;
parameter MMCM_CLK1_DIV = 8;
parameter DAC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
// master/slave
output dac_sync_out;
input dac_sync_in;
// dma interface
output dac_div_clk;
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal clocks and resets

78
library/axi_ad9122/axi_ad9122_channel.v
View File

@ -39,74 +39,42 @@
`timescale 1ns/100ps
module axi_ad9122_channel (
module axi_ad9122_channel #(
parameter CHANNEL_ID = 32'h0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_div_clk,
dac_rst,
dac_enable,
dac_data,
dac_frame,
dma_data,
input dac_div_clk,
input dac_rst,
output reg dac_enable,
output reg [63:0] dac_data,
output reg [ 3:0] dac_frame,
input [63:0] dma_data,
// processor interface
dac_data_frame,
dac_data_sync,
dac_dds_format,
input dac_data_frame,
input dac_data_sync,
input dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_div_clk;
input dac_rst;
output dac_enable;
output [63:0] dac_data;
output [ 3:0] dac_frame;
input [63:0] dma_data;
// processor interface
input dac_data_frame;
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [63:0] dac_data = 'd0;
reg [ 3:0] dac_frame = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;

172
library/axi_ad9122/axi_ad9122_core.v
View File

@ -37,149 +37,79 @@
`timescale 1ns/100ps
module axi_ad9122_core (
module axi_ad9122_core #(
parameter ID = 0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_div_clk,
dac_rst,
dac_frame_i0,
dac_data_i0,
dac_frame_i1,
dac_data_i1,
dac_frame_i2,
dac_data_i2,
dac_frame_i3,
dac_data_i3,
dac_frame_q0,
dac_data_q0,
dac_frame_q1,
dac_data_q1,
dac_frame_q2,
dac_data_q2,
dac_frame_q3,
dac_data_q3,
dac_status,
input dac_div_clk,
output dac_rst,
output dac_frame_i0,
output [15:0] dac_data_i0,
output dac_frame_i1,
output [15:0] dac_data_i1,
output dac_frame_i2,
output [15:0] dac_data_i2,
output dac_frame_i3,
output [15:0] dac_data_i3,
output dac_frame_q0,
output [15:0] dac_data_q0,
output dac_frame_q1,
output [15:0] dac_data_q1,
output dac_frame_q2,
output [15:0] dac_data_q2,
output dac_frame_q3,
output [15:0] dac_data_q3,
input dac_status,
// master/slave
dac_sync_out,
dac_sync_in,
output dac_sync_out,
input dac_sync_in,
// dma interface
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
output dac_valid_0,
output dac_enable_0,
input [63:0] dac_ddata_0,
output dac_valid_1,
output dac_enable_1,
input [63:0] dac_ddata_1,
input dac_dovf,
input dac_dunf,
// mmcm reset
mmcm_rst,
output mmcm_rst,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
output up_drp_sel,
output up_drp_wr,
output [11:0] up_drp_addr,
output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata,
input up_drp_ready,
input up_drp_locked,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// parameters
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_div_clk;
output dac_rst;
output dac_frame_i0;
output [15:0] dac_data_i0;
output dac_frame_i1;
output [15:0] dac_data_i1;
output dac_frame_i2;
output [15:0] dac_data_i2;
output dac_frame_i3;
output [15:0] dac_data_i3;
output dac_frame_q0;
output [15:0] dac_data_q0;
output dac_frame_q1;
output [15:0] dac_data_q1;
output dac_frame_q2;
output [15:0] dac_data_q2;
output dac_frame_q3;
output [15:0] dac_data_q3;
input dac_status;
// master/slave
output dac_sync_out;
input dac_sync_in;
// dma interface
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// mmcm reset
output mmcm_rst;
// drp interface
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [31:0] up_drp_wdata;
input [31:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;

154
library/axi_ad9122/axi_ad9122_if.v
View File

@ -39,132 +39,76 @@
`timescale 1ns/100ps
module axi_ad9122_if (
module axi_ad9122_if #(
parameter DEVICE_TYPE = 0,
parameter SERDES_OR_DDR_N = 1,
parameter MMCM_OR_BUFIO_N = 1,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12,
parameter MMCM_CLK0_DIV = 2,
parameter MMCM_CLK1_DIV = 8,
parameter IO_DELAY_GROUP = "dac_if_delay_group") (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
input dac_clk_in_p,
input dac_clk_in_n,
output dac_clk_out_p,
output dac_clk_out_n,
output dac_frame_out_p,
output dac_frame_out_n,
output [15:0] dac_data_out_p,
output [15:0] dac_data_out_n,
// internal resets and clocks
dac_rst,
dac_clk,
dac_div_clk,
dac_status,
input dac_rst,
output dac_clk,
output dac_div_clk,
output reg dac_status,
// data interface
dac_frame_i0,
dac_data_i0,
dac_frame_i1,
dac_data_i1,
dac_frame_i2,
dac_data_i2,
dac_frame_i3,
dac_data_i3,
input dac_frame_i0,
input [15:0] dac_data_i0,
input dac_frame_i1,
input [15:0] dac_data_i1,
input dac_frame_i2,
input [15:0] dac_data_i2,
input dac_frame_i3,
input [15:0] dac_data_i3,
dac_frame_q0,
dac_data_q0,
dac_frame_q1,
dac_data_q1,
dac_frame_q2,
dac_data_q2,
dac_frame_q3,
dac_data_q3,
input dac_frame_q0,
input [15:0] dac_data_q0,
input dac_frame_q1,
input [15:0] dac_data_q1,
input dac_frame_q2,
input [15:0] dac_data_q2,
input dac_frame_q3,
input [15:0] dac_data_q3,
// mmcm reset
mmcm_rst,
input mmcm_rst,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// parameters
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFIO_N = 1;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12;
parameter MMCM_CLK0_DIV = 2;
parameter MMCM_CLK1_DIV = 8;
parameter IO_DELAY_GROUP = "dac_if_delay_group";
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
// internal resets and clocks
input dac_rst;
output dac_clk;
output dac_div_clk;
output dac_status;
// data interface
input dac_frame_i0;
input [15:0] dac_data_i0;
input dac_frame_i1;
input [15:0] dac_data_i1;
input dac_frame_i2;
input [15:0] dac_data_i2;
input dac_frame_i3;
input [15:0] dac_data_i3;
input dac_frame_q0;
input [15:0] dac_data_q0;
input dac_frame_q1;
input [15:0] dac_data_q1;
input dac_frame_q2;
input [15:0] dac_data_q2;
input dac_frame_q3;
input [15:0] dac_data_q3;
// mmcm reset
input mmcm_rst;
// drp interface
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [31:0] up_drp_wdata;
output [31:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg dac_status_m1 = 'd0;
reg dac_status = 'd0;
// internal signals

143
library/axi_ad9144/axi_ad9144.v
View File

@ -37,114 +37,63 @@
`timescale 1ns/100ps
module axi_ad9144 (
module axi_ad9144 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter QUAD_OR_DUAL_N = 1,
parameter DAC_DATAPATH_DISABLE = 0) (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_valid,
tx_data,
tx_ready,
input tx_clk,
output tx_valid,
output [(128*QUAD_OR_DUAL_N)+127:0] tx_data,
input tx_ready,
// dma interface
dac_clk,
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_valid_2,
dac_enable_2,
dac_ddata_2,
dac_valid_3,
dac_enable_3,
dac_ddata_3,
dac_dovf,
dac_dunf,
output dac_clk,
output dac_valid_0,
output dac_enable_0,
input [63:0] dac_ddata_0,
output dac_valid_1,
output dac_enable_1,
input [63:0] dac_ddata_1,
output dac_valid_2,
output dac_enable_2,
input [63:0] dac_ddata_2,
output dac_valid_3,
output dac_enable_3,
input [63:0] dac_ddata_3,
input dac_dovf,
input dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter QUAD_OR_DUAL_N = 1;
parameter DAC_DATAPATH_DISABLE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output tx_valid;
output [(128*QUAD_OR_DUAL_N)+127:0] tx_data;
input tx_ready;
// dma interface
output dac_clk;
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
output dac_valid_2;
output dac_enable_2;
input [63:0] dac_ddata_2;
output dac_valid_3;
output dac_enable_3;
input [63:0] dac_ddata_3;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets

73
library/axi_ad9144/axi_ad9144_channel.v
View File

@ -37,69 +37,40 @@
`timescale 1ns/100ps
module axi_ad9144_channel (
module axi_ad9144_channel #(
parameter CHANNEL_ID = 32'h0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_clk,
dac_rst,
dac_enable,
dac_data,
dma_data,
input dac_clk,
input dac_rst,
output reg dac_enable,
output reg [63:0] dac_data,
input [63:0] dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
input dac_data_sync,
input dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
output dac_enable;
output [63:0] dac_data;
input [63:0] dma_data;
// processor interface
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [63:0] dac_data = 'd0;
reg [63:0] dac_pn7_data = 'd0;
reg [63:0] dac_pn15_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
@ -456,6 +427,4 @@ endmodule
// ***************************************************************************
// ***************************************************************************

148
library/axi_ad9144/axi_ad9144_core.v
View File

@ -39,121 +39,65 @@
`timescale 1ns/100ps
module axi_ad9144_core (
module axi_ad9144_core #(
parameter ID = 0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
dac_data_2_0,
dac_data_2_1,
dac_data_2_2,
dac_data_2_3,
dac_data_3_0,
dac_data_3_1,
dac_data_3_2,
dac_data_3_3,
input dac_clk,
output dac_rst,
output [15:0] dac_data_0_0,
output [15:0] dac_data_0_1,
output [15:0] dac_data_0_2,
output [15:0] dac_data_0_3,
output [15:0] dac_data_1_0,
output [15:0] dac_data_1_1,
output [15:0] dac_data_1_2,
output [15:0] dac_data_1_3,
output [15:0] dac_data_2_0,
output [15:0] dac_data_2_1,
output [15:0] dac_data_2_2,
output [15:0] dac_data_2_3,
output [15:0] dac_data_3_0,
output [15:0] dac_data_3_1,
output [15:0] dac_data_3_2,
output [15:0] dac_data_3_3,
// dma interface
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_valid_2,
dac_enable_2,
dac_ddata_2,
dac_valid_3,
dac_enable_3,
dac_ddata_3,
dac_dovf,
dac_dunf,
output dac_valid_0,
output dac_enable_0,
input [63:0] dac_ddata_0,
output dac_valid_1,
output dac_enable_1,
input [63:0] dac_ddata_1,
output dac_valid_2,
output dac_enable_2,
input [63:0] dac_ddata_2,
output dac_valid_3,
output dac_enable_3,
input [63:0] dac_ddata_3,
input dac_dovf,
input dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// parameters
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_clk;
output dac_rst;
output [15:0] dac_data_0_0;
output [15:0] dac_data_0_1;
output [15:0] dac_data_0_2;
output [15:0] dac_data_0_3;
output [15:0] dac_data_1_0;
output [15:0] dac_data_1_1;
output [15:0] dac_data_1_2;
output [15:0] dac_data_1_3;
output [15:0] dac_data_2_0;
output [15:0] dac_data_2_1;
output [15:0] dac_data_2_2;
output [15:0] dac_data_2_3;
output [15:0] dac_data_3_0;
output [15:0] dac_data_3_1;
output [15:0] dac_data_3_2;
output [15:0] dac_data_3_3;
// dma interface
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
output dac_valid_2;
output dac_enable_2;
input [63:0] dac_ddata_2;
output dac_valid_3;
output dac_enable_3;
input [63:0] dac_ddata_3;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;

76
library/axi_ad9144/axi_ad9144_if.v
View File

@ -37,70 +37,40 @@
`timescale 1ns/100ps
module axi_ad9144_if (
module axi_ad9144_if #(
parameter DEVICE_TYPE = 0) (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
input tx_clk,
output reg [255:0] tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
dac_data_2_0,
dac_data_2_1,
dac_data_2_2,
dac_data_2_3,
dac_data_3_0,
dac_data_3_1,
dac_data_3_2,
dac_data_3_3);
output dac_clk,
input dac_rst,
input [15:0] dac_data_0_0,
input [15:0] dac_data_0_1,
input [15:0] dac_data_0_2,
input [15:0] dac_data_0_3,
input [15:0] dac_data_1_0,
input [15:0] dac_data_1_1,
input [15:0] dac_data_1_2,
input [15:0] dac_data_1_3,
input [15:0] dac_data_2_0,
input [15:0] dac_data_2_1,
input [15:0] dac_data_2_2,
input [15:0] dac_data_2_3,
input [15:0] dac_data_3_0,
input [15:0] dac_data_3_1,
input [15:0] dac_data_3_2,
input [15:0] dac_data_3_3);
// altera (0x1) or xilinx (0x0)
parameter DEVICE_TYPE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [255:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [15:0] dac_data_0_0;
input [15:0] dac_data_0_1;
input [15:0] dac_data_0_2;
input [15:0] dac_data_0_3;
input [15:0] dac_data_1_0;
input [15:0] dac_data_1_1;
input [15:0] dac_data_1_2;
input [15:0] dac_data_1_3;
input [15:0] dac_data_2_0;
input [15:0] dac_data_2_1;
input [15:0] dac_data_2_2;
input [15:0] dac_data_2_3;
input [15:0] dac_data_3_0;
input [15:0] dac_data_3_1;
input [15:0] dac_data_3_2;
input [15:0] dac_data_3_3;
// internal registers
reg [255:0] tx_data = 'd0;
// reorder data for the jesd links
assign dac_clk = tx_clk;

123
library/axi_ad9152/axi_ad9152.v
View File

@ -39,101 +39,56 @@
`timescale 1ns/100ps
module axi_ad9152 (
module axi_ad9152 #(
parameter ID = 0,
parameter DAC_DATAPATH_DISABLE = 0,
parameter DEVICE_TYPE = 0) (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
tx_valid,
tx_ready,
input tx_clk,
output [127:0] tx_data,
output tx_valid,
input tx_ready,
// dma interface
dac_clk,
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
output dac_clk,
output dac_valid_0,
output dac_enable_0,
input [ 63:0] dac_ddata_0,
output dac_valid_1,
output dac_enable_1,
input [ 63:0] dac_ddata_1,
input dac_dovf,
input dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// parameters
parameter ID = 0;
parameter DAC_DATAPATH_DISABLE = 0;
parameter DEVICE_TYPE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [127:0] tx_data;
output tx_valid;
input tx_ready;
// dma interface
output dac_clk;
output dac_valid_0;
output dac_enable_0;
input [ 63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [ 63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets

71
library/axi_ad9152/axi_ad9152_channel.v
View File

@ -37,69 +37,40 @@
`timescale 1ns/100ps
module axi_ad9152_channel (
module axi_ad9152_channel #(
parameter CHANNEL_ID = 32'h0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_clk,
dac_rst,
dac_enable,
dac_data,
dma_data,
input dac_clk,
input dac_rst,
output reg dac_enable,
output reg [63:0] dac_data,
input [63:0] dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
input dac_data_sync,
input dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
output dac_enable;
output [63:0] dac_data;
input [63:0] dma_data;
// processor interface
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [63:0] dac_data = 'd0;
reg [63:0] dac_pn7_data = 'd0;
reg [63:0] dac_pn15_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;

106
library/axi_ad9152/axi_ad9152_core.v
View File

@ -39,93 +39,51 @@
`timescale 1ns/100ps
module axi_ad9152_core (
module axi_ad9152_core #(
parameter ID = 0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
input dac_clk,
output dac_rst,
output [15:0] dac_data_0_0,
output [15:0] dac_data_0_1,
output [15:0] dac_data_0_2,
output [15:0] dac_data_0_3,
output [15:0] dac_data_1_0,
output [15:0] dac_data_1_1,
output [15:0] dac_data_1_2,
output [15:0] dac_data_1_3,
// dma interface
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
output dac_valid_0,
output dac_enable_0,
input [63:0] dac_ddata_0,
output dac_valid_1,
output dac_enable_1,
input [63:0] dac_ddata_1,
input dac_dovf,
input dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// parameters
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_clk;
output dac_rst;
output [15:0] dac_data_0_0;
output [15:0] dac_data_0_1;
output [15:0] dac_data_0_2;
output [15:0] dac_data_0_3;
output [15:0] dac_data_1_0;
output [15:0] dac_data_1_1;
output [15:0] dac_data_1_2;
output [15:0] dac_data_1_3;
// dma interface
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;

107
library/axi_ad9162/axi_ad9162.v
View File

@ -37,95 +37,60 @@
`timescale 1ns / 1ps
module axi_ad9162 (
module axi_ad9162 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter DAC_DATAPATH_DISABLE = 0) (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_valid,
tx_data,
tx_ready,
input tx_clk,
output tx_valid,
output [255:0] tx_data,
input tx_ready,
// dma interface
dac_clk,
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
output dac_clk,
output dac_valid,
output dac_enable,
input [255:0] dac_ddata,
input dac_dovf,
input dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter DAC_DATAPATH_DISABLE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output tx_valid;
output [255:0] tx_data;
input tx_ready;
// dma interface
output dac_clk;
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets

64
library/axi_ad9162/axi_ad9162_channel.v
View File

@ -37,69 +37,47 @@
`timescale 1ns / 1ps
module axi_ad9162_channel (
module axi_ad9162_channel #(
parameter CHANNEL_ID = 32'h0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_clk,
dac_rst,
dac_enable,
dac_data,
dma_data,
input dac_clk,
input dac_rst,
output reg dac_enable,
output reg [255:0] dac_data,
input [255:0] dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
input dac_data_sync,
input dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output [ 31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
output dac_enable;
output [255:0] dac_data;
input [255:0] dma_data;
// processor interface
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [255:0] dac_data = 'd0;
reg [255:0] dac_data_int = 'd0;
reg [ 15:0] dac_dds_phase_00_0 = 'd0;
reg [ 15:0] dac_dds_phase_00_1 = 'd0;

80
library/axi_ad9162/axi_ad9162_core.v
View File

@ -37,73 +37,49 @@
`timescale 1ns / 1ps
module axi_ad9162_core (
module axi_ad9162_core #(
parameter ID = 0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_clk,
dac_rst,
dac_data,
input dac_clk,
output dac_rst,
output [255:0] dac_data,
// dma interface
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
output dac_valid,
output dac_enable,
input [255:0] dac_ddata,
input dac_dovf,
input dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_clk;
output dac_rst;
output [255:0] dac_data;
// dma interface
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals

25
library/axi_ad9162/axi_ad9162_if.v
View File

@ -37,39 +37,30 @@
`timescale 1ns / 1ps
module axi_ad9162_if (
module axi_ad9162_if #(
parameter DEVICE_TYPE = 0) (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
input tx_clk,
output reg [255:0] tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data);
output dac_clk,
input dac_rst,
input [255:0] dac_data);
// altera (0x1) or xilinx (0x0)
parameter DEVICE_TYPE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [255:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [255:0] dac_data;
// internal registers
reg [255:0] tx_data = 'd0;
// reorder data for the jesd links

116
library/axi_ad9234/axi_ad9234.v
View File

@ -39,95 +39,53 @@
`timescale 1ns/100ps
module axi_ad9234 (
module axi_ad9234 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
input rx_clk,
input [127:0] rx_data,
// dma interface
adc_clk,
adc_enable_0,
adc_valid_0,
adc_data_0,
adc_enable_1,
adc_valid_1,
adc_data_1,
adc_dovf,
adc_dunf,
output adc_clk,
output adc_enable_0,
output adc_valid_0,
output [63:0] adc_data_0,
output adc_enable_1,
output adc_valid_1,
output [63:0] adc_data_1,
input adc_dovf,
input adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [127:0] rx_data;
// dma interface
output adc_clk;
output adc_enable_0;
output adc_valid_0;
output [63:0] adc_data_0;
output adc_enable_1;
output adc_valid_1;
output [63:0] adc_data_1;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal registers

75
library/axi_ad9234/axi_ad9234_channel.v
View File

@ -40,68 +40,39 @@
`timescale 1ns/100ps
module axi_ad9234_channel (
module axi_ad9234_channel #(
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0) (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input [63:0] adc_data,
input adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [63:0] adc_dfmt_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [63:0] adc_data;
input adc_or;
// channel interface
output [63:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

36
library/axi_ad9234/axi_ad9234_if.v
View File

@ -45,39 +45,21 @@ module axi_ad9234_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
input rx_clk,
input [127:0] rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status);
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [127:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [63:0] adc_data_a;
output [63:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
output adc_clk,
input adc_rst,
output [63:0] adc_data_a,
output [63:0] adc_data_b,
output adc_or_a,
output adc_or_b,
output reg adc_status);
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s3_s;

24
library/axi_ad9234/axi_ad9234_pnmon.v
View File

@ -44,31 +44,17 @@ module axi_ad9234_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [63:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
output adc_pn_oos,
output adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pnseq_sel);
// adc interface
input adc_clk;
input [63:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
input [ 3:0] adc_pnseq_sel);
// internal registers

125
library/axi_ad9250/axi_ad9250.v
View File

@ -37,102 +37,57 @@
`timescale 1ns/100ps
module axi_ad9250 (
module axi_ad9250 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0) (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_valid,
rx_data,
rx_ready,
input rx_clk,
input [ 3:0] rx_sof,
input rx_valid,
input [63:0] rx_data,
output rx_ready,
// dma interface
adc_clk,
adc_rst,
adc_valid_a,
adc_enable_a,
adc_data_a,
adc_valid_b,
adc_enable_b,
adc_data_b,
adc_dovf,
adc_dunf,
output adc_clk,
output adc_rst,
output adc_valid_a,
output adc_enable_a,
output [31:0] adc_data_a,
output adc_valid_b,
output adc_enable_b,
output [31:0] adc_data_b,
input adc_dovf,
input adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
parameter ID = 0;
parameter DEVICE_TYPE = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input rx_valid;
input [63:0] rx_data;
output rx_ready;
// dma interface
output adc_clk;
output adc_rst;
output adc_valid_a;
output adc_enable_a;
output [31:0] adc_data_a;
output adc_valid_b;
output adc_enable_b;
output [31:0] adc_data_b;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal registers

75
library/axi_ad9250/axi_ad9250_channel.v
View File

@ -40,68 +40,39 @@
`timescale 1ns/100ps
module axi_ad9250_channel (
module axi_ad9250_channel #(
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0) (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input [27:0] adc_data,
input adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [31:0] adc_dfmt_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [27:0] adc_data;
input adc_or;
// channel interface
output [31:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

46
library/axi_ad9250/axi_ad9250_if.v
View File

@ -37,50 +37,30 @@
`timescale 1ns/100ps
module axi_ad9250_if (
module axi_ad9250_if #(
parameter DEVICE_TYPE = 0) (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_data,
input rx_clk,
input [ 3:0] rx_sof,
input [63:0] rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status);
output adc_clk,
input adc_rst,
output [27:0] adc_data_a,
output [27:0] adc_data_b,
output adc_or_a,
output adc_or_b,
output reg adc_status);
// parameters
parameter DEVICE_TYPE = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input [63:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [27:0] adc_data_a;
output [27:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s1_s;

24
library/axi_ad9250/axi_ad9250_pnmon.v
View File

@ -44,31 +44,17 @@ module axi_ad9250_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [27:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
output adc_pn_oos,
output adc_pn_err,
// processor interface
adc_pnseq_sel);
// adc interface
input adc_clk;
input [27:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
input [ 3:0] adc_pnseq_sel);
// internal registers

131
library/axi_ad9265/axi_ad9265.v
View File

@ -39,108 +39,59 @@
`timescale 1ns/100ps
module axi_ad9265 (
module axi_ad9265 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter ADC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [ 7:0] adc_data_in_p,
input [ 7:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// delay interface
delay_clk,
input delay_clk,
// dma interface
adc_clk,
adc_rst,
adc_valid,
adc_enable,
adc_data,
adc_dovf,
adc_dunf,
output adc_clk,
output adc_rst,
output adc_valid,
output adc_enable,
output [15:0] adc_data,
input adc_dovf,
input adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_rst;
output adc_valid;
output adc_enable;
output [15:0] adc_data;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal registers

78
library/axi_ad9265/axi_ad9265_channel.v
View File

@ -40,70 +40,40 @@
`timescale 1ns/100ps
module axi_ad9265_channel (
module axi_ad9265_channel #(
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input [15:0] adc_data,
input adc_or,
// channel interface
adc_dcfilter_data_out,
adc_valid,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [15:0] adc_dcfilter_data_out,
output adc_valid,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [15:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dcfilter_data_out;
output adc_valid;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

73
library/axi_ad9265/axi_ad9265_if.v
View File

@ -39,76 +39,45 @@
`timescale 1ns/100ps
module axi_ad9265_if (
module axi_ad9265_if #(
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [ 7:0] adc_data_in_p,
input [ 7:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// interface outputs
adc_clk,
adc_data,
adc_or,
adc_status,
output adc_clk,
output reg [15:0] adc_data,
output reg adc_or,
output reg adc_status,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
input up_clk,
input [ 8:0] up_dld,
input [44:0] up_dwdata,
output [44:0] up_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
// This parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data;
output adc_or;
output adc_status;
// delay control signals
input up_clk;
input [ 8:0] up_dld;
input [44:0] up_dwdata;
output [44:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [ 7:0] adc_data_p = 'd0;
reg [ 7:0] adc_data_n = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg [15:0] adc_data = 'd0;
reg adc_or = 'd0;
// internal signals

21
library/axi_ad9265/axi_ad9265_pnmon.v
View File

@ -44,25 +44,14 @@ module axi_ad9265_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [15:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
output adc_pn_oos,
output adc_pn_err,
input [ 3:0] adc_pnseq_sel);
// internal registers

146
library/axi_ad9361/altera/axi_ad9361_cmos_if.v
View File

@ -37,133 +37,72 @@
`timescale 1ns/100ps
module axi_ad9361_cmos_if (
module axi_ad9361_cmos_if #(
parameter DEVICE_TYPE = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface (receive)
rx_clk_in,
rx_frame_in,
rx_data_in,
input rx_clk_in,
input rx_frame_in,
input [11:0] rx_data_in,
// physical interface (transmit)
tx_clk_out,
tx_frame_out,
tx_data_out,
output tx_clk_out,
output tx_frame_out,
output [11:0] tx_data_out,
// ensm control
enable,
txnrx,
output enable,
output txnrx,
// clock (common to both receive and transmit)
rst,
clk,
l_clk,
input rst,
input clk,
output l_clk,
// receive data path interface
adc_valid,
adc_data,
adc_status,
adc_r1_mode,
adc_ddr_edgesel,
output reg adc_valid,
output reg [47:0] adc_data,
output reg adc_status,
input adc_r1_mode,
input adc_ddr_edgesel,
// transmit data path interface
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
input dac_valid,
input [47:0] dac_data,
input dac_clksel,
input dac_r1_mode,
// tdd interface
tdd_enable,
tdd_txnrx,
tdd_mode,
input tdd_enable,
input tdd_txnrx,
input tdd_mode,
// delay interface
mmcm_rst,
up_clk,
up_enable,
up_txnrx,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
up_dac_dld,
up_dac_dwdata,
up_dac_drdata,
delay_clk,
delay_rst,
delay_locked);
input mmcm_rst,
input up_clk,
input up_enable,
input up_txnrx,
input [12:0] up_adc_dld,
input [64:0] up_adc_dwdata,
output [64:0] up_adc_drdata,
input [15:0] up_dac_dld,
input [79:0] up_dac_dwdata,
output [79:0] up_dac_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
// this parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface (receive)
input rx_clk_in;
input rx_frame_in;
input [11:0] rx_data_in;
// physical interface (transmit)
output tx_clk_out;
output tx_frame_out;
output [11:0] tx_data_out;
// ensm control
output enable;
output txnrx;
// clock (common to both receive and transmit)
input rst;
input clk;
output l_clk;
// receive data path interface
output adc_valid;
output [47:0] adc_data;
output adc_status;
input adc_r1_mode;
input adc_ddr_edgesel;
// transmit data path interface
input dac_valid;
input [47:0] dac_data;
input dac_clksel;
input dac_r1_mode;
// tdd interface
input tdd_enable;
input tdd_txnrx;
input tdd_mode;
// delay interface
input mmcm_rst;
input up_clk;
input up_enable;
input up_txnrx;
input [12:0] up_adc_dld;
input [64:0] up_adc_dwdata;
output [64:0] up_adc_drdata;
input [15:0] up_dac_dld;
input [79:0] up_dac_dwdata;
output [79:0] up_dac_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
@ -184,9 +123,6 @@ module axi_ad9361_cmos_if (
reg adc_valid_int = 'd0;
reg [47:0] adc_data_int = 'd0;
reg adc_status_int = 'd0;
reg adc_valid = 'd0;
reg [47:0] adc_data = 'd0;
reg adc_status = 'd0;
reg [ 1:0] tx_data_cnt = 'd0;
reg [47:0] tx_data = 'd0;
reg tx_frame_p = 'd0;

36
library/axi_ad9361/axi_ad9361_rx_pnmon.v
View File

@ -40,43 +40,29 @@
`timescale 1ns/100ps
module axi_ad9361_rx_pnmon (
module axi_ad9361_rx_pnmon #(
parameter Q_OR_I_N = 0,
parameter PRBS_SEL = 0) (
// adc interface
adc_clk,
adc_valid,
adc_data_i,
adc_data_q,
input adc_clk,
input adc_valid,
input [11:0] adc_data_i,
input [11:0] adc_data_q,
// pn out of sync and error
adc_pnseq_sel,
adc_pn_oos,
adc_pn_err);
input [ 3:0] adc_pnseq_sel,
output adc_pn_oos,
output adc_pn_err);
// parameters
parameter Q_OR_I_N = 0;
parameter PRBS_SEL = 0;
localparam PRBS_P09 = 0;
localparam PRBS_P11 = 1;
localparam PRBS_P15 = 2;
localparam PRBS_P20 = 3;
// adc interface
input adc_clk;
input adc_valid;
input [11:0] adc_data_i;
input [11:0] adc_data_q;
// pn out of sync and error
input [ 3:0] adc_pnseq_sel;
output adc_pn_oos;
output adc_pn_err;
// internal registers
reg adc_pn0_valid = 'd0;

82
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -43,81 +43,43 @@ module axi_ad9361_tdd (
// clock
clk,
rst,
input clk,
input rst,
// control signals from the tdd control
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
tdd_tx_rf_en,
output tdd_rx_vco_en,
output tdd_tx_vco_en,
output tdd_rx_rf_en,
output tdd_tx_rf_en,
// status signal
tdd_enabled,
tdd_status,
output tdd_enabled,
input [ 7:0] tdd_status,
// sync signal
tdd_sync,
tdd_sync_cntr,
input tdd_sync,
output reg tdd_sync_cntr,
// tx/rx data flow control
tdd_tx_valid,
tdd_rx_valid,
output reg tdd_tx_valid,
output reg tdd_rx_valid,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input clk;
input rst;
// control signals from the tdd control
output tdd_rx_vco_en;
output tdd_tx_vco_en;
output tdd_rx_rf_en;
output tdd_tx_rf_en;
output tdd_enabled;
input [ 7:0] tdd_status;
input tdd_sync;
output tdd_sync_cntr;
// data flow control
output tdd_tx_valid;
output tdd_rx_valid;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
reg tdd_tx_valid = 1'b0;
reg tdd_rx_valid = 1'b0;
reg tdd_sync_cntr = 1'b0;
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// internal signals

48
library/axi_ad9361/axi_ad9361_tdd_if.v
View File

@ -39,59 +39,35 @@
`timescale 1ns/1ps
module axi_ad9361_tdd_if(
module axi_ad9361_tdd_if#(
parameter LEVEL_OR_PULSE_N = 0) (
// clock
clk,
rst,
input clk,
input rst,
// control signals from the tdd control
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
tdd_tx_rf_en,
input tdd_rx_vco_en,
input tdd_tx_vco_en,
input tdd_rx_rf_en,
input tdd_tx_rf_en,
// device interface
ad9361_txnrx,
ad9361_enable,
output ad9361_txnrx,
output ad9361_enable,
// interface status
ad9361_tdd_status
);
output [ 7:0] ad9361_tdd_status);
// parameters
parameter LEVEL_OR_PULSE_N = 0; // the control signals are edge (pulse) or level sensitive
localparam PULSE_MODE = 0;
localparam LEVEL_MODE = 1;
// clock
input clk;
input rst;
// control signals from the tdd control
input tdd_rx_vco_en;
input tdd_tx_vco_en;
input tdd_rx_rf_en;
input tdd_tx_rf_en;
// device interface
output ad9361_txnrx;
output ad9361_enable;
// interface status
output [ 7:0] ad9361_tdd_status;
// internal registers
reg tdd_rx_rf_en_d = 1'b0;

146
library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
View File

@ -37,133 +37,72 @@
`timescale 1ns/100ps
module axi_ad9361_cmos_if (
module axi_ad9361_cmos_if #(
parameter DEVICE_TYPE = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface (receive)
rx_clk_in,
rx_frame_in,
rx_data_in,
input rx_clk_in,
input rx_frame_in,
input [11:0] rx_data_in,
// physical interface (transmit)
tx_clk_out,
tx_frame_out,
tx_data_out,
output tx_clk_out,
output tx_frame_out,
output [11:0] tx_data_out,
// ensm control
enable,
txnrx,
output enable,
output txnrx,
// clock (common to both receive and transmit)
rst,
clk,
l_clk,
input rst,
input clk,
output l_clk,
// receive data path interface
adc_valid,
adc_data,
adc_status,
adc_r1_mode,
adc_ddr_edgesel,
output reg adc_valid,
output reg [47:0] adc_data,
output reg adc_status,
input adc_r1_mode,
input adc_ddr_edgesel,
// transmit data path interface
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
input dac_valid,
input [47:0] dac_data,
input dac_clksel,
input dac_r1_mode,
// tdd interface
tdd_enable,
tdd_txnrx,
tdd_mode,
input tdd_enable,
input tdd_txnrx,
input tdd_mode,
// delay interface
mmcm_rst,
up_clk,
up_enable,
up_txnrx,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
up_dac_dld,
up_dac_dwdata,
up_dac_drdata,
delay_clk,
delay_rst,
delay_locked);
input mmcm_rst,
input up_clk,
input up_enable,
input up_txnrx,
input [12:0] up_adc_dld,
input [64:0] up_adc_dwdata,
output [64:0] up_adc_drdata,
input [15:0] up_dac_dld,
input [79:0] up_dac_dwdata,
output [79:0] up_dac_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
// this parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface (receive)
input rx_clk_in;
input rx_frame_in;
input [11:0] rx_data_in;
// physical interface (transmit)
output tx_clk_out;
output tx_frame_out;
output [11:0] tx_data_out;
// ensm control
output enable;
output txnrx;
// clock (common to both receive and transmit)
input rst;
input clk;
output l_clk;
// receive data path interface
output adc_valid;
output [47:0] adc_data;
output adc_status;
input adc_r1_mode;
input adc_ddr_edgesel;
// transmit data path interface
input dac_valid;
input [47:0] dac_data;
input dac_clksel;
input dac_r1_mode;
// tdd interface
input tdd_enable;
input tdd_txnrx;
input tdd_mode;
// delay interface
input mmcm_rst;
input up_clk;
input up_enable;
input up_txnrx;
input [12:0] up_adc_dld;
input [64:0] up_adc_dwdata;
output [64:0] up_adc_drdata;
input [15:0] up_dac_dld;
input [79:0] up_dac_dwdata;
output [79:0] up_dac_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
@ -184,9 +123,6 @@ module axi_ad9361_cmos_if (
reg adc_valid_int = 'd0;
reg [47:0] adc_data_int = 'd0;
reg adc_status_int = 'd0;
reg adc_valid = 'd0;
reg [47:0] adc_data = 'd0;
reg adc_status = 'd0;
reg [ 1:0] tx_data_cnt = 'd0;
reg [47:0] tx_data = 'd0;
reg tx_frame_p = 'd0;

188
library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
View File

@ -37,165 +37,88 @@
`timescale 1ns/100ps
module axi_ad9361_lvds_if (
module axi_ad9361_lvds_if #(
parameter DEVICE_TYPE = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface (receive)
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
// physical interface (transmit)
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
// ensm control
enable,
txnrx,
output enable,
output txnrx,
// clock (common to both receive and transmit)
rst,
clk,
l_clk,
input rst,
input clk,
output l_clk,
// receive data path interface
adc_valid,
adc_data,
adc_status,
adc_r1_mode,
adc_ddr_edgesel,
output reg adc_valid,
output reg [47:0] adc_data,
output reg adc_status,
input adc_r1_mode,
input adc_ddr_edgesel,
// transmit data path interface
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
input dac_valid,
input [47:0] dac_data,
input dac_clksel,
input dac_r1_mode,
// tdd interface
tdd_enable,
tdd_txnrx,
tdd_mode,
input tdd_enable,
input tdd_txnrx,
input tdd_mode,
// delay interface
mmcm_rst,
up_clk,
up_enable,
up_txnrx,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
up_dac_dld,
up_dac_dwdata,
up_dac_drdata,
delay_clk,
delay_rst,
delay_locked,
input mmcm_rst,
input up_clk,
input up_enable,
input up_txnrx,
input [ 6:0] up_adc_dld,
input [34:0] up_adc_dwdata,
output [34:0] up_adc_drdata,
input [ 9:0] up_dac_dld,
input [49:0] up_dac_dwdata,
output [49:0] up_dac_drdata,
input delay_clk,
input delay_rst,
output delay_locked,
//drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// this parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface (receive)
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
// physical interface (transmit)
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
// ensm control
output enable;
output txnrx;
// clock (common to both receive and transmit)
input rst;
input clk;
output l_clk;
// receive data path interface
output adc_valid;
output [47:0] adc_data;
output adc_status;
input adc_r1_mode;
input adc_ddr_edgesel;
// transmit data path interface
input dac_valid;
input [47:0] dac_data;
input dac_clksel;
input dac_r1_mode;
// tdd interface
input tdd_enable;
input tdd_txnrx;
input tdd_mode;
// delay interface
input mmcm_rst;
input up_clk;
input up_enable;
input up_txnrx;
input [ 6:0] up_adc_dld;
input [34:0] up_adc_dwdata;
output [34:0] up_adc_drdata;
input [ 9:0] up_dac_dld;
input [49:0] up_dac_dwdata;
output [49:0] up_dac_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
//drp interface
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [31:0] up_drp_wdata;
output [31:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
@ -223,9 +146,6 @@ module axi_ad9361_lvds_if (
reg adc_valid_int = 'd0;
reg [47:0] adc_data_int = 'd0;
reg adc_status_int = 'd0;
reg adc_valid = 'd0;
reg [47:0] adc_data = 'd0;
reg adc_status = 'd0;
reg [ 2:0] tx_data_cnt = 'd0;
reg [47:0] tx_data = 'd0;
reg tx_frame = 'd0;

249
library/axi_ad9371/axi_ad9371.v
View File

@ -37,194 +37,103 @@
`timescale 1ns/100ps
module axi_ad9371 (
module axi_ad9371 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter DAC_DATAPATH_DISABLE = 0,
parameter ADC_DATAPATH_DISABLE = 0) (
// receive
adc_clk,
adc_rx_valid,
adc_rx_sof,
adc_rx_data,
adc_rx_ready,
adc_os_clk,
adc_rx_os_valid,
adc_rx_os_sof,
adc_rx_os_data,
adc_rx_os_ready,
input adc_clk,
input adc_rx_valid,
input [ 3:0] adc_rx_sof,
input [ 63:0] adc_rx_data,
output adc_rx_ready,
input adc_os_clk,
input adc_rx_os_valid,
input [ 3:0] adc_rx_os_sof,
input [ 63:0] adc_rx_os_data,
output adc_rx_os_ready,
// transmit
dac_clk,
dac_tx_valid,
dac_tx_data,
dac_tx_ready,
input dac_clk,
output dac_tx_valid,
output [127:0] dac_tx_data,
input dac_tx_ready,
// master/slave
dac_sync_in,
dac_sync_out,
input dac_sync_in,
output dac_sync_out,
// dma interface
adc_enable_i0,
adc_valid_i0,
adc_data_i0,
adc_enable_q0,
adc_valid_q0,
adc_data_q0,
adc_enable_i1,
adc_valid_i1,
adc_data_i1,
adc_enable_q1,
adc_valid_q1,
adc_data_q1,
adc_dovf,
adc_dunf,
output adc_enable_i0,
output adc_valid_i0,
output [ 15:0] adc_data_i0,
output adc_enable_q0,
output adc_valid_q0,
output [ 15:0] adc_data_q0,
output adc_enable_i1,
output adc_valid_i1,
output [ 15:0] adc_data_i1,
output adc_enable_q1,
output adc_valid_q1,
output [ 15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
adc_os_enable_i0,
adc_os_valid_i0,
adc_os_data_i0,
adc_os_enable_q0,
adc_os_valid_q0,
adc_os_data_q0,
adc_os_dovf,
adc_os_dunf,
output adc_os_enable_i0,
output adc_os_valid_i0,
output [ 31:0] adc_os_data_i0,
output adc_os_enable_q0,
output adc_os_valid_q0,
output [ 31:0] adc_os_data_q0,
input adc_os_dovf,
input adc_os_dunf,
dac_enable_i0,
dac_valid_i0,
dac_data_i0,
dac_enable_q0,
dac_valid_q0,
dac_data_q0,
dac_enable_i1,
dac_valid_i1,
dac_data_i1,
dac_enable_q1,
dac_valid_q1,
dac_data_q1,
dac_dovf,
dac_dunf,
output dac_enable_i0,
output dac_valid_i0,
input [ 31:0] dac_data_i0,
output dac_enable_q0,
output dac_valid_q0,
input [ 31:0] dac_data_q0,
output dac_enable_i1,
output dac_valid_i1,
input [ 31:0] dac_data_i1,
output dac_enable_q1,
output dac_valid_q1,
input [ 31:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter DAC_DATAPATH_DISABLE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
// receive
input adc_clk;
input adc_rx_valid;
input [ 3:0] adc_rx_sof;
input [ 63:0] adc_rx_data;
output adc_rx_ready;
input adc_os_clk;
input adc_rx_os_valid;
input [ 3:0] adc_rx_os_sof;
input [ 63:0] adc_rx_os_data;
output adc_rx_os_ready;
// transmit
input dac_clk;
output dac_tx_valid;
output [127:0] dac_tx_data;
input dac_tx_ready;
// master/slave
input dac_sync_in;
output dac_sync_out;
// dma interface
output adc_enable_i0;
output adc_valid_i0;
output [ 15:0] adc_data_i0;
output adc_enable_q0;
output adc_valid_q0;
output [ 15:0] adc_data_q0;
output adc_enable_i1;
output adc_valid_i1;
output [ 15:0] adc_data_i1;
output adc_enable_q1;
output adc_valid_q1;
output [ 15:0] adc_data_q1;
input adc_dovf;
input adc_dunf;
output adc_os_enable_i0;
output adc_os_valid_i0;
output [ 31:0] adc_os_data_i0;
output adc_os_enable_q0;
output adc_os_valid_q0;
output [ 31:0] adc_os_data_q0;
input adc_os_dovf;
input adc_os_dunf;
output dac_enable_i0;
output dac_valid_i0;
input [ 31:0] dac_data_i0;
output dac_enable_q0;
output dac_valid_q0;
input [ 31:0] dac_data_q0;
output dac_enable_i1;
output dac_valid_i1;
input [ 31:0] dac_data_i1;
output dac_enable_q1;
output dac_valid_q1;
input [ 31:0] dac_data_q1;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal registers

49
library/axi_ad9371/axi_ad9371_if.v
View File

@ -37,49 +37,30 @@
`timescale 1ns/100ps
module axi_ad9371_if (
module axi_ad9371_if #(
parameter DEVICE_TYPE = 0) (
// receive
adc_clk,
adc_rx_sof,
adc_rx_data,
adc_os_clk,
adc_rx_os_sof,
adc_rx_os_data,
input adc_clk,
input [ 3:0] adc_rx_sof,
input [ 63:0] adc_rx_data,
input adc_os_clk,
input [ 3:0] adc_rx_os_sof,
input [ 63:0] adc_rx_os_data,
adc_data,
adc_os_valid,
adc_os_data,
output [ 63:0] adc_data,
output adc_os_valid,
output [ 63:0] adc_os_data,
// transmit
dac_clk,
dac_tx_data,
input dac_clk,
output [127:0] dac_tx_data,
dac_data);
input [127:0] dac_data);
// parameters
parameter DEVICE_TYPE = 0;
// receive
input adc_clk;
input [ 3:0] adc_rx_sof;
input [ 63:0] adc_rx_data;
input adc_os_clk;
input [ 3:0] adc_rx_os_sof;
input [ 63:0] adc_rx_os_data;
output [ 63:0] adc_data;
output adc_os_valid;
output [ 63:0] adc_os_data;
// transmit
input dac_clk;
output [127:0] dac_tx_data;
input [127:0] dac_data;
// internal signals

102
library/axi_ad9371/axi_ad9371_rx.v
View File

@ -37,93 +37,53 @@
`timescale 1ns/100ps
module axi_ad9371_rx (
module axi_ad9371_rx #(
parameter DATAPATH_DISABLE = 0,
parameter ID = 0) (
// adc interface
adc_rst,
adc_clk,
adc_data,
output adc_rst,
input adc_clk,
input [ 63:0] adc_data,
// dma interface
adc_enable_i0,
adc_valid_i0,
adc_data_i0,
adc_enable_q0,
adc_valid_q0,
adc_data_q0,
adc_enable_i1,
adc_valid_i1,
adc_data_i1,
adc_enable_q1,
adc_valid_q1,
adc_data_q1,
adc_dovf,
adc_dunf,
output adc_enable_i0,
output adc_valid_i0,
output [ 15:0] adc_data_i0,
output adc_enable_q0,
output adc_valid_q0,
output [ 15:0] adc_data_q0,
output adc_enable_i1,
output adc_valid_i1,
output [ 15:0] adc_data_i1,
output adc_enable_q1,
output adc_valid_q1,
output [ 15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
// parameters
parameter DATAPATH_DISABLE = 0;
parameter ID = 0;
// adc interface
output adc_rst;
input adc_clk;
input [ 63:0] adc_data;
// dma interface
output adc_enable_i0;
output adc_valid_i0;
output [ 15:0] adc_data_i0;
output adc_enable_q0;
output adc_valid_q0;
output [ 15:0] adc_data_q0;
output adc_enable_i1;
output adc_valid_i1;
output [ 15:0] adc_data_i1;
output adc_enable_q1;
output adc_valid_q1;
output [ 15:0] adc_data_q1;
input adc_dovf;
input adc_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [ 31:0] up_rdata = 'd0;
// internal signals

90
library/axi_ad9371/axi_ad9371_rx_channel.v
View File

@ -37,80 +37,48 @@
`timescale 1ns/100ps
module axi_ad9371_rx_channel (
module axi_ad9371_rx_channel #(
parameter Q_OR_I_N = 0,
parameter COMMON_ID = 0,
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0,
parameter DATA_WIDTH = 32) (
// adc interface
adc_clk,
adc_rst,
adc_valid_in,
adc_data_in,
adc_valid_out,
adc_data_out,
adc_data_iq_in,
adc_data_iq_out,
adc_enable,
input adc_clk,
input adc_rst,
input adc_valid_in,
input [(DATA_WIDTH-1):0] adc_data_in,
output adc_valid_out,
output [(DATA_WIDTH-1):0] adc_data_out,
input [(DATA_WIDTH-1):0] adc_data_iq_in,
output [(DATA_WIDTH-1):0] adc_data_iq_out,
output adc_enable,
// channel interface
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter Q_OR_I_N = 0;
parameter COMMON_ID = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
parameter DATA_WIDTH = 32;
localparam NUM_OF_SAMPLES = DATA_WIDTH/16;
// adc interface
input adc_clk;
input adc_rst;
input adc_valid_in;
input [(DATA_WIDTH-1):0] adc_data_in;
output adc_valid_out;
output [(DATA_WIDTH-1):0] adc_data_out;
input [(DATA_WIDTH-1):0] adc_data_iq_in;
output [(DATA_WIDTH-1):0] adc_data_iq_out;
output adc_enable;
// channel interface
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire [(NUM_OF_SAMPLES-1):0] adc_dfmt_valid_s;

87
library/axi_ad9371/axi_ad9371_rx_os.v
View File

@ -37,83 +37,48 @@
`timescale 1ns/100ps
module axi_ad9371_rx_os (
module axi_ad9371_rx_os #(
parameter DATAPATH_DISABLE = 0,
parameter ID = 0) (
// adc interface
adc_os_rst,
adc_os_clk,
adc_os_valid,
adc_os_data,
output adc_os_rst,
input adc_os_clk,
input adc_os_valid,
input [ 63:0] adc_os_data,
// dma interface
adc_os_enable_i0,
adc_os_valid_i0,
adc_os_data_i0,
adc_os_enable_q0,
adc_os_valid_q0,
adc_os_data_q0,
adc_os_dovf,
adc_os_dunf,
output adc_os_enable_i0,
output adc_os_valid_i0,
output [ 31:0] adc_os_data_i0,
output adc_os_enable_q0,
output adc_os_valid_q0,
output [ 31:0] adc_os_data_q0,
input adc_os_dovf,
input adc_os_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
// parameters
parameter DATAPATH_DISABLE = 0;
parameter ID = 0;
// adc interface
output adc_os_rst;
input adc_os_clk;
input adc_os_valid;
input [ 63:0] adc_os_data;
// dma interface
output adc_os_enable_i0;
output adc_os_valid_i0;
output [ 31:0] adc_os_data_i0;
output adc_os_enable_q0;
output adc_os_valid_q0;
output [ 31:0] adc_os_data_q0;
input adc_os_dovf;
input adc_os_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [ 31:0] up_rdata = 'd0;
// internal signals

109
library/axi_ad9371/axi_ad9371_tx.v
View File

@ -37,101 +37,58 @@
`timescale 1ns/100ps
module axi_ad9371_tx (
module axi_ad9371_tx #(
parameter DATAPATH_DISABLE = 0,
parameter ID = 0) (
// dac interface
dac_rst,
dac_clk,
dac_data,
output dac_rst,
input dac_clk,
output [127:0] dac_data,
// master/slave
dac_sync_in,
dac_sync_out,
input dac_sync_in,
output dac_sync_out,
// dma interface
dac_enable_i0,
dac_valid_i0,
dac_data_i0,
dac_enable_q0,
dac_valid_q0,
dac_data_q0,
dac_enable_i1,
dac_valid_i1,
dac_data_i1,
dac_enable_q1,
dac_valid_q1,
dac_data_q1,
dac_dovf,
dac_dunf,
output dac_enable_i0,
output dac_valid_i0,
input [ 31:0] dac_data_i0,
output dac_enable_q0,
output dac_valid_q0,
input [ 31:0] dac_data_q0,
output dac_enable_i1,
output dac_valid_i1,
input [ 31:0] dac_data_i1,
output dac_enable_q1,
output dac_valid_q1,
input [ 31:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
// parameters
parameter DATAPATH_DISABLE = 0;
parameter ID = 0;
// dac interface
output dac_rst;
input dac_clk;
output [127:0] dac_data;
// master/slave
input dac_sync_in;
output dac_sync_out;
// dma interface
output dac_enable_i0;
output dac_valid_i0;
input [ 31:0] dac_data_i0;
output dac_enable_q0;
output dac_valid_q0;
input [ 31:0] dac_data_q0;
output dac_enable_i1;
output dac_valid_i1;
input [ 31:0] dac_data_i1;
output dac_enable_q1;
output dac_valid_q1;
input [ 31:0] dac_data_q1;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg dac_data_sync = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [ 31:0] up_rdata = 'd0;
// internal signals

79
library/axi_ad9371/axi_ad9371_tx_channel.v
View File

@ -37,74 +37,43 @@
`timescale 1ns/100ps
module axi_ad9371_tx_channel (
module axi_ad9371_tx_channel #(
parameter CHANNEL_ID = 32'h0,
parameter Q_OR_I_N = 0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_clk,
dac_rst,
dac_data_in,
dac_data_out,
dac_data_iq_in,
dac_data_iq_out,
input dac_clk,
input dac_rst,
input [31:0] dac_data_in,
output [31:0] dac_data_out,
input [31:0] dac_data_iq_in,
output reg [31:0] dac_data_iq_out,
// processor interface
dac_enable,
dac_data_sync,
dac_dds_format,
output reg dac_enable,
input dac_data_sync,
input dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 32'h0;
parameter Q_OR_I_N = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
input [31:0] dac_data_in;
output [31:0] dac_data_out;
input [31:0] dac_data_iq_in;
output [31:0] dac_data_iq_out;
// processor interface
output dac_enable;
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [31:0] dac_data_iq_out = 'd0;
reg [31:0] dac_pat_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;

120
library/axi_ad9434/axi_ad9434.v
View File

@ -40,99 +40,56 @@
`timescale 1ns/100ps
module axi_ad9434 (
module axi_ad9434 #(
parameter ID = 0,
parameter DEVICE_TYPE = SERIES7,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [11:0] adc_data_in_p,
input [11:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// delay interface
delay_clk,
input delay_clk,
// dma interface
adc_clk,
adc_enable,
adc_valid,
adc_data,
adc_dovf,
output adc_clk,
output adc_enable,
output adc_valid,
output [63:0] adc_data,
input adc_dovf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// parameters
localparam SERIES7 = 0;
localparam SERIES6 = 1;
parameter ID = 0;
parameter DEVICE_TYPE = SERIES7;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid;
output adc_enable;
output [63:0] adc_data;
input adc_dovf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
// internal clocks & resets
wire adc_rst;
@ -163,7 +120,6 @@ module axi_ad9434 (
wire delay_rst;
wire delay_locked_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;

116
library/axi_ad9434/axi_ad9434_core.v
View File

@ -40,108 +40,62 @@
`timescale 1ns/100ps
module axi_ad9434_core (
module axi_ad9434_core #(
parameter ID = 0) (
// device interface
adc_clk,
adc_data,
adc_or,
input adc_clk,
input [47:0] adc_data,
input adc_or,
// dma interface
dma_dvalid,
dma_data,
dma_dovf,
output dma_dvalid,
output [63:0] dma_data,
input dma_dovf,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
output up_drp_sel,
output up_drp_wr,
output [11:0] up_drp_addr,
output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata,
input up_drp_ready,
input up_drp_locked,
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked,
output [12:0] up_dld,
output [64:0] up_dwdata,
input [64:0] up_drdata,
input delay_clk,
output delay_rst,
input delay_locked,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack,
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack,
// status and control signals
mmcm_rst,
adc_rst,
adc_status);
output mmcm_rst,
output adc_rst,
input adc_status);
// parameters
parameter ID = 0;
// device interface
input adc_clk;
input [47:0] adc_data;
input adc_or;
// dma interface
output dma_dvalid;
output [63:0] dma_data;
input dma_dovf;
// drp interface
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [31:0] up_drp_wdata;
input [31:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// delay interface
output [12:0] up_dld;
output [64:0] up_dwdata;
input [64:0] up_drdata;
input delay_clk;
output delay_rst;
input delay_locked;
// processor interface
input up_clk;
input up_rstn;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
output mmcm_rst;
output adc_rst;
input adc_status;
// internal registers
reg up_wack;
reg [31:0] up_rdata;
reg up_rack;
// internal signals
wire up_status_pn_err_s;

105
library/axi_ad9434/axi_ad9434_if.v
View File

@ -40,98 +40,55 @@
`timescale 1ns/100ps
module axi_ad9434_if (
module axi_ad9434_if #(
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// device interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [11:0] adc_data_in_p,
input [11:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// interface outputs
adc_data,
adc_or,
output [47:0] adc_data,
output adc_or,
// internl reset and clocks
adc_clk,
adc_rst,
adc_status,
output adc_clk,
input adc_rst,
output reg adc_status,
// delay interface (for IDELAY macros)
up_clk,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
delay_clk,
delay_rst,
delay_locked,
input up_clk,
input [12:0] up_adc_dld,
input [64:0] up_adc_dwdata,
output [64:0] up_adc_drdata,
input delay_clk,
input delay_rst,
output delay_locked,
// mmcm reset
mmcm_rst,
input mmcm_rst,
// drp interface for MMCM_OR_BUFR_N
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// parameters
parameter DEVICE_TYPE = 0; // 0 - 7Series / 1 - 6Series
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// buffer type based on the target device.
localparam SDR = 0;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output [47:0] adc_data;
output adc_or;
// internal reset and clocks
output adc_clk;
input adc_rst;
output adc_status;
// delay interface
input up_clk;
input [12:0] up_adc_dld;
input [64:0] up_adc_dwdata;
output [64:0] up_adc_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// mmcm reset
input mmcm_rst;
// drp interface
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [31:0] up_drp_wdata;
output [31:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg adc_status = 'd0;
reg adc_status_m1 = 'd0;
// internal signals

19
library/axi_ad9434/axi_ad9434_pnmon.v
View File

@ -43,22 +43,13 @@
module axi_ad9434_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [47:0] adc_data,
// pn interface
adc_pnseq_sel,
adc_pn_err,
adc_pn_oos);
// adc interface
input adc_clk;
input [47:0] adc_data;
// pn out sync and error
input [ 3:0] adc_pnseq_sel;
output adc_pn_err;
output adc_pn_oos;
input [ 3:0] adc_pnseq_sel,
output adc_pn_err,
output adc_pn_oos);
// internal registers
reg [47:0] adc_pn_data_pn = 'd0;

126
library/axi_ad9467/axi_ad9467.v
View File

@ -39,105 +39,57 @@
`timescale 1ns/100ps
module axi_ad9467(
module axi_ad9467#(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [ 7:0] adc_data_in_p,
input [ 7:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// delay_clock
delay_clk,
input delay_clk,
// dma interface
adc_clk,
adc_valid,
adc_enable,
adc_data,
adc_dovf,
adc_dunf,
output adc_clk,
output adc_valid,
output adc_enable,
output [15:0] adc_data,
input adc_dovf,
input adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay clk
input delay_clk;
// dma interface
output adc_clk;
output adc_valid;
output adc_enable;
output [15:0] adc_data;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
// internal registers

73
library/axi_ad9467/axi_ad9467_channel.v
View File

@ -37,67 +37,38 @@
`timescale 1ns/100ps
module axi_ad9467_channel(
module axi_ad9467_channel#(
parameter CHANNEL_ID = 0) (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input [15:0] adc_data,
input adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [15:0] adc_dfmt_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [15:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

74
library/axi_ad9467/axi_ad9467_if.v
View File

@ -41,70 +41,40 @@
`timescale 1ns/100ps
module axi_ad9467_if (
module axi_ad9467_if #(
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [ 7:0] adc_data_in_p,
input [ 7:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// interface outputs
adc_clk,
adc_data,
adc_or,
output adc_clk,
output reg [15:0] adc_data,
output reg adc_or,
// processor interface
adc_ddr_edgesel,
input adc_ddr_edgesel,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
input up_clk,
input [ 8:0] up_dld,
input [44:0] up_dwdata,
output [44:0] up_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
// buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data;
output adc_or;
// processor interface
input adc_ddr_edgesel;
// delay control signals
input up_clk;
input [ 8:0] up_dld;
input [44:0] up_dwdata;
output [44:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
@ -113,10 +83,8 @@ module axi_ad9467_if (
reg [ 7:0] adc_data_p_d = 'd0;
reg [ 7:0] adc_dmux_a = 'd0;
reg [ 7:0] adc_dmux_b = 'd0;
reg [15:0] adc_data = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or = 'd0;
// internal signals

21
library/axi_ad9467/axi_ad9467_pnmon.v
View File

@ -44,25 +44,14 @@ module axi_ad9467_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [15:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
output adc_pn_oos,
output adc_pn_err,
input [ 3:0] adc_pnseq_sel);
// internal registers

128
library/axi_ad9625/axi_ad9625.v
View File

@ -37,103 +37,57 @@
`timescale 1ns/100ps
module axi_ad9625 (
module axi_ad9625 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_valid,
rx_data,
rx_ready,
input rx_clk,
input [ 3:0] rx_sof,
input rx_valid,
input [255:0] rx_data,
output rx_ready,
// dma interface
adc_clk,
adc_rst,
adc_valid,
adc_enable,
adc_data,
adc_dovf,
adc_dunf,
adc_sref,
adc_raddr_in,
adc_raddr_out,
output adc_clk,
output adc_rst,
output adc_valid,
output adc_enable,
output [255:0] adc_data,
input adc_dovf,
input adc_dunf,
output [ 15:0] adc_sref,
input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input rx_valid;
input [255:0] rx_data;
output rx_ready;
// dma interface
output adc_clk;
output adc_rst;
output adc_valid;
output adc_enable;
output [255:0] adc_data;
input adc_dovf;
input adc_dunf;
output [ 15:0] adc_sref;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [ 31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [ 31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal registers

66
library/axi_ad9625/axi_ad9625_channel.v
View File

@ -44,59 +44,31 @@ module axi_ad9625_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input [191:0] adc_data,
input adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [255:0] adc_dfmt_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// adc interface
input adc_clk;
input adc_rst;
input [191:0] adc_data;
input adc_or;
// channel interface
output [255:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// internal signals

53
library/axi_ad9625/axi_ad9625_if.v
View File

@ -37,59 +37,36 @@
`timescale 1ns/100ps
module axi_ad9625_if (
module axi_ad9625_if #(
parameter ID = 0,
parameter DEVICE_TYPE = 0) (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_data,
input rx_clk,
input [ 3:0] rx_sof,
input [255:0] rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data,
adc_or,
adc_status,
adc_sref,
adc_raddr_in,
adc_raddr_out);
output adc_clk,
input adc_rst,
output reg [191:0] adc_data,
output adc_or,
output reg adc_status,
output reg [ 15:0] adc_sref,
input [ 3:0] adc_raddr_in,
output reg [ 3:0] adc_raddr_out);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
// jesd interface
// rx_clk is ref_clk/4
input rx_clk;
input [ 3:0] rx_sof;
input [255:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [191:0] adc_data;
output adc_or;
output adc_status;
output [ 15:0] adc_sref;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// internal registers
reg [191:0] adc_data = 'd0;
reg [ 15:0] adc_sref = 'd0;
reg [191:0] adc_data_cur = 'd0;
reg [191:0] adc_data_prv = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [ 3:0] adc_raddr_out = 'd0;
reg [191:0] adc_wdata = 'd0;
reg adc_status = 'd0;
// internal signals

24
library/axi_ad9625/axi_ad9625_pnmon.v
View File

@ -44,31 +44,17 @@ module axi_ad9625_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [191:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
output adc_pn_oos,
output adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pnseq_sel);
// adc interface
input adc_clk;
input [191:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
input [ 3:0] adc_pnseq_sel);
// internal registers

146
library/axi_ad9643/axi_ad9643.v
View File

@ -37,118 +37,64 @@
`timescale 1ns/100ps
module axi_ad9643 (
module axi_ad9643 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter ADC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [13:0] adc_data_in_p,
input [13:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// delay interface
delay_clk,
input delay_clk,
// dma interface
adc_clk,
adc_valid_0,
adc_enable_0,
adc_data_0,
adc_valid_1,
adc_enable_1,
adc_data_1,
adc_dovf,
adc_dunf,
up_adc_gpio_in,
up_adc_gpio_out,
adc_rst,
output adc_clk,
output adc_valid_0,
output adc_enable_0,
output [15:0] adc_data_0,
output adc_valid_1,
output adc_enable_1,
output [15:0] adc_data_1,
input adc_dovf,
input adc_dunf,
input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out,
output adc_rst,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid_0;
output adc_enable_0;
output [15:0] adc_data_0;
output adc_valid_1;
output adc_enable_1;
output [15:0] adc_data_1;
input adc_dovf;
input adc_dunf;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
output adc_rst;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal registers

83
library/axi_ad9643/axi_ad9643_channel.v
View File

@ -38,73 +38,42 @@
`timescale 1ns/100ps
module axi_ad9643_channel (
module axi_ad9643_channel #(
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input [13:0] adc_data,
input adc_or,
// channel interface
adc_dcfilter_data_out,
adc_dcfilter_data_in,
adc_iqcor_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [15:0] adc_dcfilter_data_out,
input [15:0] adc_dcfilter_data_in,
output [15:0] adc_iqcor_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [13:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dcfilter_data_out;
input [15:0] adc_dcfilter_data_in;
output [15:0] adc_iqcor_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

89
library/axi_ad9643/axi_ad9643_if.v
View File

@ -42,82 +42,47 @@
`timescale 1ns/100ps
module axi_ad9643_if (
module axi_ad9643_if #(
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [13:0] adc_data_in_p,
input [13:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// interface outputs
adc_clk,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status,
output adc_clk,
output reg [13:0] adc_data_a,
output reg [13:0] adc_data_b,
output reg adc_or_a,
output reg adc_or_b,
output reg adc_status,
// processor control signals
adc_ddr_edgesel,
adc_pin_mode,
input adc_ddr_edgesel,
input adc_pin_mode,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
input up_clk,
input [14:0] up_dld,
input [74:0] up_dwdata,
output [74:0] up_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
// This parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [13:0] adc_data_a;
output [13:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// processor control signals
input adc_ddr_edgesel;
input adc_pin_mode;
// delay control signals
input up_clk;
input [14:0] up_dld;
input [74:0] up_dwdata;
output [74:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [13:0] adc_data_p = 'd0;
reg [13:0] adc_data_n = 'd0;
reg [13:0] adc_data_p_d = 'd0;
@ -128,10 +93,6 @@ module axi_ad9643_if (
reg [13:0] adc_data_mux_b = 'd0;
reg adc_or_mux_a = 'd0;
reg adc_or_mux_b = 'd0;
reg [13:0] adc_data_a = 'd0;
reg [13:0] adc_data_b = 'd0;
reg adc_or_a = 'd0;
reg adc_or_b = 'd0;
// internal signals

21
library/axi_ad9643/axi_ad9643_pnmon.v
View File

@ -44,25 +44,14 @@ module axi_ad9643_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [13:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input [13:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
output adc_pn_oos,
output adc_pn_err,
input [ 3:0] adc_pnseq_sel);
// internal registers

146
library/axi_ad9652/axi_ad9652.v
View File

@ -37,118 +37,64 @@
`timescale 1ns/100ps
module axi_ad9652 (
module axi_ad9652 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter ADC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [15:0] adc_data_in_p,
input [15:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// delay interface
delay_clk,
input delay_clk,
// dma interface
adc_clk,
adc_rst,
adc_valid_0,
adc_enable_0,
adc_data_0,
adc_valid_1,
adc_enable_1,
adc_data_1,
adc_dovf,
adc_dunf,
up_adc_gpio_in,
up_adc_gpio_out,
output adc_clk,
output adc_rst,
output adc_valid_0,
output adc_enable_0,
output [15:0] adc_data_0,
output adc_valid_1,
output adc_enable_1,
output [15:0] adc_data_1,
input adc_dovf,
input adc_dunf,
input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [15:0] adc_data_in_p;
input [15:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_rst;
output adc_valid_0;
output adc_enable_0;
output [15:0] adc_data_0;
output adc_valid_1;
output adc_enable_1;
output [15:0] adc_data_1;
input adc_dovf;
input adc_dunf;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal registers

83
library/axi_ad9652/axi_ad9652_channel.v
View File

@ -40,73 +40,42 @@
`timescale 1ns/100ps
module axi_ad9652_channel (
module axi_ad9652_channel #(
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input [15:0] adc_data,
input adc_or,
// channel interface
adc_dcfilter_data_out,
adc_dcfilter_data_in,
adc_iqcor_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [15:0] adc_dcfilter_data_out,
input [15:0] adc_dcfilter_data_in,
output [15:0] adc_iqcor_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [15:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dcfilter_data_out;
input [15:0] adc_dcfilter_data_in;
output [15:0] adc_iqcor_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

87
library/axi_ad9652/axi_ad9652_if.v
View File

@ -42,90 +42,52 @@
`timescale 1ns/100ps
module axi_ad9652_if (
module axi_ad9652_if #(
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [15:0] adc_data_in_p,
input [15:0] adc_data_in_n,
input adc_or_in_p,
input adc_or_in_n,
// interface outputs
adc_clk,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status,
output adc_clk,
output reg [15:0] adc_data_a,
output reg [15:0] adc_data_b,
output reg adc_or_a,
output reg adc_or_b,
output reg adc_status,
// processor control signals
adc_ddr_edgesel,
input adc_ddr_edgesel,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
input up_clk,
input [16:0] up_dld,
input [84:0] up_dwdata,
output [84:0] up_drdata,
input delay_clk,
input delay_rst,
output delay_locked);
// This parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [15:0] adc_data_in_p;
input [15:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data_a;
output [15:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// processor control signals
input adc_ddr_edgesel;
// delay control signals
input up_clk;
input [16:0] up_dld;
input [84:0] up_dwdata;
output [84:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [15:0] adc_data_p = 'd0;
reg [15:0] adc_data_n = 'd0;
reg [15:0] adc_data_p_d = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or_p_d = 'd0;
reg [15:0] adc_data_a = 'd0;
reg [15:0] adc_data_b = 'd0;
reg adc_or_a = 'd0;
reg adc_or_b = 'd0;
// internal signals
@ -164,7 +126,6 @@ module axi_ad9652_if (
end
end
// data interface
generate

21
library/axi_ad9652/axi_ad9652_pnmon.v
View File

@ -44,25 +44,14 @@ module axi_ad9652_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [15:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
output adc_pn_oos,
output adc_pn_err,
input [ 3:0] adc_pnseq_sel);
// internal registers

127
library/axi_ad9671/axi_ad9671.v
View File

@ -37,103 +37,58 @@
`timescale 1ns/100ps
module axi_ad9671 (
module axi_ad9671 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter QUAD_OR_DUAL_N = 1) (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_valid,
rx_data,
rx_ready,
input rx_clk,
input [ 3:0] rx_sof,
input rx_valid,
input [(64*QUAD_OR_DUAL_N)+63:0] rx_data,
output rx_ready,
// dma interface
adc_clk,
adc_valid,
adc_enable,
adc_data,
adc_dovf,
adc_dunf,
adc_sync_in,
adc_sync_out,
adc_raddr_in,
adc_raddr_out,
output adc_clk,
output [ 7:0] adc_valid,
output [ 7:0] adc_enable,
output [127:0] adc_data,
input adc_dovf,
input adc_dunf,
input adc_sync_in,
output adc_sync_out,
input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [ 31:0] s_axi_rdata,
input s_axi_rready);
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter QUAD_OR_DUAL_N = 1;
// jesd interface
// rx_clk is the jesd clock (ref_clk/2)
input rx_clk;
input [ 3:0] rx_sof;
input rx_valid;
input [(64*QUAD_OR_DUAL_N)+63:0] rx_data;
output rx_ready;
// dma interface
output adc_clk;
output [ 7:0] adc_valid;
output [ 7:0] adc_enable;
output [127:0] adc_data;
input adc_dovf;
input adc_dunf;
input adc_sync_in;
output adc_sync_out;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [ 31:0] s_axi_rdata;
input s_axi_rready;
// internal registers

79
library/axi_ad9671/axi_ad9671_channel.v
View File

@ -40,71 +40,40 @@
`timescale 1ns/100ps
module axi_ad9671_channel (
module axi_ad9671_channel #(
parameter CHANNEL_ID = 0) (
// adc interface
adc_clk,
adc_rst,
adc_valid,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input adc_valid,
input [15:0] adc_data,
input adc_or,
// channel interface
adc_dfmt_valid,
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output adc_dfmt_valid,
output [15:0] adc_dfmt_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 0;
// adc interface
input adc_clk;
input adc_rst;
input adc_valid;
input [15:0] adc_data;
input adc_or;
// channel interface
output adc_dfmt_valid;
output [15:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

119
library/axi_ad9671/axi_ad9671_if.v
View File

@ -37,87 +37,49 @@
`timescale 1ns/100ps
module axi_ad9671_if (
module axi_ad9671_if #(
parameter QUAD_OR_DUAL_N = 1,
parameter DEVICE_TYPE = 0,
parameter ID = 0) (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_data,
input rx_clk,
input [ 3:0] rx_sof,
input [(64*QUAD_OR_DUAL_N)+63:0] rx_data,
// adc data output
adc_clk,
adc_rst,
adc_valid,
adc_data_a,
adc_or_a,
adc_data_b,
adc_or_b,
adc_data_c,
adc_or_c,
adc_data_d,
adc_or_d,
adc_data_e,
adc_or_e,
adc_data_f,
adc_or_f,
adc_data_g,
adc_or_g,
adc_data_h,
adc_or_h,
adc_start_code,
adc_sync_in,
adc_sync_out,
adc_sync,
adc_sync_status,
adc_status,
adc_raddr_in,
adc_raddr_out);
output adc_clk,
input adc_rst,
output adc_valid,
output reg [ 15:0] adc_data_a,
output adc_or_a,
output reg [ 15:0] adc_data_b,
output adc_or_b,
output reg [ 15:0] adc_data_c,
output adc_or_c,
output reg [ 15:0] adc_data_d,
output adc_or_d,
output reg [ 15:0] adc_data_e,
output adc_or_e,
output reg [ 15:0] adc_data_f,
output adc_or_f,
output reg [ 15:0] adc_data_g,
output adc_or_g,
output reg [ 15:0] adc_data_h,
output adc_or_h,
input [ 31:0] adc_start_code,
input adc_sync_in,
output adc_sync_out,
input adc_sync,
output reg adc_sync_status,
output reg adc_status,
input [ 3:0] adc_raddr_in,
output reg [ 3:0] adc_raddr_out);
// parameters
parameter QUAD_OR_DUAL_N = 1;
parameter DEVICE_TYPE = 0;
parameter ID = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input [(64*QUAD_OR_DUAL_N)+63:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output adc_valid;
output [ 15:0] adc_data_a;
output adc_or_a;
output [ 15:0] adc_data_b;
output adc_or_b;
output [ 15:0] adc_data_c;
output adc_or_c;
output [ 15:0] adc_data_d;
output adc_or_d;
output [ 15:0] adc_data_e;
output adc_or_e;
output [ 15:0] adc_data_f;
output adc_or_f;
output [ 15:0] adc_data_g;
output adc_or_g;
output [ 15:0] adc_data_h;
output adc_or_h;
input [ 31:0] adc_start_code;
input adc_sync_in;
output adc_sync_out;
input adc_sync;
output adc_sync_status;
output adc_status;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// internal wires
@ -140,19 +102,8 @@ module axi_ad9671_if (
reg int_valid = 'd0;
reg [127:0] int_data = 'd0;
reg adc_status = 'd0;
reg adc_sync_status = 'd0;
reg rx_sof_d = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [ 3:0] adc_raddr_out = 'd0;
reg [ 15:0] adc_data_a = 'd0;
reg [ 15:0] adc_data_b = 'd0;
reg [ 15:0] adc_data_c = 'd0;
reg [ 15:0] adc_data_d = 'd0;
reg [ 15:0] adc_data_e = 'd0;
reg [ 15:0] adc_data_f = 'd0;
reg [ 15:0] adc_data_g = 'd0;
reg [ 15:0] adc_data_h = 'd0;
// adc clock & valid

24
library/axi_ad9671/axi_ad9671_pnmon.v
View File

@ -44,27 +44,15 @@ module axi_ad9671_pnmon (
// adc interface
adc_clk,
adc_valid,
adc_data,
input adc_clk,
input adc_valid,
input [15:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input adc_valid;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
output adc_pn_oos,
output adc_pn_err,
input [ 3:0] adc_pnseq_sel);
// internal registers

124
library/axi_ad9680/axi_ad9680.v
View File

@ -37,101 +37,57 @@
`timescale 1ns/100ps
module axi_ad9680 (
module axi_ad9680 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group") (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_valid,
rx_data,
rx_ready,
input rx_clk,
input [ 3:0] rx_sof,
input rx_valid,
input [127:0] rx_data,
output rx_ready,
// dma interface
adc_clk,
adc_enable_0,
adc_valid_0,
adc_data_0,
adc_enable_1,
adc_valid_1,
adc_data_1,
adc_dovf,
adc_dunf,
output adc_clk,
output adc_enable_0,
output adc_valid_0,
output [63:0] adc_data_0,
output adc_enable_1,
output adc_valid_1,
output [63:0] adc_data_1,
input adc_dovf,
input adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input rx_valid;
input [127:0] rx_data;
output rx_ready;
// dma interface
output adc_clk;
output adc_enable_0;
output adc_valid_0;
output [63:0] adc_data_0;
output adc_enable_1;
output adc_valid_1;
output [63:0] adc_data_1;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers

73
library/axi_ad9680/axi_ad9680_channel.v
View File

@ -40,67 +40,38 @@
`timescale 1ns/100ps
module axi_ad9680_channel (
module axi_ad9680_channel #(
parameter CHANNEL_ID = 0) (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
input adc_clk,
input adc_rst,
input [55:0] adc_data,
input adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [63:0] adc_dfmt_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [55:0] adc_data;
input adc_or;
// channel interface
output [63:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

46
library/axi_ad9680/axi_ad9680_if.v
View File

@ -37,50 +37,30 @@
`timescale 1ns/100ps
module axi_ad9680_if (
module axi_ad9680_if #(
parameter DEVICE_TYPE = 0) (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_data,
input rx_clk,
input [ 3:0] rx_sof,
input [127:0] rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status);
output adc_clk,
input adc_rst,
output [55:0] adc_data_a,
output [55:0] adc_data_b,
output adc_or_a,
output adc_or_b,
output reg adc_status);
// parameters
parameter DEVICE_TYPE = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input [127:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [55:0] adc_data_a;
output [55:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s3_s;

24
library/axi_ad9680/axi_ad9680_pnmon.v
View File

@ -44,31 +44,17 @@ module axi_ad9680_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [55:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
output adc_pn_oos,
output adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pnseq_sel);
// adc interface
input adc_clk;
input [55:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
input [ 3:0] adc_pnseq_sel);
// internal registers

135
library/axi_ad9684/axi_ad9684.v
View File

@ -40,109 +40,62 @@
`timescale 1ns/100ps
module axi_ad9684 (
module axi_ad9684 #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter OR_STATUS = 1) (
// device interface ports
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [13:0] adc_data_in_p,
input [13:0] adc_data_in_n,
input adc_data_or_p,
input adc_data_or_n,
// dma interface ports
adc_clk,
adc_rst,
adc_valid_0,
adc_enable_0,
adc_data_0,
adc_valid_1,
adc_enable_1,
adc_data_1,
adc_dovf,
adc_dunf,
output adc_clk,
output adc_rst,
output adc_valid_0,
output adc_enable_0,
output [31:0] adc_data_0,
output adc_valid_1,
output adc_enable_1,
output [31:0] adc_data_1,
input adc_dovf,
input adc_dunf,
// delay clock ports
delay_clk,
input delay_clk,
// axi slave interface ports
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready
);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
parameter OR_STATUS = 1;
// IO definitions
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
output adc_clk;
output adc_rst;
output adc_valid_0;
output adc_enable_0;
output [31:0] adc_data_0;
output adc_valid_1;
output adc_enable_1;
output [31:0] adc_data_1;
input adc_dovf;
input adc_dunf;
input delay_clk;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
// internal registers

80
library/axi_ad9684/axi_ad9684_channel.v
View File

@ -40,70 +40,42 @@
`timescale 1ns/100ps
module axi_ad9684_channel (
module axi_ad9684_channel #(
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0) (
// adc data interface
adc_clk,
adc_rst,
adc_data,
adc_data_q,
adc_or,
input adc_clk,
input adc_rst,
input [27:0] adc_data,
input [27:0] adc_data_q,
input adc_or,
// channel interface
adc_dfmt_data,
adc_valid,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
output [31:0] adc_dfmt_data,
output adc_valid,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// up interface
up_clk,
up_rstn,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack
);
input up_clk,
input up_rstn,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
// IO definitions
input adc_clk;
input adc_rst;
input [27:0] adc_data;
input [27:0] adc_data_q;
input adc_or;
output [31:0] adc_dfmt_data;
output adc_enable;
output adc_valid;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
input up_clk;
input up_rstn;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals

108
library/axi_ad9684/axi_ad9684_if.v
View File

@ -40,95 +40,56 @@
`timescale 1ns/100ps
module axi_ad9684_if (
module axi_ad9684_if #(
parameter DEVICE_TYPE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter OR_STATUS = 0) (
// device interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [13:0] adc_data_in_p,
input [13:0] adc_data_in_n,
input adc_data_or_p,
input adc_data_or_n,
// data interface
adc_clk,
adc_rst,
adc_data_a,
adc_or_a,
adc_data_b,
adc_or_b,
adc_status,
output adc_clk,
input adc_rst,
output [27:0] adc_data_a,
output adc_or_a,
output [27:0] adc_data_b,
output adc_or_b,
output reg adc_status,
// delay interface
delay_clk,
delay_rst,
delay_dload,
delay_wdata,
delay_rdata,
delay_locked,
input delay_clk,
input delay_rst,
input [14:0] delay_dload,
input [74:0] delay_wdata,
output [74:0] delay_rdata,
output delay_locked,
// reset
rst,
input rst,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked
);
input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// parameters
parameter DEVICE_TYPE = 0; // 0 - 7Series / 1 - 6Series
parameter IO_DELAY_GROUP = "dev_if_delay_group";
parameter OR_STATUS = 0;
// buffer type based on the target device
localparam DDR_OR_SDR_N = 1;
// IO definitions
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
output adc_clk;
input adc_rst;
output [27:0] adc_data_a;
output adc_or_a;
output [27:0] adc_data_b;
output adc_or_b;
output adc_status;
input delay_clk;
input delay_rst;
input [14:0] delay_dload;
input [74:0] delay_wdata;
output [74:0] delay_rdata;
output delay_locked;
input rst;
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [31:0] up_drp_wdata;
output [31:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg adc_status = 'd0;
reg adc_status_m1 = 'd0;
// internal signals
@ -140,7 +101,6 @@ module axi_ad9684_if (
wire loaden_s;
wire [ 7:0] phase_s;
genvar l_inst;
// adc_clk is 1:2 of the sampling clock

24
library/axi_ad9684/axi_ad9684_pnmon.v
View File

@ -44,31 +44,17 @@ module axi_ad9684_pnmon (
// adc interface
adc_clk,
adc_data,
input adc_clk,
input [27:0] adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
output adc_pn_oos,
output adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pnseq_sel);
// adc interface
input adc_clk;
input [27:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
input [ 3:0] adc_pnseq_sel);
// internal registers

132
library/axi_ad9739a/axi_ad9739a.v
View File

@ -39,104 +39,58 @@
`timescale 1ns/100ps
module axi_ad9739a (
module axi_ad9739a #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter SERDES_OR_DDR_N = 1,
parameter MMCM_OR_BUFIO_N = 1,
parameter DAC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
input dac_clk_in_p,
input dac_clk_in_n,
output dac_clk_out_p,
output dac_clk_out_n,
output [ 13:0] dac_data_out_a_p,
output [ 13:0] dac_data_out_a_n,
output [ 13:0] dac_data_out_b_p,
output [ 13:0] dac_data_out_b_n,
// dma interface
dac_div_clk,
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
output dac_div_clk,
output dac_valid,
output dac_enable,
input [255:0] dac_ddata,
input dac_dovf,
input dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFIO_N = 1;
parameter DAC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [ 13:0] dac_data_out_a_p;
output [ 13:0] dac_data_out_a_n;
output [ 13:0] dac_data_out_b_p;
output [ 13:0] dac_data_out_b_n;
// dma interface
output dac_div_clk;
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal clocks and resets

131
library/axi_ad9739a/axi_ad9739a_channel.v
View File

@ -39,114 +39,55 @@
`timescale 1ns/100ps
module axi_ad9739a_channel (
module axi_ad9739a_channel #(
parameter CHANNEL_ID = 32'h0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_div_clk,
dac_rst,
dac_enable,
dac_data_00,
dac_data_01,
dac_data_02,
dac_data_03,
dac_data_04,
dac_data_05,
dac_data_06,
dac_data_07,
dac_data_08,
dac_data_09,
dac_data_10,
dac_data_11,
dac_data_12,
dac_data_13,
dac_data_14,
dac_data_15,
dma_data,
input dac_div_clk,
input dac_rst,
output reg dac_enable,
output reg [ 15:0] dac_data_00,
output reg [ 15:0] dac_data_01,
output reg [ 15:0] dac_data_02,
output reg [ 15:0] dac_data_03,
output reg [ 15:0] dac_data_04,
output reg [ 15:0] dac_data_05,
output reg [ 15:0] dac_data_06,
output reg [ 15:0] dac_data_07,
output reg [ 15:0] dac_data_08,
output reg [ 15:0] dac_data_09,
output reg [ 15:0] dac_data_10,
output reg [ 15:0] dac_data_11,
output reg [ 15:0] dac_data_12,
output reg [ 15:0] dac_data_13,
output reg [ 15:0] dac_data_14,
output reg [ 15:0] dac_data_15,
input [255:0] dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
input dac_data_sync,
input dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output [ 31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_div_clk;
input dac_rst;
output dac_enable;
output [ 15:0] dac_data_00;
output [ 15:0] dac_data_01;
output [ 15:0] dac_data_02;
output [ 15:0] dac_data_03;
output [ 15:0] dac_data_04;
output [ 15:0] dac_data_05;
output [ 15:0] dac_data_06;
output [ 15:0] dac_data_07;
output [ 15:0] dac_data_08;
output [ 15:0] dac_data_09;
output [ 15:0] dac_data_10;
output [ 15:0] dac_data_11;
output [ 15:0] dac_data_12;
output [ 15:0] dac_data_13;
output [ 15:0] dac_data_14;
output [ 15:0] dac_data_15;
input [255:0] dma_data;
// processor interface
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [ 15:0] dac_data_00 = 'd0;
reg [ 15:0] dac_data_01 = 'd0;
reg [ 15:0] dac_data_02 = 'd0;
reg [ 15:0] dac_data_03 = 'd0;
reg [ 15:0] dac_data_04 = 'd0;
reg [ 15:0] dac_data_05 = 'd0;
reg [ 15:0] dac_data_06 = 'd0;
reg [ 15:0] dac_data_07 = 'd0;
reg [ 15:0] dac_data_08 = 'd0;
reg [ 15:0] dac_data_09 = 'd0;
reg [ 15:0] dac_data_10 = 'd0;
reg [ 15:0] dac_data_11 = 'd0;
reg [ 15:0] dac_data_12 = 'd0;
reg [ 15:0] dac_data_13 = 'd0;
reg [ 15:0] dac_data_14 = 'd0;
reg [ 15:0] dac_data_15 = 'd0;
reg [ 15:0] dac_dds_phase_00_0 = 'd0;
reg [ 15:0] dac_dds_phase_00_1 = 'd0;
reg [ 15:0] dac_dds_phase_01_0 = 'd0;

124
library/axi_ad9739a/axi_ad9739a_core.v
View File

@ -39,105 +39,57 @@
`timescale 1ns/100ps
module axi_ad9739a_core (
module axi_ad9739a_core #(
parameter ID = 0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
dac_div_clk,
dac_rst,
dac_data_00,
dac_data_01,
dac_data_02,
dac_data_03,
dac_data_04,
dac_data_05,
dac_data_06,
dac_data_07,
dac_data_08,
dac_data_09,
dac_data_10,
dac_data_11,
dac_data_12,
dac_data_13,
dac_data_14,
dac_data_15,
dac_status,
input dac_div_clk,
output dac_rst,
output [ 15:0] dac_data_00,
output [ 15:0] dac_data_01,
output [ 15:0] dac_data_02,
output [ 15:0] dac_data_03,
output [ 15:0] dac_data_04,
output [ 15:0] dac_data_05,
output [ 15:0] dac_data_06,
output [ 15:0] dac_data_07,
output [ 15:0] dac_data_08,
output [ 15:0] dac_data_09,
output [ 15:0] dac_data_10,
output [ 15:0] dac_data_11,
output [ 15:0] dac_data_12,
output [ 15:0] dac_data_13,
output [ 15:0] dac_data_14,
output [ 15:0] dac_data_15,
input dac_status,
// dma interface
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
output dac_valid,
output dac_enable,
input [255:0] dac_ddata,
input dac_dovf,
input dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
// parameters
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_div_clk;
output dac_rst;
output [ 15:0] dac_data_00;
output [ 15:0] dac_data_01;
output [ 15:0] dac_data_02;
output [ 15:0] dac_data_03;
output [ 15:0] dac_data_04;
output [ 15:0] dac_data_05;
output [ 15:0] dac_data_06;
output [ 15:0] dac_data_07;
output [ 15:0] dac_data_08;
output [ 15:0] dac_data_09;
output [ 15:0] dac_data_10;
output [ 15:0] dac_data_11;
output [ 15:0] dac_data_12;
output [ 15:0] dac_data_13;
output [ 15:0] dac_data_14;
output [ 15:0] dac_data_15;
input dac_status;
// dma interface
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;

102
library/axi_ad9739a/axi_ad9739a_if.v
View File

@ -41,90 +41,50 @@
`timescale 1ns/100ps
module axi_ad9739a_if (
module axi_ad9739a_if #(
parameter DEVICE_TYPE = 0) (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
input dac_clk_in_p,
input dac_clk_in_n,
output dac_clk_out_p,
output dac_clk_out_n,
output [13:0] dac_data_out_a_p,
output [13:0] dac_data_out_a_n,
output [13:0] dac_data_out_b_p,
output [13:0] dac_data_out_b_n,
// internal resets and clocks
dac_rst,
dac_clk,
dac_div_clk,
dac_status,
input dac_rst,
output dac_clk,
output dac_div_clk,
output reg dac_status,
// data interface
dac_data_00,
dac_data_01,
dac_data_02,
dac_data_03,
dac_data_04,
dac_data_05,
dac_data_06,
dac_data_07,
dac_data_08,
dac_data_09,
dac_data_10,
dac_data_11,
dac_data_12,
dac_data_13,
dac_data_14,
dac_data_15);
input [15:0] dac_data_00,
input [15:0] dac_data_01,
input [15:0] dac_data_02,
input [15:0] dac_data_03,
input [15:0] dac_data_04,
input [15:0] dac_data_05,
input [15:0] dac_data_06,
input [15:0] dac_data_07,
input [15:0] dac_data_08,
input [15:0] dac_data_09,
input [15:0] dac_data_10,
input [15:0] dac_data_11,
input [15:0] dac_data_12,
input [15:0] dac_data_13,
input [15:0] dac_data_14,
input [15:0] dac_data_15);
// parameters
parameter DEVICE_TYPE = 0;
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
// internal resets and clocks
input dac_rst;
output dac_clk;
output dac_div_clk;
output dac_status;
// data interface
input [15:0] dac_data_00;
input [15:0] dac_data_01;
input [15:0] dac_data_02;
input [15:0] dac_data_03;
input [15:0] dac_data_04;
input [15:0] dac_data_05;
input [15:0] dac_data_06;
input [15:0] dac_data_07;
input [15:0] dac_data_08;
input [15:0] dac_data_09;
input [15:0] dac_data_10;
input [15:0] dac_data_11;
input [15:0] dac_data_12;
input [15:0] dac_data_13;
input [15:0] dac_data_14;
input [15:0] dac_data_15;
// internal registers
reg dac_status = 'd0;
// internal signals
wire dac_clk_in_s;

112
library/axi_clkgen/axi_clkgen.v
View File

@ -36,85 +36,51 @@
// ***************************************************************************
// software programmable clock generator (still needs a reference input!)
module axi_clkgen (
module axi_clkgen #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter CLKIN_PERIOD = 5.0,
parameter CLKIN2_PERIOD = 5.0,
parameter VCO_DIV = 11,
parameter VCO_MUL = 49,
parameter CLK0_DIV = 6,
parameter CLK0_PHASE = 0.000,
parameter CLK1_DIV = 6,
parameter CLK1_PHASE = 0.000,
parameter CLK2_DIV = 6,
parameter CLK2_PHASE = 0.000) (
// clocks
clk,
clk2,
clk_0,
clk_1,
input clk,
input clk2,
output clk_0,
output clk_1,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter CLKIN_PERIOD = 5.0;
parameter CLKIN2_PERIOD = 5.0;
parameter VCO_DIV = 11;
parameter VCO_MUL = 49;
parameter CLK0_DIV = 6;
parameter CLK0_PHASE = 0.000;
parameter CLK1_DIV = 6;
parameter CLK1_PHASE = 0.000;
parameter CLK2_DIV = 6;
parameter CLK2_PHASE = 0.000;
// clocks
input clk;
input clk2;
output clk_0;
output clk_1;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// reset and clocks

51
library/axi_gpreg/axi_gpreg_clock_mon.v
View File

@ -37,54 +37,33 @@
`timescale 1ns/100ps
module axi_gpreg_clock_mon (
module axi_gpreg_clock_mon #(
parameter ID = 0,
parameter BUF_ENABLE = 0) (
// clock
d_clk,
input d_clk,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// parameters
parameter ID = 0;
parameter BUF_ENABLE = 0;
// clock
input d_clk;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_d_preset = 'd0;
reg up_wack = 'd0;
reg up_d_resetn = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals

58
library/axi_gpreg/axi_gpreg_io.v
View File

@ -37,58 +37,32 @@
`timescale 1ns/100ps
module axi_gpreg_io (
module axi_gpreg_io #(
parameter ID = 0) (
// gpio
up_gp_ioenb,
up_gp_out,
up_gp_in,
output reg [31:0] up_gp_ioenb,
output reg [31:0] up_gp_out,
input [31:0] up_gp_in,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// parameters
parameter ID = 0;
// gpio
output [31:0] up_gp_ioenb;
output [31:0] up_gp_out;
input [31:0] up_gp_in;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_gp_ioenb = 'd0;
reg [31:0] up_gp_out = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire up_wreq_s;

104
library/axi_hdmi_rx/axi_hdmi_rx.v
View File

@ -37,87 +37,47 @@
// ***************************************************************************
// ***************************************************************************
module axi_hdmi_rx (
module axi_hdmi_rx #(
parameter ID = 0) (
// hdmi interface
hdmi_rx_clk,
hdmi_rx_data,
input hdmi_rx_clk,
input [15:0] hdmi_rx_data,
// dma interface
hdmi_clk,
hdmi_dma_sof,
hdmi_dma_de,
hdmi_dma_data,
hdmi_dma_ovf,
hdmi_dma_unf,
output hdmi_clk,
output hdmi_dma_sof,
output hdmi_dma_de,
output [63:0] hdmi_dma_data,
input hdmi_dma_ovf,
input hdmi_dma_unf,
// processor interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
// parameters
parameter ID = 0;
// hdmi interface
input hdmi_rx_clk;
input [15:0] hdmi_rx_data;
// vdma interface
output hdmi_clk;
output hdmi_dma_sof;
output hdmi_dma_de;
output [63:0] hdmi_dma_data;
input hdmi_dma_ovf;
input hdmi_dma_unf;
// processor interface
input s_axi_aresetn;
input s_axi_aclk;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal signals

72
library/axi_hdmi_rx/axi_hdmi_rx_core.v
View File

@ -40,60 +40,32 @@ module axi_hdmi_rx_core (
// hdmi interface
hdmi_clk,
hdmi_rst,
hdmi_data,
hdmi_edge_sel,
hdmi_bgr,
hdmi_packed,
hdmi_csc_bypass,
hdmi_vs_count,
hdmi_hs_count,
hdmi_tpm_oos,
hdmi_vs_oos,
hdmi_hs_oos,
hdmi_vs_mismatch,
hdmi_hs_mismatch,
hdmi_vs,
hdmi_hs,
input hdmi_clk,
input hdmi_rst,
input [15:0] hdmi_data,
input hdmi_edge_sel,
input hdmi_bgr,
input hdmi_packed,
input hdmi_csc_bypass,
input [15:0] hdmi_vs_count,
input [15:0] hdmi_hs_count,
output hdmi_tpm_oos,
output reg hdmi_vs_oos,
output reg hdmi_hs_oos,
output reg hdmi_vs_mismatch,
output reg hdmi_hs_mismatch,
output reg [15:0] hdmi_vs,
output reg [15:0] hdmi_hs,
// dma interface
hdmi_dma_sof,
hdmi_dma_de,
hdmi_dma_data);
// hdmi interface
input hdmi_clk;
input hdmi_rst;
input [15:0] hdmi_data;
input hdmi_edge_sel;
input hdmi_bgr;
input hdmi_packed;
input hdmi_csc_bypass;
input [15:0] hdmi_vs_count;
input [15:0] hdmi_hs_count;
output hdmi_tpm_oos;
output hdmi_vs_oos;
output hdmi_hs_oos;
output hdmi_vs_mismatch;
output hdmi_hs_mismatch;
output [15:0] hdmi_vs;
output [15:0] hdmi_hs;
// dma interface
output hdmi_dma_sof;
output hdmi_dma_de;
output [63:0] hdmi_dma_data;
output reg hdmi_dma_sof,
output reg hdmi_dma_de,
output reg [63:0] hdmi_dma_data);
// internal registers
reg hdmi_dma_sof = 'd0;
reg hdmi_dma_de = 'd0;
reg hdmi_dma_de_cnt = 'd0;
reg [63:0] hdmi_dma_data = 'd0;
reg hdmi_dma_sof_int = 'd0;
reg hdmi_dma_de_int = 'd0;
reg [31:0] hdmi_dma_data_int = 'd0;
@ -110,12 +82,6 @@ module axi_hdmi_rx_core (
reg hdmi_de_444_p = 'd0;
reg [31:0] hdmi_data_444_p = 'd0;
reg hdmi_dma_enable = 'd0;
reg [15:0] hdmi_vs = 'd0;
reg [15:0] hdmi_hs = 'd0;
reg hdmi_vs_oos = 'd0;
reg hdmi_hs_oos = 'd0;
reg hdmi_vs_mismatch = 'd0;
reg hdmi_hs_mismatch = 'd0;
reg hdmi_hs_de_d = 'd0;
reg hdmi_vs_de_d = 'd0;
reg hdmi_sof = 'd0;

31
library/axi_hdmi_rx/axi_hdmi_rx_es.v
View File

@ -36,32 +36,20 @@
// ***************************************************************************
// Receive HDMI, hdmi embedded syncs data in, video dma data out.
module axi_hdmi_rx_es (
module axi_hdmi_rx_es #(
parameter DATA_WIDTH = 32) (
// hdmi interface
hdmi_clk,
hdmi_data,
hdmi_vs_de,
hdmi_hs_de,
hdmi_data_de);
input hdmi_clk,
input [(DATA_WIDTH-1):0] hdmi_data,
output reg hdmi_vs_de,
output reg hdmi_hs_de,
output reg [(DATA_WIDTH-1):0] hdmi_data_de);
// parameters
parameter DATA_WIDTH = 32;
localparam BYTE_WIDTH = DATA_WIDTH/8;
// hdmi interface
input hdmi_clk;
input [(DATA_WIDTH-1):0] hdmi_data;
// dma interface
output hdmi_vs_de;
output hdmi_hs_de;
output [(DATA_WIDTH-1):0] hdmi_data_de;
// internal registers
reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0;
@ -76,9 +64,6 @@ module axi_hdmi_rx_es (
reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
reg hdmi_hs_de_rcv_4d = 'd0;
reg hdmi_vs_de_rcv_4d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_de = 'd0;
reg hdmi_hs_de = 'd0;
reg hdmi_vs_de = 'd0;
reg [ 1:0] hdmi_preamble_cnt = 'd0;
reg hdmi_hs_de_rcv = 'd0;
reg hdmi_vs_de_rcv = 'd0;

17
library/axi_hdmi_rx/axi_hdmi_rx_tpm.v
View File

@ -36,18 +36,12 @@
// ***************************************************************************
module axi_hdmi_rx_tpm (
hdmi_clk,
hdmi_sof,
hdmi_de,
hdmi_data,
input hdmi_clk,
input hdmi_sof,
input hdmi_de,
input [15:0] hdmi_data,
hdmi_tpm_oos);
input hdmi_clk;
input hdmi_sof;
input hdmi_de;
input [15:0] hdmi_data;
output hdmi_tpm_oos;
output reg hdmi_tpm_oos);
wire [15:0] hdmi_tpm_lr_data_s;
wire hdmi_tpm_lr_mismatch_s;
@ -57,7 +51,6 @@ module axi_hdmi_rx_tpm (
reg [15:0] hdmi_tpm_data = 'd0;
reg hdmi_tpm_lr_mismatch = 'd0;
reg hdmi_tpm_fr_mismatch = 'd0;
reg hdmi_tpm_oos = 'd0;
// Limited range
assign hdmi_tpm_lr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h10) ? 8'h10 :

159
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -35,141 +35,80 @@
// ***************************************************************************
// ***************************************************************************
module axi_hdmi_tx (
module axi_hdmi_tx #(
parameter ID = 0,
parameter CR_CB_N = 0,
parameter DEVICE_TYPE = 0,
parameter EMBEDDED_SYNC = 0,
parameter OUT_CLK_POLARITY = 0) (
// hdmi interface
hdmi_clk,
hdmi_out_clk,
input hdmi_clk,
output hdmi_out_clk,
// 16-bit interface
hdmi_16_hsync,
hdmi_16_vsync,
hdmi_16_data_e,
hdmi_16_data,
hdmi_16_es_data,
output hdmi_16_hsync,
output hdmi_16_vsync,
output hdmi_16_data_e,
output [15:0] hdmi_16_data,
output [15:0] hdmi_16_es_data,
// 24-bit interface
hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_data_e,
hdmi_24_data,
output hdmi_24_hsync,
output hdmi_24_vsync,
output hdmi_24_data_e,
output [23:0] hdmi_24_data,
// 36-bit interface
hdmi_36_hsync,
hdmi_36_vsync,
hdmi_36_data_e,
hdmi_36_data,
output hdmi_36_hsync,
output hdmi_36_vsync,
output hdmi_36_data_e,
output [35:0] hdmi_36_data,
// vdma interface
vdma_clk,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_data,
vdma_ready,
input vdma_clk,
output vdma_fs,
input vdma_fs_ret,
input vdma_valid,
input [63:0] vdma_data,
output vdma_ready,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
// parameters
parameter ID = 0;
parameter CR_CB_N = 0;
parameter DEVICE_TYPE = 0;
parameter EMBEDDED_SYNC = 0;
/* 0 = Launch on rising edge, 1 = Launch on falling edge */
parameter OUT_CLK_POLARITY = 0;
localparam XILINX_7SERIES = 0;
localparam XILINX_ULTRASCALE = 1;
localparam ALTERA_5SERIES = 16;
// hdmi interface
input hdmi_clk;
output hdmi_out_clk;
// 16-bit interface
output hdmi_16_hsync;
output hdmi_16_vsync;
output hdmi_16_data_e;
output [15:0] hdmi_16_data;
output [15:0] hdmi_16_es_data;
// 24-bit interface
output hdmi_24_hsync;
output hdmi_24_vsync;
output hdmi_24_data_e;
output [23:0] hdmi_24_data;
// 36-bit interface
output hdmi_36_hsync;
output hdmi_36_vsync;
output hdmi_36_data_e;
output [35:0] hdmi_36_data;
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_fs_ret;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// reset and clocks
wire up_rstn;

171
library/axi_hdmi_tx/axi_hdmi_tx_core.v
View File

@ -36,145 +36,80 @@
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
module axi_hdmi_tx_core (
module axi_hdmi_tx_core #(
parameter CR_CB_N = 0,
parameter EMBEDDED_SYNC = 0) (
// hdmi interface
hdmi_clk,
hdmi_rst,
input hdmi_clk,
input hdmi_rst,
// 16-bit interface
hdmi_16_hsync,
hdmi_16_vsync,
hdmi_16_data_e,
hdmi_16_data,
hdmi_16_es_data,
output reg hdmi_16_hsync,
output reg hdmi_16_vsync,
output reg hdmi_16_data_e,
output reg [15:0] hdmi_16_data,
output reg [15:0] hdmi_16_es_data,
// 24-bit interface
hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_data_e,
hdmi_24_data,
output reg hdmi_24_hsync,
output reg hdmi_24_vsync,
output reg hdmi_24_data_e,
output reg [23:0] hdmi_24_data,
// 36-bit interface
hdmi_36_hsync,
hdmi_36_vsync,
hdmi_36_data_e,
hdmi_36_data,
output reg hdmi_36_hsync,
output reg hdmi_36_vsync,
output reg hdmi_36_data_e,
output reg [35:0] hdmi_36_data,
// control signals
hdmi_fs_toggle,
hdmi_raddr_g,
hdmi_tpm_oos,
hdmi_status,
output reg hdmi_fs_toggle,
output reg [ 8:0] hdmi_raddr_g,
output reg hdmi_tpm_oos,
output reg hdmi_status,
// vdma interface
vdma_clk,
vdma_wr,
vdma_waddr,
vdma_wdata,
vdma_fs_ret_toggle,
vdma_fs_waddr,
input vdma_clk,
input vdma_wr,
input [ 8:0] vdma_waddr,
input [47:0] vdma_wdata,
input vdma_fs_ret_toggle,
input [ 8:0] vdma_fs_waddr,
// processor interface
hdmi_csc_bypass,
hdmi_ss_bypass,
hdmi_srcsel,
hdmi_const_rgb,
hdmi_hl_active,
hdmi_hl_width,
hdmi_hs_width,
hdmi_he_max,
hdmi_he_min,
hdmi_vf_active,
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min,
hdmi_clip_max,
hdmi_clip_min);
input hdmi_csc_bypass,
input hdmi_ss_bypass,
input [ 1:0] hdmi_srcsel,
input [23:0] hdmi_const_rgb,
input [15:0] hdmi_hl_active,
input [15:0] hdmi_hl_width,
input [15:0] hdmi_hs_width,
input [15:0] hdmi_he_max,
input [15:0] hdmi_he_min,
input [15:0] hdmi_vf_active,
input [15:0] hdmi_vf_width,
input [15:0] hdmi_vs_width,
input [15:0] hdmi_ve_max,
input [15:0] hdmi_ve_min,
input [23:0] hdmi_clip_max,
input [23:0] hdmi_clip_min);
// parameters
parameter CR_CB_N = 0;
parameter EMBEDDED_SYNC = 0;
// hdmi interface
input hdmi_clk;
input hdmi_rst;
// 16-bit interface
output hdmi_16_hsync;
output hdmi_16_vsync;
output hdmi_16_data_e;
output [15:0] hdmi_16_data;
output [15:0] hdmi_16_es_data;
// 24-bit interface
output hdmi_24_hsync;
output hdmi_24_vsync;
output hdmi_24_data_e;
output [23:0] hdmi_24_data;
// 36-bit interface
output hdmi_36_hsync;
output hdmi_36_vsync;
output hdmi_36_data_e;
output [35:0] hdmi_36_data;
// control signals
output hdmi_fs_toggle;
output [ 8:0] hdmi_raddr_g;
output hdmi_tpm_oos;
output hdmi_status;
// vdma interface
input vdma_clk;
input vdma_wr;
input [ 8:0] vdma_waddr;
input [47:0] vdma_wdata;
input vdma_fs_ret_toggle;
input [ 8:0] vdma_fs_waddr;
// processor interface
input hdmi_csc_bypass;
input hdmi_ss_bypass;
input [ 1:0] hdmi_srcsel;
input [23:0] hdmi_const_rgb;
input [15:0] hdmi_hl_active;
input [15:0] hdmi_hl_width;
input [15:0] hdmi_hs_width;
input [15:0] hdmi_he_max;
input [15:0] hdmi_he_min;
input [15:0] hdmi_vf_active;
input [15:0] hdmi_vf_width;
input [15:0] hdmi_vs_width;
input [15:0] hdmi_ve_max;
input [15:0] hdmi_ve_min;
input [23:0] hdmi_clip_max;
input [23:0] hdmi_clip_min;
// internal registers
reg hdmi_status = 'd0;
reg hdmi_enable = 'd0;
reg [15:0] hdmi_hs_count = 'd0;
reg [15:0] hdmi_vs_count = 'd0;
reg hdmi_fs = 'd0;
reg hdmi_fs_toggle = 'd0;
reg hdmi_fs_ret_toggle_m1 = 'd0;
reg hdmi_fs_ret_toggle_m2 = 'd0;
reg hdmi_fs_ret_toggle_m3 = 'd0;
@ -185,7 +120,6 @@ module axi_hdmi_tx_core (
reg hdmi_hs_de = 'd0;
reg hdmi_vs_de = 'd0;
reg [ 9:0] hdmi_raddr = 'd0;
reg [ 8:0] hdmi_raddr_g = 'd0;
reg hdmi_hs_d = 'd0;
reg hdmi_vs_d = 'd0;
reg hdmi_hs_de_d = 'd0;
@ -200,11 +134,6 @@ module axi_hdmi_tx_core (
reg hdmi_data_sel_2d = 'd0;
reg [47:0] hdmi_data_2d = 'd0;
reg [23:0] hdmi_tpm_data = 'd0;
reg hdmi_tpm_oos = 'd0;
reg hdmi_36_hsync = 'd0;
reg hdmi_36_vsync = 'd0;
reg hdmi_36_data_e = 'd0;
reg [35:0] hdmi_36_data = 'd0;
reg hdmi_hsync = 'd0;
reg hdmi_vsync = 'd0;
reg hdmi_hsync_data_e = 'd0;
@ -217,14 +146,8 @@ module axi_hdmi_tx_core (
reg hdmi_24_csc_vsync_data_e = 'd0;
reg hdmi_24_csc_data_e = 'd0;
reg [23:0] hdmi_24_csc_data = 'd0;
reg hdmi_24_hsync = 'd0;
reg hdmi_24_vsync = 'd0;
reg hdmi_24_hsync_data_e = 'd0;
reg hdmi_24_vsync_data_e = 'd0;
reg hdmi_24_data_e = 'd0;
reg [23:0] hdmi_24_data = 'd0;
reg hdmi_16_hsync = 'd0;
reg hdmi_16_vsync = 'd0;
reg hdmi_16_hsync_data_e = 'd0;
reg hdmi_16_vsync_data_e = 'd0;
reg hdmi_16_hsync_d = 'd0;
@ -233,12 +156,9 @@ module axi_hdmi_tx_core (
reg hdmi_16_vsync_data_e_d = 'd0;
reg hdmi_16_data_e_d = 'd0;
reg [15:0] hdmi_16_data_d = 'd0;
reg hdmi_16_data_e = 'd0;
reg [15:0] hdmi_16_data = 'd0;
reg hdmi_es_hs_de = 'd0;
reg hdmi_es_vs_de = 'd0;
reg [15:0] hdmi_es_data = 'd0;
reg [15:0] hdmi_16_es_data = 'd0;
reg [23:0] hdmi_clip_data = 'd0;
reg hdmi_clip_hs_de_d = 'd0;
reg hdmi_clip_vs_de_d = 'd0;
@ -272,7 +192,6 @@ module axi_hdmi_tx_core (
wire [15:0] hdmi_ss_data_s;
wire [15:0] hdmi_es_data_s;
// binary to grey conversion
function [8:0] b2g;

26
library/axi_hdmi_tx/axi_hdmi_tx_es.v
View File

@ -38,29 +38,20 @@
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
module axi_hdmi_tx_es (
module axi_hdmi_tx_es #(
parameter DATA_WIDTH = 32) (
// hdmi interface
hdmi_clk,
hdmi_hs_de,
hdmi_vs_de,
hdmi_data_de,
hdmi_data);
input hdmi_clk,
input hdmi_hs_de,
input hdmi_vs_de,
input [(DATA_WIDTH-1):0] hdmi_data_de,
output reg [(DATA_WIDTH-1):0] hdmi_data);
// parameters
parameter DATA_WIDTH = 32;
localparam BYTE_WIDTH = DATA_WIDTH/8;
// hdmi interface
input hdmi_clk;
input hdmi_hs_de;
input hdmi_vs_de;
input [(DATA_WIDTH-1):0] hdmi_data_de;
output [(DATA_WIDTH-1):0] hdmi_data;
// internal registers
reg hdmi_hs_de_d = 'd0;
@ -73,7 +64,6 @@ module axi_hdmi_tx_es (
reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
reg hdmi_hs_de_5d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_5d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data = 'd0;
// internal wires

Some files were not shown because too many files have changed in this diff Show More