From 1bc8a41aea8056be17df9eb6ad0d5bffead524ff Mon Sep 17 00:00:00 2001 From: hotoleanudan <58723330+hotoleanudan@users.noreply.github.com> Date: Tue, 2 Nov 2021 12:05:42 +0200 Subject: [PATCH] vc709_carrier: Add vc709 carrier (#788) Added vc709 carrier to the projects/common folder location. Signed-off-by: Dan Hotoleanu --- projects/common/vc709/vc709_system_bd.tcl | 259 ++++++++++++++++++ projects/common/vc709/vc709_system_constr.xdc | 55 ++++ projects/common/vc709/vc709_system_mig.prj | 210 ++++++++++++++ projects/scripts/adi_project_xilinx.tcl | 5 + 4 files changed, 529 insertions(+) create mode 100644 projects/common/vc709/vc709_system_bd.tcl create mode 100644 projects/common/vc709/vc709_system_constr.xdc create mode 100644 projects/common/vc709/vc709_system_mig.prj diff --git a/projects/common/vc709/vc709_system_bd.tcl b/projects/common/vc709/vc709_system_bd.tcl new file mode 100644 index 000000000..03de976b2 --- /dev/null +++ b/projects/common/vc709/vc709_system_bd.tcl @@ -0,0 +1,259 @@ + +create_bd_port -dir I -type rst sys_rst +create_bd_port -dir I sys_clk_p +create_bd_port -dir I sys_clk_n + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mgt_clk +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:emc_rtl:1.0 linear_flash +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main + +create_bd_port -dir I uart_sin +create_bd_port -dir O uart_sout + +create_bd_port -dir O -from 7 -to 0 spi_csn_o +create_bd_port -dir I -from 7 -to 0 spi_csn_i +create_bd_port -dir I spi_clk_i +create_bd_port -dir O spi_clk_o +create_bd_port -dir I spi_sdo_i +create_bd_port -dir O spi_sdo_o +create_bd_port -dir I spi_sdi_i + +create_bd_port -dir I -from 31 -to 0 gpio0_i +create_bd_port -dir O -from 31 -to 0 gpio0_o +create_bd_port -dir O -from 31 -to 0 gpio0_t +create_bd_port -dir I -from 31 -to 0 gpio1_i +create_bd_port -dir O -from 31 -to 0 gpio1_o +create_bd_port -dir O -from 31 -to 0 gpio1_t + +set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst] + +# instance: microblaze - processor + +ad_ip_instance microblaze sys_mb +ad_ip_parameter sys_mb CONFIG.G_TEMPLATE_LIST 4 +ad_ip_parameter sys_mb CONFIG.C_DCACHE_FORCE_TAG_LUTRAM 1 + +# instance: microblaze - local memory & bus + +ad_ip_instance lmb_v10 sys_dlmb +ad_ip_instance lmb_v10 sys_ilmb + +ad_ip_instance lmb_bram_if_cntlr sys_dlmb_cntlr +ad_ip_parameter sys_dlmb_cntlr CONFIG.C_ECC 0 + +ad_ip_instance lmb_bram_if_cntlr sys_ilmb_cntlr +ad_ip_parameter sys_ilmb_cntlr CONFIG.C_ECC 0 + +ad_ip_instance blk_mem_gen sys_lmb_bram +ad_ip_parameter sys_lmb_bram CONFIG.Memory_Type True_Dual_Port_RAM +ad_ip_parameter sys_lmb_bram CONFIG.use_bram_block BRAM_Controller + +# instance: microblaze- mdm + +ad_ip_instance mdm sys_mb_debug +ad_ip_parameter sys_mb_debug CONFIG.C_USE_UART 1 + +# instance: system reset/clocks + +ad_ip_instance proc_sys_reset sys_rstgen +ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 +ad_ip_instance proc_sys_reset sys_200m_rstgen +ad_ip_parameter sys_200m_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +# instance: ddr (mig) + +ad_ip_instance mig_7series axi_ddr_cntrl +set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]] +file copy -force $ad_hdl_dir/projects/common/vc709/vc709_system_mig.prj "$axi_ddr_cntrl_dir/" +ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE vc709_system_mig.prj + +# instance: default peripherals + +ad_ip_instance axi_iic axi_iic_main + +ad_ip_instance axi_uartlite axi_uart +ad_ip_parameter axi_uart CONFIG.C_BAUDRATE 115200 + +ad_ip_instance axi_timer axi_timer + +ad_ip_instance axi_quad_spi axi_spi +ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 8 +ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8 + +ad_ip_instance axi_gpio axi_gpio +ad_ip_parameter axi_gpio CONFIG.C_IS_DUAL 1 +ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32 +ad_ip_parameter axi_gpio CONFIG.C_GPIO2_WIDTH 32 +ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1 + +# instance: interrupt + +ad_ip_instance axi_intc axi_intc +ad_ip_parameter axi_intc CONFIG.C_HAS_FAST 0 + +ad_ip_instance xlconcat sys_concat_intc +ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 + +# linear flash + +ad_ip_instance axi_emc axi_linear_flash +ad_ip_parameter axi_linear_flash CONFIG.USE_BOARD_FLOW true +ad_ip_parameter axi_linear_flash CONFIG.EMC_BOARD_INTERFACE linear_flash +ad_ip_parameter axi_linear_flash CONFIG.C_MEM0_TYPE 2 +ad_ip_parameter axi_linear_flash CONFIG.C_S_AXI_MEM_ID_WIDTH 0 +ad_ip_parameter axi_linear_flash CONFIG.C_THZCE_PS_MEM_0 7000 +ad_ip_parameter axi_linear_flash CONFIG.C_TLZWE_PS_MEM_0 0 +ad_ip_parameter axi_linear_flash CONFIG.C_TWC_PS_MEM_0 15000 +ad_ip_parameter axi_linear_flash CONFIG.C_WR_REC_TIME_MEM_0 0 +ad_ip_parameter axi_linear_flash CONFIG.C_TWP_PS_MEM_0 40000 +ad_ip_parameter axi_linear_flash CONFIG.C_TWPH_PS_MEM_0 20000 +ad_ip_parameter axi_linear_flash CONFIG.C_TPACC_PS_FLASH_0 15000 +ad_ip_parameter axi_linear_flash CONFIG.C_TCEDV_PS_MEM_0 96000 +ad_ip_parameter axi_linear_flash CONFIG.C_TAVDV_PS_MEM_0 96000 + +# connections + +ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst +ad_connect sys_rstgen/mb_reset sys_mb/Reset +ad_connect sys_rstgen/bus_struct_reset sys_dlmb/SYS_Rst +ad_connect sys_rstgen/bus_struct_reset sys_ilmb/SYS_Rst +ad_connect sys_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst +ad_connect sys_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst + +# microblaze local memory + +ad_connect sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB +ad_connect sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB +ad_connect sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA +ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB +ad_connect sys_mb/DLMB sys_dlmb/LMB_M +ad_connect sys_mb/ILMB sys_ilmb/LMB_M + +# system id + +ad_ip_instance axi_sysid axi_sysid_0 +ad_ip_instance sysid_rom rom_sys_0 + +ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr +ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data +ad_connect sys_cpu_clk rom_sys_0/clk + +# microblaze debug & interrupt + +ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG +ad_connect axi_intc/interrupt sys_mb/INTERRUPT +ad_connect sys_concat_intc/dout axi_intc/intr + +# defaults (peripherals) + +ad_connect axi_ddr_cntrl/mmcm_locked sys_rstgen/dcm_locked +ad_connect axi_ddr_cntrl/mmcm_locked sys_200m_rstgen/dcm_locked + +ad_connect sys_cpu_clk axi_ddr_cntrl/ui_addn_clk_0 +ad_connect sys_200m_clk axi_ddr_cntrl/ui_clk +ad_connect sys_cpu_resetn axi_ddr_cntrl/aresetn +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_200m_reset sys_200m_rstgen/peripheral_reset +ad_connect sys_200m_resetn sys_200m_rstgen/peripheral_aresetn + +# generic system clocks pointers + +set sys_cpu_clk [get_bd_nets sys_cpu_clk] +set sys_dma_clk [get_bd_nets sys_200m_clk] +set sys_iodelay_clk [get_bd_nets sys_200m_clk] + +set sys_cpu_reset [get_bd_nets sys_cpu_reset] +set sys_cpu_resetn [get_bd_nets sys_cpu_resetn] +set sys_dma_reset [get_bd_nets sys_200m_reset] +set sys_dma_resetn [get_bd_nets sys_200m_resetn] +set sys_iodelay_reset [get_bd_nets sys_200m_reset] +set sys_iodelay_resetn [get_bd_nets sys_200m_resetn] + +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_200m_clk sys_200m_rstgen/slowest_sync_clk +ad_connect sys_cpu_clk sys_mb/Clk +ad_connect sys_cpu_clk sys_dlmb/LMB_Clk +ad_connect sys_cpu_clk sys_ilmb/LMB_Clk +ad_connect sys_cpu_clk sys_dlmb_cntlr/LMB_Clk +ad_connect sys_cpu_clk sys_ilmb_cntlr/LMB_Clk +ad_connect sys_cpu_clk axi_spi/ext_spi_clk + +# defaults (interrupts) + +ad_connect sys_concat_intc/In0 axi_timer/interrupt +ad_connect sys_concat_intc/In1 GND +ad_connect sys_concat_intc/In2 GND +ad_connect sys_concat_intc/In3 GND +ad_connect sys_concat_intc/In4 axi_uart/interrupt +ad_connect sys_concat_intc/In5 GND +ad_connect sys_concat_intc/In6 GND +ad_connect sys_concat_intc/In7 GND +ad_connect sys_concat_intc/In8 GND +ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt +ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt +ad_connect sys_concat_intc/In12 GND +ad_connect sys_concat_intc/In13 GND +ad_connect sys_concat_intc/In14 GND +ad_connect sys_concat_intc/In15 GND + +# defaults (external interface) + +ad_connect sys_rst sys_rstgen/ext_reset_in +ad_connect sys_rst axi_ddr_cntrl/sys_rst +ad_connect sys_200m_rst sys_200m_rstgen/ext_reset_in +ad_connect sys_200m_rst axi_ddr_cntrl/ui_clk_sync_rst +ad_connect sys_clk_p axi_ddr_cntrl/sys_clk_p +ad_connect sys_clk_n axi_ddr_cntrl/sys_clk_n +ad_connect ddr3 axi_ddr_cntrl/DDR3 +ad_connect uart_sin axi_uart/rx +ad_connect uart_sout axi_uart/tx +ad_connect iic_main axi_iic_main/iic + +ad_connect spi_csn_i axi_spi/ss_i +ad_connect spi_csn_o axi_spi/ss_o +ad_connect spi_clk_i axi_spi/sck_i +ad_connect spi_clk_o axi_spi/sck_o +ad_connect spi_sdo_i axi_spi/io0_i +ad_connect spi_sdo_o axi_spi/io0_o +ad_connect spi_sdi_i axi_spi/io1_i +ad_connect gpio0_i axi_gpio/gpio_io_i +ad_connect gpio0_o axi_gpio/gpio_io_o +ad_connect gpio0_t axi_gpio/gpio_io_t +ad_connect gpio1_i axi_gpio/gpio2_io_i +ad_connect gpio1_o axi_gpio/gpio2_io_o +ad_connect gpio1_t axi_gpio/gpio2_io_t + +# linear_flash + +ad_connect axi_linear_flash/EMC_INTF linear_flash + +ad_connect sys_cpu_resetn axi_linear_flash/s_axi_aresetn +ad_connect sys_cpu_clk axi_linear_flash/s_axi_aclk +ad_connect sys_cpu_clk axi_linear_flash/rdclk + +# address mapping + +ad_cpu_interconnect 0x41400000 sys_mb_debug +ad_cpu_interconnect 0x41200000 axi_intc +ad_cpu_interconnect 0x41C00000 axi_timer +ad_cpu_interconnect 0x40600000 axi_uart +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interconnect 0x45000000 axi_sysid_0 +ad_cpu_interconnect 0x40000000 axi_gpio +ad_cpu_interconnect 0x44A70000 axi_spi +ad_cpu_interconnect 0x60000000 axi_linear_flash + +ad_mem_hp0_interconnect sys_200m_clk axi_ddr_cntrl/S_AXI +ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_DC +ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_IC + +create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \ + [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr +create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \ + [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr + +set_property range 0x2000000 [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_linear_flash}] diff --git a/projects/common/vc709/vc709_system_constr.xdc b/projects/common/vc709/vc709_system_constr.xdc new file mode 100644 index 000000000..b99afa7cd --- /dev/null +++ b/projects/common/vc709/vc709_system_constr.xdc @@ -0,0 +1,55 @@ + +# constraints + +set_property -dict {PACKAGE_PIN AV40 IOSTANDARD LVCMOS18} [get_ports sys_rst] + +# clocks + +set_property -dict {PACKAGE_PIN H19 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_p] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_n] + +# uart + +set_property -dict {PACKAGE_PIN AU33 IOSTANDARD LVCMOS18} [get_ports uart_sin] +set_property -dict {PACKAGE_PIN AU36 IOSTANDARD LVCMOS18} [get_ports uart_sout] + +# fan + +set_property -dict {PACKAGE_PIN BA37 IOSTANDARD LVCMOS18} [get_ports fan_pwm] + +set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[0]] ; ## GPIO_DIP_SW0 +set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[1]] ; ## GPIO_DIP_SW1 +set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[2]] ; ## GPIO_DIP_SW2 +set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[3]] ; ## GPIO_DIP_SW3 +set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[4]] ; ## GPIO_DIP_SW4 +set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[5]] ; ## GPIO_DIP_SW5 +set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[6]] ; ## GPIO_DIP_SW6 +set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[7]] ; ## GPIO_DIP_SW7 +set_property -dict {PACKAGE_PIN AR40 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[8]] ; ## GPIO_SW_N +set_property -dict {PACKAGE_PIN AU38 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[9]] ; ## GPIO_SW_E +set_property -dict {PACKAGE_PIN AP40 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[10]] ; ## GPIO_SW_S +set_property -dict {PACKAGE_PIN AW40 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[11]] ; ## GPIO_SW_W +set_property -dict {PACKAGE_PIN AV39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[12]] ; ## GPIO_SW_C +set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[0]] ; ## GPIO_LED_0_LS +set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[1]] ; ## GPIO_LED_1_LS +set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[2]] ; ## GPIO_LED_2_LS +set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[3]] ; ## GPIO_LED_3_LS +set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[4]] ; ## GPIO_LED_4_LS +set_property -dict {PACKAGE_PIN AP41 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[5]] ; ## GPIO_LED_5_LS +set_property -dict {PACKAGE_PIN AP42 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6_LS +set_property -dict {PACKAGE_PIN AU39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7_LS + +# iic + +set_property -dict {PACKAGE_PIN AY42 IOSTANDARD LVCMOS18} [get_ports iic_rstn] +set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN AU32 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda] + +#Setting the Configuration Bank Voltage Select +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] + +# Create SPI clock +create_generated_clock -name spi_clk \ + -source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \ + -divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o] diff --git a/projects/common/vc709/vc709_system_mig.prj b/projects/common/vc709/vc709_system_mig.prj new file mode 100644 index 000000000..992cfe372 --- /dev/null +++ b/projects/common/vc709/vc709_system_mig.prj @@ -0,0 +1,210 @@ + + + + system_axi_ddr_cntrl_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7vx690t-ffg1761/-2 + 4.2 + Differential + Use System Clock + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9 + 1250 + 2.0V + 4:1 + 200 + 1 + 800 + 8.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 16 + 10 + 3 + 1.5V + 4294967296 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 32 + 256 + 4 + 0 + + + + diff --git a/projects/scripts/adi_project_xilinx.tcl b/projects/scripts/adi_project_xilinx.tcl index 3b3325707..2525a8fb8 100644 --- a/projects/scripts/adi_project_xilinx.tcl +++ b/projects/scripts/adi_project_xilinx.tcl @@ -129,6 +129,11 @@ proc adi_project {project_name {mode 0} {parameter_list {}} } { set device "xcvc1902-vsva2197-2MP-e-S" set board [lindex [lsearch -all -inline [get_board_parts] *vck190*] end] } + if [regexp "_vc709$" $project_name] { + set device "xc7vx690tffg1761-2" + set board [lindex [lsearch -all -inline [get_board_parts] *vc709*] end] + } + adi_project_create $project_name $mode $parameter_list $device $board }