vc709_carrier: Add vc709 carrier (#788)
Added vc709 carrier to the projects/common folder location. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>main
hotoleanudan
GitHub
parent
70cc53bbc8
commit
1bc8a41aea
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create_bd_port -dir I -type rst sys_rst
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create_bd_port -dir I sys_clk_p
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create_bd_port -dir I sys_clk_n
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mgt_clk
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:emc_rtl:1.0 linear_flash
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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create_bd_port -dir I uart_sin
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create_bd_port -dir O uart_sout
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create_bd_port -dir O -from 7 -to 0 spi_csn_o
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create_bd_port -dir I -from 7 -to 0 spi_csn_i
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create_bd_port -dir I spi_clk_i
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create_bd_port -dir O spi_clk_o
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create_bd_port -dir I spi_sdo_i
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create_bd_port -dir O spi_sdo_o
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create_bd_port -dir I spi_sdi_i
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create_bd_port -dir I -from 31 -to 0 gpio0_i
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create_bd_port -dir O -from 31 -to 0 gpio0_o
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create_bd_port -dir O -from 31 -to 0 gpio0_t
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create_bd_port -dir I -from 31 -to 0 gpio1_i
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create_bd_port -dir O -from 31 -to 0 gpio1_o
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create_bd_port -dir O -from 31 -to 0 gpio1_t
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set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst]
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# instance: microblaze - processor
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ad_ip_instance microblaze sys_mb
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ad_ip_parameter sys_mb CONFIG.G_TEMPLATE_LIST 4
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ad_ip_parameter sys_mb CONFIG.C_DCACHE_FORCE_TAG_LUTRAM 1
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# instance: microblaze - local memory & bus
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ad_ip_instance lmb_v10 sys_dlmb
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ad_ip_instance lmb_v10 sys_ilmb
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ad_ip_instance lmb_bram_if_cntlr sys_dlmb_cntlr
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ad_ip_parameter sys_dlmb_cntlr CONFIG.C_ECC 0
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ad_ip_instance lmb_bram_if_cntlr sys_ilmb_cntlr
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ad_ip_parameter sys_ilmb_cntlr CONFIG.C_ECC 0
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ad_ip_instance blk_mem_gen sys_lmb_bram
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ad_ip_parameter sys_lmb_bram CONFIG.Memory_Type True_Dual_Port_RAM
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ad_ip_parameter sys_lmb_bram CONFIG.use_bram_block BRAM_Controller
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# instance: microblaze- mdm
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ad_ip_instance mdm sys_mb_debug
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ad_ip_parameter sys_mb_debug CONFIG.C_USE_UART 1
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# instance: system reset/clocks
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ad_ip_instance proc_sys_reset sys_rstgen
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ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_ip_instance proc_sys_reset sys_200m_rstgen
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ad_ip_parameter sys_200m_rstgen CONFIG.C_EXT_RST_WIDTH 1
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# instance: ddr (mig)
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ad_ip_instance mig_7series axi_ddr_cntrl
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set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]]
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file copy -force $ad_hdl_dir/projects/common/vc709/vc709_system_mig.prj "$axi_ddr_cntrl_dir/"
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ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE vc709_system_mig.prj
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# instance: default peripherals
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ad_ip_instance axi_iic axi_iic_main
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ad_ip_instance axi_uartlite axi_uart
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ad_ip_parameter axi_uart CONFIG.C_BAUDRATE 115200
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ad_ip_instance axi_timer axi_timer
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ad_ip_instance axi_quad_spi axi_spi
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ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0
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ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 8
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ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8
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ad_ip_instance axi_gpio axi_gpio
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ad_ip_parameter axi_gpio CONFIG.C_IS_DUAL 1
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ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32
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ad_ip_parameter axi_gpio CONFIG.C_GPIO2_WIDTH 32
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ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1
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# instance: interrupt
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ad_ip_instance axi_intc axi_intc
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ad_ip_parameter axi_intc CONFIG.C_HAS_FAST 0
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ad_ip_instance xlconcat sys_concat_intc
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ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
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# linear flash
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ad_ip_instance axi_emc axi_linear_flash
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ad_ip_parameter axi_linear_flash CONFIG.USE_BOARD_FLOW true
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ad_ip_parameter axi_linear_flash CONFIG.EMC_BOARD_INTERFACE linear_flash
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ad_ip_parameter axi_linear_flash CONFIG.C_MEM0_TYPE 2
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ad_ip_parameter axi_linear_flash CONFIG.C_S_AXI_MEM_ID_WIDTH 0
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ad_ip_parameter axi_linear_flash CONFIG.C_THZCE_PS_MEM_0 7000
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ad_ip_parameter axi_linear_flash CONFIG.C_TLZWE_PS_MEM_0 0
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ad_ip_parameter axi_linear_flash CONFIG.C_TWC_PS_MEM_0 15000
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ad_ip_parameter axi_linear_flash CONFIG.C_WR_REC_TIME_MEM_0 0
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ad_ip_parameter axi_linear_flash CONFIG.C_TWP_PS_MEM_0 40000
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ad_ip_parameter axi_linear_flash CONFIG.C_TWPH_PS_MEM_0 20000
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ad_ip_parameter axi_linear_flash CONFIG.C_TPACC_PS_FLASH_0 15000
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ad_ip_parameter axi_linear_flash CONFIG.C_TCEDV_PS_MEM_0 96000
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ad_ip_parameter axi_linear_flash CONFIG.C_TAVDV_PS_MEM_0 96000
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# connections
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ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst
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ad_connect sys_rstgen/mb_reset sys_mb/Reset
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ad_connect sys_rstgen/bus_struct_reset sys_dlmb/SYS_Rst
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ad_connect sys_rstgen/bus_struct_reset sys_ilmb/SYS_Rst
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ad_connect sys_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst
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ad_connect sys_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst
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# microblaze local memory
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ad_connect sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB
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ad_connect sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB
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ad_connect sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA
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ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB
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ad_connect sys_mb/DLMB sys_dlmb/LMB_M
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ad_connect sys_mb/ILMB sys_ilmb/LMB_M
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# system id
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ad_ip_instance axi_sysid axi_sysid_0
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ad_ip_instance sysid_rom rom_sys_0
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ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr
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ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data
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ad_connect sys_cpu_clk rom_sys_0/clk
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# microblaze debug & interrupt
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ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG
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ad_connect axi_intc/interrupt sys_mb/INTERRUPT
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ad_connect sys_concat_intc/dout axi_intc/intr
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# defaults (peripherals)
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ad_connect axi_ddr_cntrl/mmcm_locked sys_rstgen/dcm_locked
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ad_connect axi_ddr_cntrl/mmcm_locked sys_200m_rstgen/dcm_locked
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ad_connect sys_cpu_clk axi_ddr_cntrl/ui_addn_clk_0
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ad_connect sys_200m_clk axi_ddr_cntrl/ui_clk
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ad_connect sys_cpu_resetn axi_ddr_cntrl/aresetn
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_200m_reset sys_200m_rstgen/peripheral_reset
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ad_connect sys_200m_resetn sys_200m_rstgen/peripheral_aresetn
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# generic system clocks pointers
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set sys_cpu_clk [get_bd_nets sys_cpu_clk]
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set sys_dma_clk [get_bd_nets sys_200m_clk]
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set sys_iodelay_clk [get_bd_nets sys_200m_clk]
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set sys_cpu_reset [get_bd_nets sys_cpu_reset]
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set sys_cpu_resetn [get_bd_nets sys_cpu_resetn]
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set sys_dma_reset [get_bd_nets sys_200m_reset]
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set sys_dma_resetn [get_bd_nets sys_200m_resetn]
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set sys_iodelay_reset [get_bd_nets sys_200m_reset]
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set sys_iodelay_resetn [get_bd_nets sys_200m_resetn]
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_200m_clk sys_200m_rstgen/slowest_sync_clk
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ad_connect sys_cpu_clk sys_mb/Clk
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ad_connect sys_cpu_clk sys_dlmb/LMB_Clk
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ad_connect sys_cpu_clk sys_ilmb/LMB_Clk
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ad_connect sys_cpu_clk sys_dlmb_cntlr/LMB_Clk
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ad_connect sys_cpu_clk sys_ilmb_cntlr/LMB_Clk
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ad_connect sys_cpu_clk axi_spi/ext_spi_clk
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# defaults (interrupts)
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ad_connect sys_concat_intc/In0 axi_timer/interrupt
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ad_connect sys_concat_intc/In1 GND
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ad_connect sys_concat_intc/In2 GND
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ad_connect sys_concat_intc/In3 GND
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ad_connect sys_concat_intc/In4 axi_uart/interrupt
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ad_connect sys_concat_intc/In5 GND
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ad_connect sys_concat_intc/In6 GND
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ad_connect sys_concat_intc/In7 GND
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ad_connect sys_concat_intc/In8 GND
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ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt
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ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt
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ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt
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ad_connect sys_concat_intc/In12 GND
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ad_connect sys_concat_intc/In13 GND
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ad_connect sys_concat_intc/In14 GND
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ad_connect sys_concat_intc/In15 GND
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# defaults (external interface)
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ad_connect sys_rst sys_rstgen/ext_reset_in
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ad_connect sys_rst axi_ddr_cntrl/sys_rst
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ad_connect sys_200m_rst sys_200m_rstgen/ext_reset_in
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ad_connect sys_200m_rst axi_ddr_cntrl/ui_clk_sync_rst
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ad_connect sys_clk_p axi_ddr_cntrl/sys_clk_p
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ad_connect sys_clk_n axi_ddr_cntrl/sys_clk_n
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ad_connect ddr3 axi_ddr_cntrl/DDR3
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ad_connect uart_sin axi_uart/rx
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ad_connect uart_sout axi_uart/tx
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ad_connect iic_main axi_iic_main/iic
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ad_connect spi_csn_i axi_spi/ss_i
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ad_connect spi_csn_o axi_spi/ss_o
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ad_connect spi_clk_i axi_spi/sck_i
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ad_connect spi_clk_o axi_spi/sck_o
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ad_connect spi_sdo_i axi_spi/io0_i
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ad_connect spi_sdo_o axi_spi/io0_o
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ad_connect spi_sdi_i axi_spi/io1_i
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ad_connect gpio0_i axi_gpio/gpio_io_i
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ad_connect gpio0_o axi_gpio/gpio_io_o
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ad_connect gpio0_t axi_gpio/gpio_io_t
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ad_connect gpio1_i axi_gpio/gpio2_io_i
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ad_connect gpio1_o axi_gpio/gpio2_io_o
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ad_connect gpio1_t axi_gpio/gpio2_io_t
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# linear_flash
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ad_connect axi_linear_flash/EMC_INTF linear_flash
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ad_connect sys_cpu_resetn axi_linear_flash/s_axi_aresetn
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ad_connect sys_cpu_clk axi_linear_flash/s_axi_aclk
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ad_connect sys_cpu_clk axi_linear_flash/rdclk
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# address mapping
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ad_cpu_interconnect 0x41400000 sys_mb_debug
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ad_cpu_interconnect 0x41200000 axi_intc
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ad_cpu_interconnect 0x41C00000 axi_timer
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ad_cpu_interconnect 0x40600000 axi_uart
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ad_cpu_interconnect 0x41600000 axi_iic_main
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ad_cpu_interconnect 0x45000000 axi_sysid_0
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ad_cpu_interconnect 0x40000000 axi_gpio
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ad_cpu_interconnect 0x44A70000 axi_spi
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ad_cpu_interconnect 0x60000000 axi_linear_flash
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ad_mem_hp0_interconnect sys_200m_clk axi_ddr_cntrl/S_AXI
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ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_DC
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ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_IC
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create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \
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[get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr
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create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \
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[get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr
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set_property range 0x2000000 [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_linear_flash}]
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@ -0,0 +1,55 @@
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# constraints
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set_property -dict {PACKAGE_PIN AV40 IOSTANDARD LVCMOS18} [get_ports sys_rst]
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# clocks
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set_property -dict {PACKAGE_PIN H19 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_p]
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set_property -dict {PACKAGE_PIN G18 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_n]
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# uart
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set_property -dict {PACKAGE_PIN AU33 IOSTANDARD LVCMOS18} [get_ports uart_sin]
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set_property -dict {PACKAGE_PIN AU36 IOSTANDARD LVCMOS18} [get_ports uart_sout]
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# fan
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set_property -dict {PACKAGE_PIN BA37 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
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set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[0]] ; ## GPIO_DIP_SW0
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set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[1]] ; ## GPIO_DIP_SW1
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set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[2]] ; ## GPIO_DIP_SW2
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set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[3]] ; ## GPIO_DIP_SW3
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set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[4]] ; ## GPIO_DIP_SW4
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set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[5]] ; ## GPIO_DIP_SW5
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set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[6]] ; ## GPIO_DIP_SW6
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set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[7]] ; ## GPIO_DIP_SW7
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set_property -dict {PACKAGE_PIN AR40 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[8]] ; ## GPIO_SW_N
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set_property -dict {PACKAGE_PIN AU38 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[9]] ; ## GPIO_SW_E
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set_property -dict {PACKAGE_PIN AP40 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[10]] ; ## GPIO_SW_S
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set_property -dict {PACKAGE_PIN AW40 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[11]] ; ## GPIO_SW_W
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set_property -dict {PACKAGE_PIN AV39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_i[12]] ; ## GPIO_SW_C
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set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[0]] ; ## GPIO_LED_0_LS
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set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[1]] ; ## GPIO_LED_1_LS
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set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[2]] ; ## GPIO_LED_2_LS
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set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[3]] ; ## GPIO_LED_3_LS
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set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[4]] ; ## GPIO_LED_4_LS
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set_property -dict {PACKAGE_PIN AP41 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[5]] ; ## GPIO_LED_5_LS
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set_property -dict {PACKAGE_PIN AP42 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6_LS
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set_property -dict {PACKAGE_PIN AU39 IOSTANDARD LVCMOS18} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7_LS
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# iic
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set_property -dict {PACKAGE_PIN AY42 IOSTANDARD LVCMOS18} [get_ports iic_rstn]
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set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl]
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set_property -dict {PACKAGE_PIN AU32 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda]
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#Setting the Configuration Bank Voltage Select
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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# Create SPI clock
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create_generated_clock -name spi_clk \
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-source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \
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-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o]
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@ -0,0 +1,210 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<Project NoOfControllers="1">
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<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
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<ModuleName>system_axi_ddr_cntrl_0</ModuleName>
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<dci_inouts_inputs>1</dci_inouts_inputs>
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<dci_inputs>1</dci_inputs>
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<Debug_En>OFF</Debug_En>
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<DataDepth_En>1024</DataDepth_En>
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<LowPower_En>ON</LowPower_En>
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<XADC_En>Enabled</XADC_En>
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<TargetFPGA>xc7vx690t-ffg1761/-2</TargetFPGA>
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<Version>4.2</Version>
|
||||
<SystemClock>Differential</SystemClock>
|
||||
<ReferenceClock>Use System Clock</ReferenceClock>
|
||||
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
|
||||
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||
<InternalVref>0</InternalVref>
|
||||
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||
<dci_cascade>0</dci_cascade>
|
||||
<Controller number="0">
|
||||
<MemoryDevice>DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9</MemoryDevice>
|
||||
<TimePeriod>1250</TimePeriod>
|
||||
<VccAuxIO>2.0V</VccAuxIO>
|
||||
<PHYRatio>4:1</PHYRatio>
|
||||
<InputClkFreq>200</InputClkFreq>
|
||||
<UIExtraClocks>1</UIExtraClocks>
|
||||
<MMCM_VCO>800</MMCM_VCO>
|
||||
<MMCMClkOut0> 8.000</MMCMClkOut0>
|
||||
<MMCMClkOut1>1</MMCMClkOut1>
|
||||
<MMCMClkOut2>1</MMCMClkOut2>
|
||||
<MMCMClkOut3>1</MMCMClkOut3>
|
||||
<MMCMClkOut4>1</MMCMClkOut4>
|
||||
<DataWidth>64</DataWidth>
|
||||
<DeepMemory>1</DeepMemory>
|
||||
<DataMask>1</DataMask>
|
||||
<ECC>Disabled</ECC>
|
||||
<Ordering>Normal</Ordering>
|
||||
<BankMachineCnt>4</BankMachineCnt>
|
||||
<CustomPart>FALSE</CustomPart>
|
||||
<NewPartName></NewPartName>
|
||||
<RowAddress>16</RowAddress>
|
||||
<ColAddress>10</ColAddress>
|
||||
<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||
<C0_MEM_SIZE>4294967296</C0_MEM_SIZE>
|
||||
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||
<PinSelection>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A20" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="B21" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="B17" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A15" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A21" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="F17" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="E17" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[15]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="B19" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="C20" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A19" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A17" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A16" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="D20" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="C18" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="D17" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="C19" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_addr[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="D21" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_ba[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="C21" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_ba[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="D18" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_ba[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="K17" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_cas_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="E18" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_ck_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="E19" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_ck_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="K19" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_cke[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="J17" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_cs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M13" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dm[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="K15" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dm[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="F12" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dm[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="A14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dm[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="C23" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dm[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="D25" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dm[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="C31" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dm[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="F31" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dm[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[15]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[16]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[17]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[18]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[19]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[20]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[21]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[22]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[23]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[24]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[25]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[26]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[27]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[28]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[29]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[30]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[31]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[32]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[33]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[34]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[35]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[36]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[37]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[38]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[39]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[40]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[41]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[42]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[43]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[44]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[45]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[46]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[47]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[48]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[49]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[50]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[51]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[52]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[53]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[54]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[55]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[56]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[57]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[58]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[59]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[60]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[61]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[62]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[63]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dq[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_n[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_n[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_n[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_n[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_n[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_n[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_n[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_p[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_p[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_p[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_p[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_p[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_p[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_dqs_p[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="H20" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_odt[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="E20" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_ras_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="LVCMOS15" PADName="P18" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_reset_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="F20" SLEW="FAST" VCCAUX_IO="HIGH" name="ddr3_we_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="LVCMOS18" PADName="AM39" SLEW="SLOW" VCCAUX_IO="" name="led[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="LVCMOS18" PADName="AN39" SLEW="SLOW" VCCAUX_IO="" name="led[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="LVCMOS18" PADName="AR37" SLEW="SLOW" VCCAUX_IO="" name="led[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="LVCMOS18" PADName="AT37" SLEW="SLOW" VCCAUX_IO="" name="led[3]"/>
|
||||
</PinSelection>
|
||||
<System_Clock>
|
||||
<Pin Bank="38" PADName="H19/G18(CC_P/N)" name="sys_clk_p/n"/>
|
||||
</System_Clock>
|
||||
<System_Control>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters tcke="5" tfaw="27" tras="34" trcd="13.91" trefi="7.8" trfc="260" trp="13.91" trrd="5" trtp="7.5" twtr="7.5"/>
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency">11</mrCasLatency>
|
||||
<mrMode name="Mode">Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset">No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/7</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/6</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)">0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable">Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency">8</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>AXI</PortInterface>
|
||||
<AXIParameters>
|
||||
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||
<C0_S_AXI_ADDR_WIDTH>32</C0_S_AXI_ADDR_WIDTH>
|
||||
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
|
||||
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
|
||||
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||
</AXIParameters>
|
||||
</Controller>
|
||||
|
||||
</Project>
|
||||
|
|
@ -129,6 +129,11 @@ proc adi_project {project_name {mode 0} {parameter_list {}} } {
|
|||
set device "xcvc1902-vsva2197-2MP-e-S"
|
||||
set board [lindex [lsearch -all -inline [get_board_parts] *vck190*] end]
|
||||
}
|
||||
if [regexp "_vc709$" $project_name] {
|
||||
set device "xc7vx690tffg1761-2"
|
||||
set board [lindex [lsearch -all -inline [get_board_parts] *vc709*] end]
|
||||
}
|
||||
|
||||
adi_project_create $project_name $mode $parameter_list $device $board
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue