From 1b06c74919e1e7259d7b814db13e54da20f4c8d1 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Thu, 27 Jan 2022 08:10:38 +0000 Subject: [PATCH] common/up_dac_common: Add manual sync request --- library/common/up_dac_common.v | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v index dd4a910f8..ebff7a505 100644 --- a/library/common/up_dac_common.v +++ b/library/common/up_dac_common.v @@ -66,6 +66,7 @@ module up_dac_common #( output dac_sync, output dac_ext_sync_arm, output dac_ext_sync_disarm, + output dac_ext_sync_manual_req, output dac_frame, output dac_clksel, output dac_par_type, @@ -130,6 +131,7 @@ module up_dac_common #( reg up_dac_sync = 'd0; reg up_dac_ext_sync_arm = 'd0; reg up_dac_ext_sync_disarm = 'd0; + reg up_dac_ext_sync_manual_req = 'd0; reg [4:0] up_dac_num_lanes = 'd0; reg up_dac_sdr_ddr_n = 'd0; reg up_dac_symb_op = 'd0; @@ -196,6 +198,7 @@ module up_dac_common #( up_dac_sync <= 'd0; up_dac_ext_sync_arm <= 'd0; up_dac_ext_sync_disarm <= 'd0; + up_dac_ext_sync_manual_req <= 'd0; up_dac_num_lanes <= 'd0; up_dac_sdr_ddr_n <= 'd0; up_dac_symb_op <= 'd0; @@ -245,6 +248,13 @@ module up_dac_common #( end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin up_dac_ext_sync_disarm <= up_wdata[2]; end + if (up_dac_ext_sync_manual_req == 1'b1) begin + if (up_xfer_done_s == 1'b1) begin + up_dac_ext_sync_manual_req <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin + up_dac_ext_sync_manual_req <= up_wdata[8]; + end if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin up_dac_sdr_ddr_n <= up_wdata[16]; up_dac_symb_op <= up_wdata[15]; @@ -423,7 +433,10 @@ module up_dac_common #( 7'h03: up_rdata_int <= CONFIG; 7'h07: up_rdata_int <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] 7'h10: up_rdata_int <= {29'd0, up_dac_clk_enb, up_mmcm_resetn, up_resetn}; - 7'h11: up_rdata_int <= {29'd0, up_dac_ext_sync_disarm, up_dac_ext_sync_arm, up_dac_sync}; + 7'h11: up_rdata_int <= {20'd0, + 3'b0, up_dac_ext_sync_manual_req, + 4'b0, + 1'b0, up_dac_ext_sync_disarm, up_dac_ext_sync_arm, up_dac_sync}; 7'h12: up_rdata_int <= {15'd0, up_dac_sdr_ddr_n, up_dac_symb_op, up_dac_symb_8_16b, 1'd0, up_dac_num_lanes, @@ -462,7 +475,7 @@ module up_dac_common #( // dac control & status - up_xfer_cntrl #(.DATA_WIDTH(34)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(35)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_dac_sdr_ddr_n, @@ -471,6 +484,7 @@ module up_dac_common #( up_dac_num_lanes, up_dac_ext_sync_arm, up_dac_ext_sync_disarm, + up_dac_ext_sync_manual_req, up_dac_sync, up_dac_clksel, up_dac_frame, @@ -489,6 +503,7 @@ module up_dac_common #( dac_num_lanes, dac_ext_sync_arm, dac_ext_sync_disarm, + dac_ext_sync_manual_req, dac_sync_s, dac_clksel, dac_frame_s,