From 18ab43b5a10d2e623b41916abeda5de9c88a4ce2 Mon Sep 17 00:00:00 2001 From: Nicola Corna Date: Fri, 8 Oct 2021 13:36:55 +0200 Subject: [PATCH] axi_hdmi_tx: Add UltraScale+ architecture to Verilog --- library/axi_hdmi_tx/axi_hdmi_tx.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index 3f4fad1bd..1e729e0a2 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -107,6 +107,7 @@ module axi_hdmi_tx #( localparam EMBEDDED_SYNC = (INTERFACE == "16_BIT_EMBEDDED_SYNC") ? 1 : 0; localparam XILINX_7SERIES = 1; localparam XILINX_ULTRASCALE = 2; + localparam XILINX_ULTRASCALE_PLUS = 3; localparam INTEL_5SERIES = 101; // reset and clocks @@ -302,7 +303,7 @@ module axi_hdmi_tx #( // hdmi output clock generate - if (FPGA_TECHNOLOGY == XILINX_ULTRASCALE) begin + if (FPGA_TECHNOLOGY == XILINX_ULTRASCALE || FPGA_TECHNOLOGY == XILINX_ULTRASCALE_PLUS) begin ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr ( .SR (1'b0), .D1 (~OUT_CLK_POLARITY),