ad9467_zed: Update project to the new framework.
Istvan Csomortani
parent
2d7bae2ba6
commit
1819a41ab5
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@ -1,228 +1,84 @@
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# ad9467
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# ad9467
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set adc_clk_in_p [create_bd_port -dir I adc_clk_in_p]
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set adc_clk_in_n [create_bd_port -dir I adc_clk_in_n]
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set adc_data_or_p [create_bd_port -dir I adc_data_or_p]
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set adc_data_or_n [create_bd_port -dir I adc_data_or_n]
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set adc_data_in_n [create_bd_port -dir I -from 7 -to 0 adc_data_in_n]
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set adc_data_in_p [create_bd_port -dir I -from 7 -to 0 adc_data_in_p]
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create_bd_port -dir I adc_clk_in_p
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create_bd_port -dir I adc_clk_in_n
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create_bd_port -dir I adc_data_or_p
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create_bd_port -dir I adc_data_or_n
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create_bd_port -dir I -from 7 -to 0 adc_data_in_n
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create_bd_port -dir I -from 7 -to 0 adc_data_in_p
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set spi_csn_i [create_bd_port -dir I spi_csn_i]
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if {$sys_zynq == 0} {
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set spi_csn_o [create_bd_port -dir O -from 1 -to 0 spi_csn_o]
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} else {
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set spi_csn_adc_o [create_bd_port -dir O spi_csn_adc_o]
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set spi_csn_clk_o [create_bd_port -dir O spi_csn_clk_o]
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}
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set spi_clk_i [create_bd_port -dir I spi_clk_i]
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set spi_clk_o [create_bd_port -dir O spi_clk_o]
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set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
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set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
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set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
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# adc peripheral
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# interrupts
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set ad9467_dma_irq [create_bd_port -dir O ad9467_dma_irq]
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if {$sys_zynq == 0} {
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set ad9467_spi_irq [create_bd_port -dir O ad9467_spi_irq]
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}
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set axi_ad9467 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9467:1.0 axi_ad9467]
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# adc peripheral
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set axi_ad9467_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9467_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9467_dma
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set axi_ad9467 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9467:1.0 axi_ad9467]
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# connections (ad9467)
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set axi_ad9467_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9467_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $axi_ad9467_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9467_dma
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ad_connect adc_clk_in_p axi_ad9467/adc_clk_in_p
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ad_connect adc_clk_in_n axi_ad9467/adc_clk_in_n
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ad_connect adc_data_in_n axi_ad9467/adc_data_in_n
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ad_connect adc_data_in_p axi_ad9467/adc_data_in_p
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ad_connect adc_data_or_p axi_ad9467/adc_or_in_p
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ad_connect adc_data_or_n axi_ad9467/adc_or_in_n
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_ad9467_dma
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}
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ad_connect axi_ad9467/adc_clk axi_ad9467_dma/fifo_wr_clk
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# spi
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ad_connect sys_200m_clk axi_ad9467/delay_clk
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if {$sys_zynq == 0} {
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set axi_ad9467_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad9467_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9467_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $axi_ad9467_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9467_spi
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} else {
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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}
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ad_connect axi_ad9467/adc_valid axi_ad9467_dma/fifo_wr_en
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ad_connect axi_ad9467/adc_data axi_ad9467_dma/fifo_wr_din
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ad_connect axi_ad9467/adc_dovf axi_ad9467_dma/fifo_wr_overflow
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# additions to default configuration
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# interconnect
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if {$sys_zynq == 0} {
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set_property -dict [list CONFIG.NUM_MI {10}] $axi_cpu_interconnect
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} else {
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set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect
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}
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ad_cpu_interconnect 0x44A00000 axi_ad9467
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ad_cpu_interconnect 0x44A30000 axi_ad9467_dma
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if {$sys_zynq == 0} {
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set_property -dict [list CONFIG.NUM_SI {9}] $axi_mem_interconnect
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}
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# memory inteconnect
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# clock for ila
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad9467_dma/m_dest_axi
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
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# interrupts
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set_property LEFT 31 [get_bd_ports GPIO_I]
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set_property LEFT 31 [get_bd_ports GPIO_O]
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set_property LEFT 31 [get_bd_ports GPIO_T]
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ad_cpu_interrupt ps-13 mb-12 axi_ad9467_dma/irq
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set sys_ila_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
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# ila (with fifo to prevent timing failure)
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connect_bd_net -net sys_ila_clk $sys_ila_clk_source
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} else {
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set ila_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 ila_clkgen]
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set_property -dict [list CONFIG.PRIM_IN_FREQ {200}] $ila_clkgen
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $ila_clkgen
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set_property -dict [list CONFIG.USE_LOCKED {false}] $ila_clkgen
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set_property -dict [list CONFIG.USE_RESET {false}] $ila_clkgen
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set ila_fifo [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 ila_fifo]
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set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $ila_fifo
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set_property -dict [list CONFIG.Input_Data_Width {16}] $ila_fifo
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set_property -dict [list CONFIG.Input_Depth {128}] $ila_fifo
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set_property -dict [list CONFIG.Output_Data_Width {32}] $ila_fifo
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set_property -dict [list CONFIG.Overflow_Flag {true}] $ila_fifo
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set_property -dict [list CONFIG.Reset_Pin {false}] $ila_fifo
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connect_bd_net -net sys_200m_clk [get_bd_pins ila_clkgen/clk_in1]
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set ila_ad9467_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_ad9467_mon]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9467_mon
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_ad9467_mon
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {32}] $ila_ad9467_mon
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set sys_ila_clk_source [get_bd_pins ila_clkgen/clk_out1]
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connect_bd_net -net sys_ila_clk $sys_ila_clk_source
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}
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# connections (spi)
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ad_connect sys_200m_clk ila_ad9467_mon/clk
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ad_connect axi_ad9467/adc_clk ila_fifo/wr_clk
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ad_connect sys_200m_clk ila_fifo/rd_clk
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if {$sys_zynq == 0} {
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9467_spi/ss_i]
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9467_spi/ss_o]
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connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9467_spi/sck_i]
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connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9467_spi/sck_o]
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connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9467_spi/io0_i]
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connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9467_spi/io0_o]
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connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9467_spi/io1_i]
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ad_connect ila_fifo/din axi_ad9467/adc_data
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ad_connect ila_fifo/rd_en "VCC"
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ad_connect ila_fifo/wr_en "VCC"
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ad_connect ila_fifo/dout ila_ad9467_mon/probe0
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delete_bd_objs [get_bd_nets sys_concat_intc_din_2]
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delete_bd_objs [get_bd_ports unc_int2]
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} else {
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connect_bd_net -net spi_csn_adc [get_bd_ports spi_csn_adc_o] [get_bd_pins sys_ps7/SPI0_SS_O]
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connect_bd_net -net spi_csn_clk [get_bd_ports spi_csn_clk_o] [get_bd_pins sys_ps7/SPI0_SS1_O]
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
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connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
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connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
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connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
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connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
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connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
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}
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# connections (ad9467)
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connect_bd_net -net axi_ad9467_adc_clk_in_n [get_bd_ports adc_clk_in_p] [get_bd_pins axi_ad9467/adc_clk_in_p]
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connect_bd_net -net axi_ad9467_adc_clk_in_p [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9467/adc_clk_in_n]
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connect_bd_net -net axi_ad9467_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9467/adc_data_in_n]
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connect_bd_net -net axi_ad9467_adc_data_in_p [get_bd_ports adc_data_in_p] [get_bd_pins axi_ad9467/adc_data_in_p]
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connect_bd_net -net axi_ad9467_adc_data_or_p [get_bd_ports adc_data_or_p] [get_bd_pins axi_ad9467/adc_or_in_p]
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connect_bd_net -net axi_ad9467_adc_data_or_n [get_bd_ports adc_data_or_n] [get_bd_pins axi_ad9467/adc_or_in_n]
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set adc_250m_clk_source [get_bd_pins axi_ad9467/adc_clk]
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connect_bd_net -net adc_250m_clk [get_bd_pins axi_ad9467_dma/fifo_wr_clk] $adc_250m_clk_source
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467/delay_clk]
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connect_bd_net -net axi_ad9467_dma_dwr [get_bd_pins axi_ad9467/adc_valid] [get_bd_pins axi_ad9467_dma/fifo_wr_en]
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connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins axi_ad9467/adc_data] [get_bd_pins axi_ad9467_dma/fifo_wr_din]
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connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_dovf] [get_bd_pins axi_ad9467_dma/fifo_wr_overflow]
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connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_ports ad9467_dma_irq]
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# interconnect (cpu)
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] [get_bd_pins $sys_100m_clk_source]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] [get_bd_pins $sys_100m_clk_source]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] [get_bd_pins $sys_100m_resetn_source]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] [get_bd_pins $sys_100m_resetn_source]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9467/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9467_dma/s_axi_aclk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_dma/s_axi_aresetn]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9467_dma/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9467/s_axi]
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if {$sys_zynq == 0} {
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9467_spi/axi_lite]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9467_spi/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9467_spi/ext_spi_clk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_spi/s_axi_aresetn]
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connect_bd_net -net axi_ad9467_spi_irq [get_bd_pins axi_ad9467_spi/ip2intc_irpt] [get_bd_ports ad9467_spi_irq]
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}
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# interconnect (mem/adc)
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if {$sys_zynq == 0} {
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connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9467_dma/m_dest_axi]
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_200m_clk_source
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_200m_resetn_source
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9467_dma/m_dest_axi_aresetn]
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} else {
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connect_bd_intf_net -intf_net axi_ad9467_dma_data [get_bd_intf_pins axi_ad9467_dma/m_dest_axi] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
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connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_dma/m_dest_axi_aresetn]
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467_dma/m_dest_axi_aclk]
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}
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# ila (with fifo to prevent timing failure)
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set ila_fifo [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 ila_fifo]
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set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $ila_fifo
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set_property -dict [list CONFIG.Input_Data_Width {16}] $ila_fifo
|
||||
set_property -dict [list CONFIG.Input_Depth {128}] $ila_fifo
|
||||
set_property -dict [list CONFIG.Output_Data_Width {32}] $ila_fifo
|
||||
set_property -dict [list CONFIG.Overflow_Flag {true}] $ila_fifo
|
||||
set_property -dict [list CONFIG.Reset_Pin {false}] $ila_fifo
|
||||
|
||||
set ila_ad9467_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_ad9467_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9467_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_ad9467_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {32}] $ila_ad9467_mon
|
||||
|
||||
set ila_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 ila_constant_1]
|
||||
|
||||
connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins ila_fifo/din] [get_bd_pins axi_ad9467/adc_ddata]
|
||||
connect_bd_net -net adc_250m_clk [get_bd_pins axi_ad9467/adc_clk] [get_bd_pins ila_fifo/wr_clk]
|
||||
connect_bd_net -net sys_ila_clk [get_bd_pins ila_fifo/rd_clk] [get_bd_pins ila_ad9467_mon/clk]
|
||||
connect_bd_net -net xlconstant_0_const [get_bd_pins ila_fifo/rd_en] [get_bd_pins ila_fifo/wr_en] [get_bd_pins ila_constant_1/dout]
|
||||
|
||||
connect_bd_net -net ila_fifo_dout [get_bd_pins ila_fifo/dout] [get_bd_pins ila_ad9467_mon/probe0]
|
||||
|
||||
# address mapping
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9467/s_axi/axi_lite] SEG_data_ad9467_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9467_dma/s_axi/axi_lite] SEG_data_ad9467_dma
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9467_spi/axi_lite/Reg] SEG_data_ad9467_spi
|
||||
}
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9467_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
} else {
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9467_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
# load script
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
set project_name ad9467_fmc_zed
|
||||
|
||||
|
|
|
|||
|
|
@ -40,28 +40,28 @@
|
|||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
ddr_addr,
|
||||
ddr_ba,
|
||||
ddr_cas_n,
|
||||
ddr_ck_n,
|
||||
ddr_ck_p,
|
||||
ddr_cke,
|
||||
ddr_cs_n,
|
||||
ddr_dm,
|
||||
ddr_dq,
|
||||
ddr_dqs_n,
|
||||
ddr_dqs_p,
|
||||
ddr_odt,
|
||||
ddr_ras_n,
|
||||
ddr_reset_n,
|
||||
ddr_we_n,
|
||||
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
fixed_io_ddr_vrn,
|
||||
fixed_io_ddr_vrp,
|
||||
fixed_io_mio,
|
||||
fixed_io_ps_clk,
|
||||
fixed_io_ps_porb,
|
||||
fixed_io_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
|
|
@ -98,29 +98,29 @@ module system_top (
|
|||
spi_sdio
|
||||
);
|
||||
|
||||
inout [14:0] DDR_addr;
|
||||
inout [ 2:0] DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [ 3:0] DDR_dm;
|
||||
inout [31:0] DDR_dq;
|
||||
inout [ 3:0] DDR_dqs_n;
|
||||
inout [ 3:0] DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
inout [14:0] ddr_addr;
|
||||
inout [ 2:0] ddr_ba;
|
||||
inout ddr_cas_n;
|
||||
inout ddr_ck_n;
|
||||
inout ddr_ck_p;
|
||||
inout ddr_cke;
|
||||
inout ddr_cs_n;
|
||||
inout [ 3:0] ddr_dm;
|
||||
inout [31:0] ddr_dq;
|
||||
inout [ 3:0] ddr_dqs_n;
|
||||
inout [ 3:0] ddr_dqs_p;
|
||||
inout ddr_odt;
|
||||
inout ddr_ras_n;
|
||||
inout ddr_reset_n;
|
||||
inout ddr_we_n;
|
||||
|
||||
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0] FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
inout fixed_io_ddr_vrn;
|
||||
inout fixed_io_ddr_vrp;
|
||||
inout [53:0] fixed_io_mio;
|
||||
inout fixed_io_ps_clk;
|
||||
inout fixed_io_ps_porb;
|
||||
inout fixed_io_ps_srstb;
|
||||
|
||||
inout [31:0] gpio_bd;
|
||||
|
||||
|
|
@ -161,9 +161,9 @@ inout spi_sdio;
|
|||
wire [ 1:0] spi_csn;
|
||||
wire spi_miso;
|
||||
wire spi_mosi;
|
||||
wire [31:0] gpio_i;
|
||||
wire [31:0] gpio_o;
|
||||
wire [31:0] gpio_t;
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
|
|
@ -171,8 +171,6 @@ wire [ 1:0] iic_mux_sda_i_s;
|
|||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
|
||||
wire [15:0] ps_intrs;
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_gpio (
|
||||
|
|
@ -205,30 +203,30 @@ ad9467_spi i_spi (
|
|||
);
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR_addr(DDR_addr),
|
||||
.DDR_ba(DDR_ba),
|
||||
.DDR_cas_n(DDR_cas_n),
|
||||
.DDR_ck_n(DDR_ck_n),
|
||||
.DDR_ck_p(DDR_ck_p),
|
||||
.DDR_cke(DDR_cke),
|
||||
.DDR_cs_n(DDR_cs_n),
|
||||
.DDR_dm(DDR_dm),
|
||||
.DDR_dq(DDR_dq),
|
||||
.DDR_dqs_n(DDR_dqs_n),
|
||||
.DDR_dqs_p(DDR_dqs_p),
|
||||
.DDR_odt(DDR_odt),
|
||||
.DDR_ras_n(DDR_ras_n),
|
||||
.DDR_reset_n(DDR_reset_n),
|
||||
.DDR_we_n(DDR_we_n),
|
||||
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio (FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
||||
.GPIO_I (gpio_i),
|
||||
.GPIO_O (gpio_o),
|
||||
.GPIO_T (gpio_t),
|
||||
.ddr_addr(ddr_addr),
|
||||
.ddr_ba(ddr_ba),
|
||||
.ddr_cas_n(ddr_cas_n),
|
||||
.ddr_ck_n(ddr_ck_n),
|
||||
.ddr_ck_p(ddr_ck_p),
|
||||
.ddr_cke(ddr_cke),
|
||||
.ddr_cs_n(ddr_cs_n),
|
||||
.ddr_dm(ddr_dm),
|
||||
.ddr_dq(ddr_dq),
|
||||
.ddr_dqs_n(ddr_dqs_n),
|
||||
.ddr_dqs_p(ddr_dqs_p),
|
||||
.ddr_odt(ddr_odt),
|
||||
.ddr_ras_n(ddr_ras_n),
|
||||
.ddr_reset_n(ddr_reset_n),
|
||||
.ddr_we_n(ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
|
|
@ -241,27 +239,24 @@ system_wrapper i_system_wrapper (
|
|||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_I (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_O (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_T (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_I (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_O (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_T (iic_mux_sda_t_s),
|
||||
.ps_intr_0 (ps_intrs[0]),
|
||||
.ps_intr_1 (ps_intrs[1]),
|
||||
.ps_intr_10 (ps_intrs[10]),
|
||||
.ps_intr_11 (ps_intrs[11]),
|
||||
.ps_intr_12 (ps_intrs[12]),
|
||||
.ps_intr_13 (ps_intrs[13]),
|
||||
.ps_intr_2 (ps_intrs[2]),
|
||||
.ps_intr_3 (ps_intrs[3]),
|
||||
.ps_intr_4 (ps_intrs[4]),
|
||||
.ps_intr_5 (ps_intrs[5]),
|
||||
.ps_intr_6 (ps_intrs[6]),
|
||||
.ps_intr_7 (ps_intrs[7]),
|
||||
.ps_intr_8 (ps_intrs[8]),
|
||||
.ps_intr_9 (ps_intrs[9]),
|
||||
.ad9467_dma_irq (ps_intrs[13]),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.ps_intr_12 (1'b0),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif),
|
||||
.adc_clk_in_n(adc_clk_in_n),
|
||||
|
|
@ -270,14 +265,14 @@ system_wrapper i_system_wrapper (
|
|||
.adc_data_in_p(adc_data_in_p),
|
||||
.adc_data_or_n(adc_data_or_n),
|
||||
.adc_data_or_p(adc_data_or_p),
|
||||
.spi_clk_i(1'b0),
|
||||
.spi_clk_o(spi_clk),
|
||||
.spi_csn_i(1'b1),
|
||||
.spi_csn_adc_o(spi_csn[0]),
|
||||
.spi_csn_clk_o(spi_csn[1]),
|
||||
.spi_sdi_i(spi_miso),
|
||||
.spi_sdo_i(1'b0),
|
||||
.spi_sdo_o(spi_mosi));
|
||||
.spi0_clk_i(1'b0),
|
||||
.spi0_clk_o(spi_clk),
|
||||
.spi0_csn_i(1'b1),
|
||||
.spi0_csn_0_o(spi_csn[0]),
|
||||
.spi0_csn_1_o(spi_csn[1]),
|
||||
.spi0_sdi_i(spi_miso),
|
||||
.spi0_sdo_i(1'b0),
|
||||
.spi0_sdo_o(spi_mosi));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue