daq2: daq2_qsys.tcl: Convert to ADI JESD204
Convert the DAQ2 project for Intel/Altera platforms to the ADI JESD204 framework. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
parent
ce88b8ba91
commit
17d3e3c64b
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@ -22,9 +22,7 @@ M_DEPS += ../../scripts/adi_project_alt.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
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M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
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M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
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M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
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M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
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M_DEPS += ../../../library/altera/adi_jesd204/adi_jesd204_hw.tcl
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M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
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M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
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M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
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@ -33,6 +31,9 @@ M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc
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M_DEPS += ../../../library/altera/common/up_rst_constr.sdc
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M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc
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M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc
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M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue.v
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M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl
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M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_hw.tcl
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M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
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M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
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M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
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@ -80,6 +81,44 @@ M_DEPS += ../../../library/common/up_dac_common.v
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M_DEPS += ../../../library/common/up_delay_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_status.v
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M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_common.v
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M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
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M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
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M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
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M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
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M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
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M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
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M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
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M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
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M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
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M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
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M_DEPS += ../../../library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
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M_DEPS += ../../../library/jesd204/jesd204_common/eof.v
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M_DEPS += ../../../library/jesd204/jesd204_common/lmfc.v
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M_DEPS += ../../../library/jesd204/jesd204_common/pipeline_stage.v
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M_DEPS += ../../../library/jesd204/jesd204_common/scrambler.v
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M_DEPS += ../../../library/jesd204/jesd204_rx/align_mux.v
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M_DEPS += ../../../library/jesd204/jesd204_rx/elastic_buffer.v
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M_DEPS += ../../../library/jesd204/jesd204_rx/ilas_monitor.v
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M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
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M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
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M_DEPS += ../../../library/jesd204/jesd204_rx/lane_latency_monitor.v
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M_DEPS += ../../../library/jesd204/jesd204_rx/rx.v
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M_DEPS += ../../../library/jesd204/jesd204_rx/rx_cgs.v
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M_DEPS += ../../../library/jesd204/jesd204_rx/rx_ctrl.v
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M_DEPS += ../../../library/jesd204/jesd204_rx/rx_lane.v
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M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/8b10b_decoder.v
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M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
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M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
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M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/pattern_align.v
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M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/8b10b_encoder.v
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M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
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M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
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M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
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M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
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M_DEPS += ../../../library/jesd204/jesd204_tx/tx.v
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M_DEPS += ../../../library/jesd204/jesd204_tx/tx_ctrl.v
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M_DEPS += ../../../library/jesd204/jesd204_tx/tx_lane.v
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M_DEPS += ../../../library/scripts/adi_env.tcl
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M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
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M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
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@ -91,6 +130,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_sync.v
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M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
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M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
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M_DEPS += ../../../library/util_cdc/sync_bits.v
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M_DEPS += ../../../library/util_cdc/sync_data.v
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M_DEPS += ../../../library/util_cdc/sync_event.v
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M_DEPS += ../../../library/util_cdc/sync_gray.v
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M_DEPS += ../../../library/util_cpack/util_cpack.v
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M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
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@ -1,11 +1,9 @@
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "3.000 ns" -name rx_ref_clk [get_ports {rx_ref_clk}]
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create_clock -period "3.000 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
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set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
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set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*]
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@ -14,62 +14,59 @@ set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
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set_location_assignment PIN_AJ8 -to rx_ref_clk ; ## B20 FMCA_GBTCLK1_M2C_P
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set_location_assignment PIN_AJ7 -to "rx_ref_clk(n)" ; ## B21 FMCA_GBTCLK1_M2C_N
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set_location_assignment PIN_AV5 -to rx_data[0] ; ## A10 FMCA_DP3_M2C_P
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set_location_assignment PIN_AV6 -to "rx_data[0](n)" ; ## A11 FMCA_DP3_M2C_N
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set_location_assignment PIN_AW7 -to rx_data[1] ; ## C06 FMCA_DP0_M2C_P
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set_location_assignment PIN_AW8 -to "rx_data[1](n)" ; ## C07 FMCA_DP0_M2C_N
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set_location_assignment PIN_AY5 -to rx_data[2] ; ## A06 FMCA_DP2_M2C_P
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set_location_assignment PIN_AY6 -to "rx_data[2](n)" ; ## A07 FMCA_DP2_M2C_N
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set_location_assignment PIN_BA7 -to rx_data[3] ; ## A02 FMCA_DP1_M2C_P
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set_location_assignment PIN_BA8 -to "rx_data[3](n)" ; ## A03 FMCA_DP1_M2C_N
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set_location_assignment PIN_AV5 -to rx_serial_data[0] ; ## A10 FMCA_DP3_M2C_P
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set_location_assignment PIN_AV6 -to "rx_serial_data[0](n)"; ## A11 FMCA_DP3_M2C_N
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set_location_assignment PIN_AW7 -to rx_serial_data[1] ; ## C06 FMCA_DP0_M2C_P
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set_location_assignment PIN_AW8 -to "rx_serial_data[1](n)"; ## C07 FMCA_DP0_M2C_N
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set_location_assignment PIN_AY5 -to rx_serial_data[2] ; ## A06 FMCA_DP2_M2C_P
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set_location_assignment PIN_AY6 -to "rx_serial_data[2](n)"; ## A07 FMCA_DP2_M2C_N
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set_location_assignment PIN_BA7 -to rx_serial_data[3] ; ## A02 FMCA_DP1_M2C_P
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set_location_assignment PIN_BA8 -to "rx_serial_data[3](n)"; ## A03 FMCA_DP1_M2C_N
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set_location_assignment PIN_AT10 -to rx_sync ; ## D08 FMCA_LA01_CC_P
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set_location_assignment PIN_AR11 -to "rx_sync(n)" ; ## D09 FMCA_LA01_CC_N
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set_location_assignment PIN_AR20 -to rx_sysref ; ## G09 FMCA_LA03_P
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set_location_assignment PIN_AR19 -to "rx_sysref(n)" ; ## G10 FMCA_LA03_N
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set_location_assignment PIN_AL8 -to tx_ref_clk ; ## D04 FMCA_GBTCLK0_M2C_P
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set_location_assignment PIN_AL7 -to "tx_ref_clk(n)" ; ## D05 FMCA_GBTCLK0_M2C_N
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set_location_assignment PIN_BC3 -to tx_data[0] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[0])
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set_location_assignment PIN_BC4 -to "tx_data[0](n)" ; ## A31 FMCA_DP3_C2M_N (tx_data_n[0])
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set_location_assignment PIN_BC7 -to tx_data[1] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[3])
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set_location_assignment PIN_BC8 -to "tx_data[1](n)" ; ## C03 FMCA_DP0_C2M_N (tx_data_n[3])
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set_location_assignment PIN_BB5 -to tx_data[2] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1])
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set_location_assignment PIN_BB6 -to "tx_data[2](n)" ; ## A27 FMCA_DP2_C2M_N (tx_data_n[1])
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set_location_assignment PIN_BD5 -to tx_data[3] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[2])
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set_location_assignment PIN_BD6 -to "tx_data[3](n)" ; ## A23 FMCA_DP1_C2M_N (tx_data_n[2])
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set_location_assignment PIN_BC3 -to tx_serial_data[0] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[0])
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set_location_assignment PIN_BC4 -to "tx_serial_data[0](n)"; ## A31 FMCA_DP3_C2M_N (tx_data_n[0])
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set_location_assignment PIN_BC7 -to tx_serial_data[1] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[3])
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set_location_assignment PIN_BC8 -to "tx_serial_data[1](n)"; ## C03 FMCA_DP0_C2M_N (tx_data_n[3])
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set_location_assignment PIN_BB5 -to tx_serial_data[2] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1])
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set_location_assignment PIN_BB6 -to "tx_serial_data[2](n)"; ## A27 FMCA_DP2_C2M_N (tx_data_n[1])
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set_location_assignment PIN_BD5 -to tx_serial_data[3] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[2])
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set_location_assignment PIN_BD6 -to "tx_serial_data[3](n)"; ## A23 FMCA_DP1_C2M_N (tx_data_n[2])
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set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_LA02_P
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set_location_assignment PIN_AT22 -to "tx_sync(n)" ; ## H08 FMCA_LA02_N
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set_location_assignment PIN_AN20 -to tx_sysref ; ## H10 FMCA_LA04_P
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set_location_assignment PIN_AP19 -to "tx_sysref(n)" ; ## H11 FMCA_LA04_N
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_data
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_ref_clk
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set_instance_assignment -name IO_STANDARD LVDS -to "rx_ref_clk(n)"
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data
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set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
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set_instance_assignment -name IO_STANDARD LVDS -to "rx_sync(n)"
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set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
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set_instance_assignment -name IO_STANDARD LVDS -to "rx_sysref(n)"
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_ref_clk
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set_instance_assignment -name IO_STANDARD LVDS -to "tx_ref_clk(n)"
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data
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set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
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set_instance_assignment -name IO_STANDARD LVDS -to "tx_sync(n)"
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
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set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
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set_instance_assignment -name IO_STANDARD LVDS -to "tx_sysref(n)"
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3]
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# Merge RX and TX into single transceiver
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for {set i 0} {$i < 4} {incr i} {
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}]
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}
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# gpio
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@ -97,4 +94,3 @@ set_location_assignment PIN_AW13 -to spi_sdio ; ## D14 FMCA_LA09_
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set_location_assignment PIN_AN19 -to spi_dir ; ## G13 FMCA_LA08_N
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execute_flow -compile
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@ -82,11 +82,11 @@ module system_top (
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input rx_ref_clk,
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input rx_sysref,
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output rx_sync,
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input [ 3:0] rx_data,
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input [ 3:0] rx_serial_data,
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input tx_ref_clk,
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input tx_sysref,
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input tx_sync,
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output [ 3:0] tx_data,
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output [ 3:0] tx_serial_data,
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// gpio
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@ -171,10 +171,7 @@ module system_top (
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assign gpio_bd_o = gpio_o[15:0];
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system_bd i_system_bd (
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.rx_data_0_rx_serial_data (rx_data[0]),
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.rx_data_1_rx_serial_data (rx_data[1]),
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.rx_data_2_rx_serial_data (rx_data[2]),
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.rx_data_3_rx_serial_data (rx_data[3]),
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.rx_serial_data_rx_serial_data (rx_serial_data),
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.rx_ref_clk_clk (rx_ref_clk),
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.rx_sync_export (rx_sync),
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.rx_sysref_export (rx_sysref),
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@ -213,10 +210,7 @@ module system_top (
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.sys_spi_MOSI (spi_mosi_s),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn_s),
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.tx_data_0_tx_serial_data (tx_data[0]),
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.tx_data_1_tx_serial_data (tx_data[1]),
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.tx_data_2_tx_serial_data (tx_data[2]),
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.tx_data_3_tx_serial_data (tx_data[3]),
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.tx_serial_data_tx_serial_data (tx_serial_data),
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.tx_ref_clk_clk (tx_ref_clk),
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.tx_sync_export (tx_sync),
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.tx_sysref_export (tx_sysref));
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@ -1,57 +1,32 @@
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# ad9144-xcvr
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add_instance avl_ad9144_xcvr avl_adxcvr
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set_instance_parameter_value avl_ad9144_xcvr {ID} {0}
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set_instance_parameter_value avl_ad9144_xcvr {TX_OR_RX_N} {1}
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set_instance_parameter_value avl_ad9144_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
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set_instance_parameter_value avl_ad9144_xcvr {LANE_RATE} {10000.0}
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set_instance_parameter_value avl_ad9144_xcvr {REFCLK_FREQUENCY} {500.0}
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||||
set_instance_parameter_value avl_ad9144_xcvr {NUM_OF_LANES} {4}
|
||||
set_instance_parameter_value avl_ad9144_xcvr {NUM_OF_CONVS} {2}
|
||||
set_instance_parameter_value avl_ad9144_xcvr {FRM_BCNT} {1}
|
||||
set_instance_parameter_value avl_ad9144_xcvr {FRM_SCNT} {1}
|
||||
set_instance_parameter_value avl_ad9144_xcvr {MF_FCNT} {32}
|
||||
set_instance_parameter_value avl_ad9144_xcvr {HD} {1}
|
||||
set_instance_parameter_value avl_ad9144_xcvr {TX_LANE_MAP} {0 3 1 2}
|
||||
add_instance ad9144_jesd204 adi_jesd204
|
||||
set_instance_parameter_value ad9144_jesd204 {ID} {0}
|
||||
set_instance_parameter_value ad9144_jesd204 {TX_OR_RX_N} {1}
|
||||
set_instance_parameter_value ad9144_jesd204 {LANE_RATE} {10000}
|
||||
set_instance_parameter_value ad9144_jesd204 {REFCLK_FREQUENCY} {333.333333}
|
||||
set_instance_parameter_value ad9144_jesd204 {LANE_MAP} {0 3 1 2}
|
||||
set_instance_parameter_value ad9144_jesd204 {SOFT_PCS} {true}
|
||||
|
||||
add_connection sys_clk.clk avl_ad9144_xcvr.sys_clk
|
||||
add_connection sys_clk.clk_reset avl_ad9144_xcvr.sys_resetn
|
||||
add_connection sys_clk.clk ad9144_jesd204.sys_clk
|
||||
add_connection sys_clk.clk_reset ad9144_jesd204.sys_resetn
|
||||
add_interface tx_ref_clk clock sink
|
||||
set_interface_property tx_ref_clk EXPORT_OF avl_ad9144_xcvr.ref_clk
|
||||
add_interface tx_data_0 conduit end
|
||||
set_interface_property tx_data_0 EXPORT_OF avl_ad9144_xcvr.tx_data_0
|
||||
add_interface tx_data_1 conduit end
|
||||
set_interface_property tx_data_1 EXPORT_OF avl_ad9144_xcvr.tx_data_1
|
||||
add_interface tx_data_2 conduit end
|
||||
set_interface_property tx_data_2 EXPORT_OF avl_ad9144_xcvr.tx_data_2
|
||||
add_interface tx_data_3 conduit end
|
||||
set_interface_property tx_data_3 EXPORT_OF avl_ad9144_xcvr.tx_data_3
|
||||
set_interface_property tx_ref_clk EXPORT_OF ad9144_jesd204.ref_clk
|
||||
add_interface tx_serial_data conduit end
|
||||
set_interface_property tx_serial_data EXPORT_OF ad9144_jesd204.serial_data
|
||||
add_interface tx_sysref conduit end
|
||||
set_interface_property tx_sysref EXPORT_OF avl_ad9144_xcvr.sysref
|
||||
set_interface_property tx_sysref EXPORT_OF ad9144_jesd204.sysref
|
||||
add_interface tx_sync conduit end
|
||||
set_interface_property tx_sync EXPORT_OF avl_ad9144_xcvr.sync
|
||||
|
||||
# ad9144-xcvr
|
||||
|
||||
add_instance axi_ad9144_xcvr axi_adxcvr
|
||||
set_instance_parameter_value axi_ad9144_xcvr {ID} {0}
|
||||
set_instance_parameter_value axi_ad9144_xcvr {TX_OR_RX_N} {1}
|
||||
set_instance_parameter_value axi_ad9144_xcvr {NUM_OF_LANES} {4}
|
||||
|
||||
add_connection sys_clk.clk axi_ad9144_xcvr.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_ad9144_xcvr.s_axi_reset
|
||||
add_connection axi_ad9144_xcvr.if_up_rst avl_ad9144_xcvr.rst
|
||||
add_connection avl_ad9144_xcvr.ready axi_ad9144_xcvr.ready
|
||||
add_connection axi_ad9144_xcvr.core_pll_locked avl_ad9144_xcvr.core_pll_locked
|
||||
set_interface_property tx_sync EXPORT_OF ad9144_jesd204.sync
|
||||
|
||||
# ad9144-core
|
||||
|
||||
add_instance axi_ad9144_core axi_ad9144
|
||||
set_instance_parameter_value axi_ad9144_core {QUAD_OR_DUAL_N} {0}
|
||||
|
||||
add_connection avl_ad9144_xcvr.core_clk axi_ad9144_core.if_tx_clk
|
||||
add_connection axi_ad9144_core.if_tx_data avl_ad9144_xcvr.ip_data
|
||||
add_connection ad9144_jesd204.link_clk axi_ad9144_core.if_tx_clk
|
||||
add_connection axi_ad9144_core.if_tx_data ad9144_jesd204.link_data
|
||||
add_connection sys_clk.clk_reset axi_ad9144_core.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9144_core.s_axi_clock
|
||||
|
||||
|
|
@ -61,7 +36,7 @@ add_instance util_ad9144_upack util_upack
|
|||
set_instance_parameter_value util_ad9144_upack {CHANNEL_DATA_WIDTH} {64}
|
||||
set_instance_parameter_value util_ad9144_upack {NUM_OF_CHANNELS} {2}
|
||||
|
||||
add_connection avl_ad9144_xcvr.core_clk util_ad9144_upack.if_dac_clk
|
||||
add_connection ad9144_jesd204.link_clk util_ad9144_upack.if_dac_clk
|
||||
add_connection axi_ad9144_core.dac_ch_0 util_ad9144_upack.dac_ch_0
|
||||
add_connection axi_ad9144_core.dac_ch_1 util_ad9144_upack.dac_ch_1
|
||||
|
||||
|
|
@ -74,7 +49,7 @@ set_instance_parameter_value axi_ad9144_dma {DMA_2D_TRANSFER} {0}
|
|||
set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_DEST} {2}
|
||||
set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_SRC} {0}
|
||||
|
||||
add_connection avl_ad9144_xcvr.core_clk axi_ad9144_dma.if_fifo_rd_clk
|
||||
add_connection ad9144_jesd204.link_clk axi_ad9144_dma.if_fifo_rd_clk
|
||||
add_connection util_ad9144_upack.if_dac_valid axi_ad9144_dma.if_fifo_rd_en
|
||||
add_connection util_ad9144_upack.if_dac_data axi_ad9144_dma.if_fifo_rd_dout
|
||||
add_connection axi_ad9144_dma.if_fifo_rd_underflow axi_ad9144_core.if_dac_dunf
|
||||
|
|
@ -85,56 +60,32 @@ add_connection sys_dma_clk.clk axi_ad9144_dma.m_src_axi_clock
|
|||
|
||||
# ad9680-xcvr
|
||||
|
||||
add_instance avl_ad9680_xcvr avl_adxcvr
|
||||
set_instance_parameter_value avl_ad9680_xcvr {ID} {1}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {TX_OR_RX_N} {0}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {LANE_RATE} {10000.0}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {REFCLK_FREQUENCY} {500.0}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_LANES} {4}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_CONVS} {2}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {FRM_BCNT} {1}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {FRM_SCNT} {1}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {MF_FCNT} {32}
|
||||
set_instance_parameter_value avl_ad9680_xcvr {HD} {1}
|
||||
add_instance ad9680_jesd204 adi_jesd204
|
||||
set_instance_parameter_value ad9680_jesd204 {ID} {1}
|
||||
set_instance_parameter_value ad9680_jesd204 {TX_OR_RX_N} {0}
|
||||
set_instance_parameter_value ad9680_jesd204 {LANE_RATE} {10000.0}
|
||||
set_instance_parameter_value ad9680_jesd204 {REFCLK_FREQUENCY} {333.333333}
|
||||
set_instance_parameter_value ad9680_jesd204 {NUM_OF_LANES} {4}
|
||||
set_instance_parameter_value ad9680_jesd204 {SOFT_PCS} {true}
|
||||
|
||||
add_connection sys_clk.clk avl_ad9680_xcvr.sys_clk
|
||||
add_connection sys_clk.clk_reset avl_ad9680_xcvr.sys_resetn
|
||||
add_connection sys_clk.clk ad9680_jesd204.sys_clk
|
||||
add_connection sys_clk.clk_reset ad9680_jesd204.sys_resetn
|
||||
add_interface rx_ref_clk clock sink
|
||||
set_interface_property rx_ref_clk EXPORT_OF avl_ad9680_xcvr.ref_clk
|
||||
add_interface rx_data_0 conduit end
|
||||
set_interface_property rx_data_0 EXPORT_OF avl_ad9680_xcvr.rx_data_0
|
||||
add_interface rx_data_1 conduit end
|
||||
set_interface_property rx_data_1 EXPORT_OF avl_ad9680_xcvr.rx_data_1
|
||||
add_interface rx_data_2 conduit end
|
||||
set_interface_property rx_data_2 EXPORT_OF avl_ad9680_xcvr.rx_data_2
|
||||
add_interface rx_data_3 conduit end
|
||||
set_interface_property rx_data_3 EXPORT_OF avl_ad9680_xcvr.rx_data_3
|
||||
set_interface_property rx_ref_clk EXPORT_OF ad9680_jesd204.ref_clk
|
||||
add_interface rx_serial_data conduit end
|
||||
set_interface_property rx_serial_data EXPORT_OF ad9680_jesd204.serial_data
|
||||
add_interface rx_sysref conduit end
|
||||
set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref
|
||||
set_interface_property rx_sysref EXPORT_OF ad9680_jesd204.sysref
|
||||
add_interface rx_sync conduit end
|
||||
set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync
|
||||
|
||||
# ad9680-xcvr
|
||||
|
||||
add_instance axi_ad9680_xcvr axi_adxcvr
|
||||
set_instance_parameter_value axi_ad9680_xcvr {ID} {1}
|
||||
set_instance_parameter_value axi_ad9680_xcvr {TX_OR_RX_N} {0}
|
||||
set_instance_parameter_value axi_ad9680_xcvr {NUM_OF_LANES} {4}
|
||||
|
||||
add_connection sys_clk.clk axi_ad9680_xcvr.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset
|
||||
add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst
|
||||
add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready
|
||||
add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked
|
||||
set_interface_property rx_sync EXPORT_OF ad9680_jesd204.sync
|
||||
|
||||
# ad9680
|
||||
|
||||
add_instance axi_ad9680_core axi_ad9680
|
||||
|
||||
add_connection avl_ad9680_xcvr.core_clk axi_ad9680_core.if_rx_clk
|
||||
add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof
|
||||
add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data
|
||||
add_connection ad9680_jesd204.link_clk axi_ad9680_core.if_rx_clk
|
||||
add_connection ad9680_jesd204.link_sof axi_ad9680_core.if_rx_sof
|
||||
add_connection ad9680_jesd204.link_data axi_ad9680_core.if_rx_data
|
||||
add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
|
||||
|
||||
|
|
@ -145,8 +96,7 @@ set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64}
|
|||
set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
|
||||
|
||||
add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst
|
||||
add_connection sys_dma_clk.clk_reset util_ad9680_cpack.if_adc_rst
|
||||
add_connection avl_ad9680_xcvr.core_clk util_ad9680_cpack.if_adc_clk
|
||||
add_connection ad9680_jesd204.link_clk util_ad9680_cpack.if_adc_clk
|
||||
add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
|
||||
add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
|
||||
|
||||
|
|
@ -158,7 +108,7 @@ set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128}
|
|||
set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
|
||||
|
||||
add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
|
||||
add_connection avl_ad9680_xcvr.core_clk ad9680_adcfifo.if_adc_clk
|
||||
add_connection ad9680_jesd204.link_clk ad9680_adcfifo.if_adc_clk
|
||||
add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr
|
||||
add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata
|
||||
add_connection sys_dma_clk.clk ad9680_adcfifo.if_dma_clk
|
||||
|
|
@ -189,36 +139,20 @@ add_connection sys_dma_clk.clk axi_ad9680_dma.m_dest_axi_clock
|
|||
|
||||
# reconfig sharing
|
||||
|
||||
add_instance avl_adxcfg_0 avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n
|
||||
add_connection avl_adxcfg_0.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_0
|
||||
add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0
|
||||
|
||||
add_instance avl_adxcfg_1 avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n
|
||||
add_connection avl_adxcfg_1.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_1
|
||||
add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1
|
||||
|
||||
add_instance avl_adxcfg_2 avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n
|
||||
add_connection avl_adxcfg_2.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_2
|
||||
add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2
|
||||
|
||||
add_instance avl_adxcfg_3 avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n
|
||||
add_connection avl_adxcfg_3.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_3
|
||||
add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
add_instance avl_adxcfg_${i} avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n
|
||||
add_connection avl_adxcfg_${i}.rcfg_m0 ad9144_jesd204.phy_reconfig_${i}
|
||||
add_connection avl_adxcfg_${i}.rcfg_m1 ad9680_jesd204.phy_reconfig_${i}
|
||||
}
|
||||
|
||||
# addresses
|
||||
|
||||
ad_cpu_interconnect 0x00020000 avl_ad9144_xcvr.ip_reconfig
|
||||
ad_cpu_interconnect 0x00024000 axi_ad9144_xcvr.s_axi
|
||||
ad_cpu_interconnect 0x00025000 avl_ad9144_xcvr.core_pll_reconfig
|
||||
ad_cpu_interconnect 0x00026000 avl_ad9144_xcvr.lane_pll_reconfig
|
||||
ad_cpu_interconnect 0x00020000 ad9144_jesd204.link_reconfig
|
||||
ad_cpu_interconnect 0x00024000 ad9144_jesd204.link_management
|
||||
ad_cpu_interconnect 0x00025000 ad9144_jesd204.link_pll_reconfig
|
||||
ad_cpu_interconnect 0x00026000 ad9144_jesd204.lane_pll_reconfig
|
||||
ad_cpu_interconnect 0x00028000 avl_adxcfg_0.rcfg_s0
|
||||
ad_cpu_interconnect 0x00029000 avl_adxcfg_1.rcfg_s0
|
||||
ad_cpu_interconnect 0x0002a000 avl_adxcfg_2.rcfg_s0
|
||||
|
|
@ -226,9 +160,9 @@ ad_cpu_interconnect 0x0002b000 avl_adxcfg_3.rcfg_s0
|
|||
ad_cpu_interconnect 0x0002c000 axi_ad9144_dma.s_axi
|
||||
ad_cpu_interconnect 0x00030000 axi_ad9144_core.s_axi
|
||||
|
||||
ad_cpu_interconnect 0x00040000 avl_ad9680_xcvr.ip_reconfig
|
||||
ad_cpu_interconnect 0x00044000 axi_ad9680_xcvr.s_axi
|
||||
ad_cpu_interconnect 0x00045000 avl_ad9680_xcvr.core_pll_reconfig
|
||||
ad_cpu_interconnect 0x00040000 ad9680_jesd204.link_reconfig
|
||||
ad_cpu_interconnect 0x00044000 ad9680_jesd204.link_management
|
||||
ad_cpu_interconnect 0x00045000 ad9680_jesd204.link_pll_reconfig
|
||||
ad_cpu_interconnect 0x00048000 avl_adxcfg_0.rcfg_s1
|
||||
ad_cpu_interconnect 0x00049000 avl_adxcfg_1.rcfg_s1
|
||||
ad_cpu_interconnect 0x0004a000 avl_adxcfg_2.rcfg_s1
|
||||
|
|
@ -243,5 +177,7 @@ ad_dma_interconnect axi_ad9680_dma.m_dest_axi
|
|||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt 8 ad9680_jesd204.interrupt
|
||||
ad_cpu_interrupt 9 ad9144_jesd204.interrupt
|
||||
ad_cpu_interrupt 10 axi_ad9680_dma.interrupt_sender
|
||||
ad_cpu_interrupt 11 axi_ad9144_dma.interrupt_sender
|
||||
|
|
|
|||
Loading…
Reference in New Issue