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util_dac_unpack: Make number of channels and channel width configurable 

Always using 128bit for the input word unnecessarily increases the DMA
alignment requirements. This breaks existing software which assumes that the
DMA alignment requirement is 64bit.

So make it configurable whether we want 8 or 4 channels and while we are at
it also make the channel width configurable.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-09-12 15:53:03 +02:00
parent 61f21a17b3
commit 17a993032b
2 changed files with 169 additions and 752 deletions
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839
library/util_dac_unpack/util_dac_unpack.v
View File

@ -79,751 +79,144 @@ module util_dac_unpack (
dma_rd,
dma_data);
input clk;
parameter CHANNELS = 8; // valid values are 4 and 8
parameter DATA_WIDTH = 16;
localparam DMA_WIDTH = CHANNELS * DATA_WIDTH;
input dac_enable_00;
input dac_valid_00;
output [ 15:0] dac_data_00;
input clk;
input dac_enable_01;
input dac_valid_01;
output [ 15:0] dac_data_01;
input dac_enable_00;
input dac_valid_00;
output [DATA_WIDTH-1:0] dac_data_00;
input dac_enable_02;
input dac_valid_02;
output [ 15:0] dac_data_02;
input dac_enable_01;
input dac_valid_01;
output [DATA_WIDTH-1:0] dac_data_01;
input dac_enable_03;
input dac_valid_03;
output [ 15:0] dac_data_03;
input dac_enable_02;
input dac_valid_02;
output [DATA_WIDTH-1:0] dac_data_02;
input dac_enable_04;
input dac_valid_04;
output [ 15:0] dac_data_04;
input dac_enable_03;
input dac_valid_03;
output [DATA_WIDTH-1:0] dac_data_03;
input dac_enable_05;
input dac_valid_05;
output [ 15:0] dac_data_05;
input dac_enable_04;
input dac_valid_04;
output [DATA_WIDTH-1:0] dac_data_04;
input dac_enable_06;
input dac_valid_06;
output [ 15:0] dac_data_06;
input dac_enable_05;
input dac_valid_05;
output [DATA_WIDTH-1:0] dac_data_05;
input dac_enable_07;
input dac_valid_07;
output [ 15:0] dac_data_07;
input dac_enable_06;
input dac_valid_06;
output [DATA_WIDTH-1:0] dac_data_06;
input fifo_valid;
output dma_rd;
input [127:0] dma_data;
input dac_enable_07;
input dac_valid_07;
output [DATA_WIDTH-1:0] dac_data_07;
wire [3:0] enable_cnt;
wire dac_chan_valid;
input fifo_valid;
output dma_rd;
input [DMA_WIDTH-1:0] dma_data;
wire [ 1:0] position_2;
wire [ 1:0] position_3;
wire [ 2:0] position_4;
wire [ 2:0] position_5;
wire [ 2:0] position_6;
wire [ 2:0] position_7;
reg [ 7:0] path_enabled = 0;
reg [ 7:0] path_enabled_d1 = 0;
reg [ 2:0] counter_0 = 0;
reg [ 2:0] counter_d1 = 0;
reg [ 15:0] dac_data_00 = 16'h0;
reg [ 15:0] dac_data_01 = 16'h0;
reg [ 15:0] dac_data_02 = 16'h0;
reg [ 15:0] dac_data_03 = 16'h0;
reg [ 15:0] dac_data_04 = 16'h0;
reg [ 15:0] dac_data_05 = 16'h0;
reg [ 15:0] dac_data_06 = 16'h0;
reg [ 15:0] dac_data_07 = 16'h0;
reg [127:0] buffer_r = 128'h0;
reg dma_rd = 1'b0;
assign enable_cnt = dac_enable_07 + dac_enable_06 + dac_enable_05 + dac_enable_04 + dac_enable_03 + dac_enable_02 + dac_enable_01 + dac_enable_00;
wire [CHANNELS-1:0] dac_enable;
wire [CHANNELS-1:0] dac_valid;
assign position_2 = dac_enable_00 + dac_enable_01;
assign position_3 = dac_enable_00 + dac_enable_01 + dac_enable_02;
assign position_4 = dac_enable_00 + dac_enable_01 + dac_enable_02 + dac_enable_03;
assign position_5 = dac_enable_00 + dac_enable_01 + dac_enable_02 + dac_enable_03 + dac_enable_04;
assign position_6 = dac_enable_00 + dac_enable_01 + dac_enable_02 + dac_enable_03 + dac_enable_04 + dac_enable_05;
assign position_7 = dac_enable_00 + dac_enable_01 + dac_enable_02 + dac_enable_03 + dac_enable_04 + dac_enable_05 + dac_enable_06;
wire [DATA_WIDTH-1:0] data_array[0:CHANNELS-1];
assign dac_chan_valid = dac_valid_07 | dac_valid_06 | dac_valid_05 | dac_valid_04 | dac_valid_03 | dac_valid_02 | dac_valid_01 | dac_valid_00;
wire [$clog2(CHANNELS)-1:0] offset [0:CHANNELS-1];
wire dac_chan_valid;
always @(enable_cnt)
begin
case(enable_cnt)
4'h1: path_enabled = 8'h01;
4'h2: path_enabled = 8'h02;
4'h4: path_enabled = 8'h08;
4'h8: path_enabled = 8'h80;
default: path_enabled = 8'h0;
endcase
end
reg [DATA_WIDTH*CHANNELS-1:0] dac_data = 'h00;
reg [DMA_WIDTH-1:0] buffer = 'h00;
reg dma_rd = 1'b0;
reg [$clog2(CHANNELS)-1:0] counter = 'h00;
reg [CHANNELS-1:0] dac_enable_d1 = 'h00;
always @(posedge clk)
begin
counter_d1 <= counter_0;
case (path_enabled)
8'h1:
begin
if (counter_0 == 7 && counter_d1 == 6)
begin
dma_rd <= 1'b1;
end
else
begin
dma_rd <= 1'b0;
end
end
8'h02:
begin
if(counter_0 == 6 && counter_d1 == 4)
begin
dma_rd <= 1'b1;
end
else
begin
dma_rd <= 1'b0;
end
end
8'h08:
begin
if(counter_0 == 4 && counter_d1 == 0)
begin
dma_rd <= 1'b1;
end
else
begin
dma_rd <= 1'b0;
end
end
8'h80:
begin
dma_rd <= 1'b1;
end
default : dma_rd <= 1'b0;
endcase
assign dac_enable[0] = dac_enable_00;
assign dac_enable[1] = dac_enable_01;
assign dac_enable[2] = dac_enable_02;
assign dac_enable[3] = dac_enable_03;
assign dac_valid[0] = dac_valid_00;
assign dac_valid[1] = dac_valid_01;
assign dac_valid[2] = dac_valid_02;
assign dac_valid[3] = dac_valid_03;
assign dac_data_00 = dac_data[DATA_WIDTH*1-1:DATA_WIDTH*0];
assign dac_data_01 = dac_data[DATA_WIDTH*2-1:DATA_WIDTH*1];
assign dac_data_02 = dac_data[DATA_WIDTH*3-1:DATA_WIDTH*2];
assign dac_data_03 = dac_data[DATA_WIDTH*4-1:DATA_WIDTH*3];
if (fifo_valid == 1'b1)
begin
buffer_r <= dma_data;
end
end
always @(posedge clk)
begin
path_enabled_d1 <= path_enabled;
if ((path_enabled == 8'h0) || (path_enabled_d1 != path_enabled))
begin
counter_0 <= 3'h0;
generate
if (CHANNELS >= 8) begin
assign dac_enable[4] = dac_enable_04;
assign dac_enable[5] = dac_enable_05;
assign dac_enable[6] = dac_enable_06;
assign dac_enable[7] = dac_enable_07;
assign dac_valid[4] = dac_valid_04;
assign dac_valid[5] = dac_valid_05;
assign dac_valid[6] = dac_valid_06;
assign dac_valid[7] = dac_valid_07;
assign dac_data_04 = dac_data[DATA_WIDTH*5-1:DATA_WIDTH*4];
assign dac_data_05 = dac_data[DATA_WIDTH*6-1:DATA_WIDTH*5];
assign dac_data_06 = dac_data[DATA_WIDTH*7-1:DATA_WIDTH*6];
assign dac_data_07 = dac_data[DATA_WIDTH*8-1:DATA_WIDTH*7];
end
else
endgenerate
function integer enable_reduce;
input n;
integer n;
integer i;
begin
if (dac_chan_valid == 1'b1 )
begin
counter_0 <= counter_0 + enable_cnt;
enable_reduce = 0;
for (i = 0; i < n; i = i + 1)
enable_reduce = enable_reduce + dac_enable[i];
end
endfunction
assign dac_chan_valid = |dac_valid;
always @(posedge clk) begin
if (fifo_valid == 1'b1) begin
buffer <= dma_data;
end
end
always @(posedge clk) begin
dma_rd <= 1'b0;
if (dac_enable != dac_enable_d1) begin
counter <= 'h00;
end else if (dac_chan_valid == 1'b1) begin
counter <= counter + enable_reduce(CHANNELS);
if (counter == 'h00)
dma_rd <= 1'b1;
end
dac_enable_d1 <= dac_enable;
end
generate
genvar i;
for (i = 0; i < CHANNELS; i = i + 1) begin : gen_data_array
assign data_array[i] = buffer[DATA_WIDTH+i*DATA_WIDTH-1:i*DATA_WIDTH];
end
endgenerate
generate
genvar j;
for (j = 0; j < CHANNELS; j = j + 1) begin : gen_dac_data
assign offset[j] = counter + enable_reduce(j);
always @(posedge clk) begin
if (dac_enable[j])
dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= data_array[offset[j]];
else
dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= 'h0000;
end
end
end
always @(posedge clk)
begin
// channel 0
if (dac_enable_00 == 1'b1)
begin
case(counter_0)
0:
begin
dac_data_00 <= buffer_r[15:0];
end
1:
begin
dac_data_00 <= buffer_r[31:16];
end
2:
begin
dac_data_00 <= buffer_r[47:32];
end
3:
begin
dac_data_00 <= buffer_r [63:48];
end
4:
begin
dac_data_00 <= buffer_r [79:64];
end
5:
begin
dac_data_00 <= buffer_r [95:80];
end
6:
begin
dac_data_00 <= buffer_r [111:96];
end
7:
begin
dac_data_00 <= buffer_r [127:112];
end
default:
begin
dac_data_00 <= 16'hdead;
end
endcase
end
else
begin
dac_data_00 <= 16'h0;
end
// channel 1
if (dac_enable_01 == 1'b1)
begin
case (counter_0)
0:
begin
if (dac_enable_00 == 1'b0)
begin
dac_data_01 <= buffer_r[15:0];
end
else
begin
dac_data_01 <= buffer_r[31:16];
end
end
1:
begin
dac_data_01 <= buffer_r[31:16];
end
2:
begin
if (dac_enable_00 == 1'b0 )
begin
dac_data_01 <= buffer_r[47:32];
end
else
begin
dac_data_01 <= buffer_r[63:48];
end
end
3:
begin
dac_data_01 <= buffer_r[63:48];
end
4:
begin
begin
if (dac_enable_00 == 1'b0)
begin
dac_data_01 <= buffer_r[79:64];
end
else
begin
dac_data_01 <= buffer_r[95:80];
end
end
end
5:
begin
dac_data_01 <= buffer_r[95:80];
end
6:
begin
if (path_enabled == 8'h1)
begin
dac_data_01 <= buffer_r [111:96];
end
if (path_enabled == 8'h2)
begin
if (dac_enable_00 == 1'b0)
begin
dac_data_01 <= buffer_r[111:96];
end
else
begin
dac_data_01 <= buffer_r[127:112];
end
end
end
7:
begin
dac_data_01 <= buffer_r[127:112];
end
default:
begin
dac_data_01 <= 16'hdead;
end
endcase
end
else
begin
dac_data_01 <= 16'h0;
end
// channel 2
if (dac_enable_02 == 1'b1)
begin
case (counter_0)
0:
begin
if (position_2 == 2'h00)
begin
dac_data_02 <= buffer_r[15:0];
end
if (position_2 == 2'h01)
begin
dac_data_02 <= buffer_r[31:16];
end
if (position_2 == 2'h02)
begin
dac_data_02 <= buffer_r[47:32];
end
end
1:
begin
dac_data_02 <= buffer_r[31:16];
end
2:
begin
if (position_2 == 2'h00)
begin
dac_data_02 <= buffer_r[47:32];
end
else
begin
dac_data_02 <= buffer_r[63:48];
end
end
3:
begin
dac_data_02 <= buffer_r[63:48];
end
4:
begin
if (position_2 == 2'h00)
begin
dac_data_02 <= buffer_r[79:64];
end
if (position_2 == 2'h01)
begin
dac_data_02 <= buffer_r[95:80];
end
if (position_2 == 2'h02)
begin
dac_data_02 <= buffer_r[111:96];
end
end
5:
begin
dac_data_02 <= buffer_r[95:80];
end
6:
begin
if (position_2 == 2'h00)
begin
dac_data_02 <= buffer_r[111:96];
end
else
begin
dac_data_02 <= buffer_r[127:112];
end
end
7:
begin
dac_data_02 <= buffer_r[127:112];
end
default:
begin
dac_data_02 <= 16'hdead;
end
endcase
end
else
begin
dac_data_02 <= 16'h0;
end
// channel 3
if (dac_enable_03 == 1'b1)
begin
case (counter_0)
0:
begin
if (position_3 == 2'h00)
begin
dac_data_03 <= buffer_r [15:0];
end
if (position_3 == 2'h01)
begin
dac_data_03 <= buffer_r [31:16];
end
if (position_3 == 2'h02)
begin
dac_data_03 <= buffer_r [47:32];
end
if (position_3 == 2'h03)
begin
dac_data_03 <= buffer_r [63:48];
end
end
1:
begin
dac_data_03 <= buffer_r [31:16];
end
2:
begin
if (position_3 == 2'h00)
begin
dac_data_03 <= buffer_r [47:32];
end
else
begin
dac_data_03 <= buffer_r [63:48];
end
end
3:
begin
dac_data_03 <= buffer_r [63:48];
end
4:
begin
if (position_3 == 2'h00)
begin
dac_data_03 <= buffer_r [79:64];
end
if (position_3 == 2'h01)
begin
dac_data_03 <= buffer_r [95:80];
end
if (position_3 == 2'h02)
begin
dac_data_03 <= buffer_r [111:96];
end
if (position_3 == 2'h03)
begin
dac_data_03 <= buffer_r [127:112];
end
end
5:
begin
dac_data_03 <= buffer_r [95:80];
end
6:
begin
if (position_3 == 2'h00)
begin
dac_data_03 <= buffer_r [111:96];
end
else
begin
dac_data_03 <= buffer_r [127:112];
end
end
7:
begin
dac_data_03 <= buffer_r [127:112];
end
default:
begin
dac_data_03 <= 16'hdead;
end
endcase
end
else
begin
dac_data_03 <= 16'h0;
end
// channel 4
if (dac_enable_04 == 1'b1)
begin
case (counter_0)
0:
begin
case (position_4)
0: dac_data_04 <= buffer_r [15:0];
1: dac_data_04 <= buffer_r [31:16];
2: dac_data_04 <= buffer_r [47:32];
3: dac_data_04 <= buffer_r [63:48];
default: dac_data_04 <= buffer_r[79:64];
endcase
end
1:
begin
dac_data_04 <= buffer_r [31:16];
end
2:
begin
if (position_4 == 3'h00)
begin
dac_data_04 <= buffer_r [47:32];
end
else
begin
dac_data_04 <= buffer_r [63:48];
end
end
3:
begin
dac_data_04 <= buffer_r [63:48];
end
4:
begin
case (position_4)
0: dac_data_04 <= buffer_r [79:64];
1: dac_data_04 <= buffer_r [95:80];
2: dac_data_04 <= buffer_r [111:96];
default: dac_data_04 <= buffer_r [127:112];
endcase
end
5:
begin
dac_data_04 <= buffer_r [95:80];
end
6:
begin
if (position_4 == 2'h00)
begin
dac_data_04 <= buffer_r [111:96];
end
else
begin
dac_data_04 <= buffer_r [127:112];
end
end
7:
begin
dac_data_04 <= buffer_r [127:112];
end
default:
begin
dac_data_04 <= 16'hdead;
end
endcase
end
else
begin
dac_data_04 <= 16'h0;
end
// channel 5
if (dac_enable_05 == 1'b1)
begin
case (counter_0)
0:
begin
case (position_5)
0: dac_data_05 <= buffer_r [15:0];
1: dac_data_05 <= buffer_r [31:16];
2: dac_data_05 <= buffer_r [47:32];
3: dac_data_05 <= buffer_r [63:48];
default: dac_data_05 <= buffer_r[95:80];
endcase
end
1:
begin
dac_data_05 <= buffer_r [31:16];
end
2:
begin
if (position_5 == 3'h00)
begin
dac_data_05 <= buffer_r [47:32];
end
else
begin
dac_data_05 <= buffer_r [63:48];
end
end
3:
begin
dac_data_05 <= buffer_r [63:48];
end
4:
begin
case (position_5)
0: dac_data_05 <= buffer_r [79:64];
1: dac_data_05 <= buffer_r [95:80];
2: dac_data_05 <= buffer_r [111:96];
default: dac_data_05 <= buffer_r [127:112];
endcase
end
5:
begin
dac_data_05 <= buffer_r [95:80];
end
6:
begin
if (position_5 == 2'h00)
begin
dac_data_05 <= buffer_r [111:96];
end
else
begin
dac_data_05 <= buffer_r [127:112];
end
end
7:
begin
dac_data_05 <= buffer_r [127:112];
end
default:
begin
dac_data_05 <= 16'hdead;
end
endcase
end
else
begin
dac_data_05 <= 16'h0;
end
// channel 6
if (dac_enable_06 == 1'b1)
begin
case (counter_0)
0:
begin
case (position_6)
0: dac_data_06 <= buffer_r [15:0];
1: dac_data_06 <= buffer_r [31:16];
2: dac_data_06 <= buffer_r [47:32];
3: dac_data_06 <= buffer_r [63:48];
default: dac_data_06 <= buffer_r[111:96];
endcase
end
1:
begin
dac_data_06 <= buffer_r [31:16];
end
2:
begin
if (position_6 == 3'h00)
begin
dac_data_06 <= buffer_r [47:32];
end
else
begin
dac_data_06 <= buffer_r [63:48];
end
end
3:
begin
dac_data_06 <= buffer_r [63:48];
end
4:
begin
case (position_6)
0: dac_data_06 <= buffer_r [79:64];
1: dac_data_06 <= buffer_r [95:80];
2: dac_data_06 <= buffer_r [111:96];
default: dac_data_06 <= buffer_r [127:112];
endcase
end
5:
begin
dac_data_06 <= buffer_r [95:80];
end
6:
begin
if (position_6 == 2'h00)
begin
dac_data_06 <= buffer_r [111:96];
end
else
begin
dac_data_06 <= buffer_r [127:112];
end
end
7:
begin
dac_data_06 <= buffer_r [127:112];
end
default:
begin
dac_data_06 <= 16'hdead;
end
endcase
end
else
begin
dac_data_06 <= 16'h0;
end
// channel 7
if (dac_enable_07 == 1'b1)
begin
case (counter_0)
0:
begin
case (position_7)
0: dac_data_07 <= buffer_r[15:0];
1: dac_data_07 <= buffer_r[31:16];
3: dac_data_07 <= buffer_r[63:48];
default: dac_data_07 <= buffer_r[127:112];
endcase
end
1:
begin
dac_data_07 <= buffer_r [31:16];
end
2:
begin
if (position_7 == 3'h00)
begin
dac_data_07 <= buffer_r [47:32];
end
else
begin
dac_data_07 <= buffer_r [63:48];
end
end
3:
begin
dac_data_07 <= buffer_r [63:48];
end
4:
begin
case (position_7)
0: dac_data_07 <= buffer_r [79:64];
1: dac_data_07 <= buffer_r [95:80];
default: dac_data_07 <= buffer_r [127:112];
endcase
end
5:
begin
dac_data_07 <= buffer_r [95:80];
end
6:
begin
if (position_7 == 2'h00)
begin
dac_data_07 <= buffer_r [111:96];
end
else
begin
dac_data_07 <= buffer_r [127:112];
end
end
7:
begin
dac_data_07 <= buffer_r [127:112];
end
default:
begin
dac_data_07 <= 16'hdead;
end
endcase
end
else
begin
dac_data_07 <= 16'h0;
end
end
endgenerate
endmodule

82
library/util_dac_unpack/util_dac_unpack_hw.tcl
View File

@ -6,6 +6,7 @@ set_module_property NAME util_dac_unpack
set_module_property DESCRIPTION "Util DAC data unpacker"
set_module_property VERSION 1.0
set_module_property DISPLAY_NAME util_dac_unpack
set_module_property ELABORATION_CALLBACK util_dac_unpack_elaborate
# files
@ -13,44 +14,67 @@ add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL util_dac_unpack
add_fileset_file util_dac_unpack.v VERILOG PATH util_dac_unpack.v
add_parameter CHANNELS INTEGER 0
set_parameter_property CHANNELS DEFAULT_VALUE 8
set_parameter_property CHANNELS ALLOWED_RANGES {4 8}
set_parameter_property CHANNELS DESCRIPTION "Valid values are 4 and 8"
set_parameter_property CHANNELS DISPLAY_NAME CHANNELS
set_parameter_property CHANNELS TYPE INTEGER
set_parameter_property CHANNELS UNITS None
set_parameter_property CHANNELS HDL_PARAMETER true
add_parameter DATA_WIDTH INTEGER 0
set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
set_parameter_property DATA_WIDTH TYPE INTEGER
set_parameter_property DATA_WIDTH UNITS None
set_parameter_property DATA_WIDTH HDL_PARAMETER true
add_interface data_clock clock end
add_interface_port data_clock clk clk Input 1
add_interface channels_data conduit end
set_interface_property channels_data associatedClock data_clock
add_interface_port channels_data dac_enable_00 dac_enable_00 Input 1
add_interface_port channels_data dac_valid_00 dac_valid_00 Input 1
add_interface_port channels_data dac_data_00 dac_data_00 Output 16
proc util_dac_unpack_elaborate {} {
set DW [ get_parameter_value DATA_WIDTH ]
set CHAN [ get_parameter_value CHANNELS ]
add_interface_port channels_data dac_enable_01 dac_enable_01 Input 1
add_interface_port channels_data dac_valid_01 dac_valid_01 Input 1
add_interface_port channels_data dac_data_01 dac_data_01 Output 16
add_interface channels_data conduit end
set_interface_property channels_data associatedClock data_clock
add_interface_port channels_data dac_enable_00 dac_enable_00 Input 1
add_interface_port channels_data dac_valid_00 dac_valid_00 Input 1
add_interface_port channels_data dac_data_00 dac_data_00 Output DATA_WIDTH
add_interface_port channels_data dac_enable_02 dac_enable_02 Input 1
add_interface_port channels_data dac_valid_02 dac_valid_02 Input 1
add_interface_port channels_data dac_data_02 dac_data_02 Input 16
add_interface_port channels_data dac_enable_01 dac_enable_01 Input 1
add_interface_port channels_data dac_valid_01 dac_valid_01 Input 1
add_interface_port channels_data dac_data_01 dac_data_01 Output DATA_WIDTH
add_interface_port channels_data dac_enable_03 dac_enable_03 Input 1
add_interface_port channels_data dac_valid_03 dac_valid_03 Input 1
add_interface_port channels_data dac_data_03 dac_data_03 Input 16
add_interface_port channels_data dac_enable_02 dac_enable_02 Input 1
add_interface_port channels_data dac_valid_02 dac_valid_02 Input 1
add_interface_port channels_data dac_data_02 dac_data_02 Output DATA_WIDTH
add_interface_port channels_data dac_enable_04 dac_enable_04 Input 1
add_interface_port channels_data dac_valid_04 dac_valid_04 Input 1
add_interface_port channels_data dac_data_04 dac_data_04 Input 16
add_interface_port channels_data dac_enable_03 dac_enable_03 Input 1
add_interface_port channels_data dac_valid_03 dac_valid_03 Input 1
add_interface_port channels_data dac_data_03 dac_data_03 Output DATA_WIDTH
add_interface_port channels_data dac_enable_05 dac_enable_05 Input 1
add_interface_port channels_data dac_valid_05 dac_valid_05 Input 1
add_interface_port channels_data dac_data_05 dac_data_05 Input 16
if {$CHAN == 8} {
add_interface_port channels_data dac_enable_04 dac_enable_04 Input 1
add_interface_port channels_data dac_valid_04 dac_valid_04 Input 1
add_interface_port channels_data dac_data_04 dac_data_04 Output DATA_WIDTH
add_interface_port channels_data dac_enable_06 dac_enable_06 Input 1
add_interface_port channels_data dac_valid_06 dac_valid_06 Input 1
add_interface_port channels_data dac_data_06 dac_data_06 Input 16
add_interface_port channels_data dac_enable_05 dac_enable_05 Input 1
add_interface_port channels_data dac_valid_05 dac_valid_05 Input 1
add_interface_port channels_data dac_data_05 dac_data_05 Output DATA_WIDTH
add_interface_port channels_data dac_enable_07 dac_enable_07 Input 1
add_interface_port channels_data dac_valid_07 dac_valid_07 Input 1
add_interface_port channels_data dac_data_07 dac_data_07 Input 16
add_interface_port channels_data dac_enable_06 dac_enable_06 Input 1
add_interface_port channels_data dac_valid_06 dac_valid_06 Input 1
add_interface_port channels_data dac_data_06 dac_data_06 Output DATA_WIDTH
add_interface_port channels_data fifo_valid fifo_valid Input 1
add_interface_port channels_data dma_rd dma_rd Output 1
add_interface_port channels_data dma_data dma_data Input 128
add_interface_port channels_data dac_enable_07 dac_enable_07 Input 1
add_interface_port channels_data dac_valid_07 dac_valid_07 Input 1
add_interface_port channels_data dac_data_07 dac_data_07 Output DATA_WIDTH
}
add_interface_port channels_data fifo_valid fifo_valid Input 1
add_interface_port channels_data dma_rd dma_rd Output 1
add_interface_port channels_data dma_data dma_data Input [expr {$DW * $CHAN}]
}