diff --git a/library/common/ad_mem_asym.v b/library/common/ad_mem_asym.v
index c28678fd8..1ebb6ded5 100644
--- a/library/common/ad_mem_asym.v
+++ b/library/common/ad_mem_asym.v
@@ -43,7 +43,8 @@ module ad_mem_asym #(
   parameter   A_ADDRESS_WIDTH =  8,
   parameter   A_DATA_WIDTH = 256,
   parameter   B_ADDRESS_WIDTH =   10,
-  parameter   B_DATA_WIDTH =  64) (
+  parameter   B_DATA_WIDTH =  64,
+  parameter   CASCADE_HEIGHT = -1) (
 
   input                             clka,
   input                             wea,
@@ -82,7 +83,7 @@ module ad_mem_asym #(
 
   // internal registers
 
-  (* ram_style = "block" *)
+  (* ram_style = "block", cascade_height = CASCADE_HEIGHT *)
   reg      [MEM_DATA_WIDTH-1:0]    m_ram[0:MEM_SIZE-1];
 
   //---------------------------------------------------------------------------
diff --git a/projects/common/xilinx/data_offload_bd.tcl b/projects/common/xilinx/data_offload_bd.tcl
index 4b5519b4f..567c8faf8 100644
--- a/projects/common/xilinx/data_offload_bd.tcl
+++ b/projects/common/xilinx/data_offload_bd.tcl
@@ -71,6 +71,7 @@ proc ad_data_offload_create {instance_name
         CONFIG.A_ADDRESS_WIDTH $source_awidth \
         CONFIG.B_DATA_WIDTH $destination_dwidth \
         CONFIG.B_ADDRESS_WIDTH $destination_awidth \
+        CONFIG.CASCADE_HEIGHT 1 \
       ] [get_bd_cells storage_unit]
 
       ad_connect storage_unit/clka i_data_offload/s_axis_aclk