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ad_mem_asym: Add option to control cascade layout 

Signed-off-by: David Winter <david.winter@analog.com>
main
David Winter 2021-06-17 15:14:20 +02:00 committed by Adrian Costina
parent 12b7fbb3a3
commit 1766b42a93
2 changed files with 4 additions and 2 deletions
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5
library/common/ad_mem_asym.v
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@ -43,7 +43,8 @@ module ad_mem_asym #(
parameter A_ADDRESS_WIDTH = 8,
parameter A_DATA_WIDTH = 256,
parameter B_ADDRESS_WIDTH = 10,
parameter B_DATA_WIDTH = 64) (
parameter B_DATA_WIDTH = 64,
parameter CASCADE_HEIGHT = -1) (
input clka,
input wea,
@ -82,7 +83,7 @@ module ad_mem_asym #(
// internal registers
(* ram_style = "block" *)
(* ram_style = "block", cascade_height = CASCADE_HEIGHT *)
reg [MEM_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1];
//---------------------------------------------------------------------------

1
projects/common/xilinx/data_offload_bd.tcl
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@ -71,6 +71,7 @@ proc ad_data_offload_create {instance_name
CONFIG.A_ADDRESS_WIDTH $source_awidth \
CONFIG.B_DATA_WIDTH $destination_dwidth \
CONFIG.B_ADDRESS_WIDTH $destination_awidth \
CONFIG.CASCADE_HEIGHT 1 \
] [get_bd_cells storage_unit]
ad_connect storage_unit/clka i_data_offload/s_axis_aclk